(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 8481beab2383360027623297ec01b8c35100946f..04d3546a829ac42c52cb842aa87d494dc241cba7 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -61,14 +61,15 @@ an arbitrary indeterminate number of Conditional tests is impossible
 to define, and efforts to enforce such defined behaviour interfere with
 Vertical-First mode parallel opportunistic behaviour.*)
 
-In `svstep` mode, the whole CR Field, part of which is selected by `BI`
-(top 3 bits), is tested based on incrementing srcstep and dststep, and
-performing the same tests as [[sv/svstep]]. Following the step update,
-(which when Rc=1 involved writing to the exact CR Field about to be tested), the
+In `svstep` mode, srcstep and dststep are incremented, and then
+tested exactly as in  [[sv/svstep]]. When Rc=1 the test results
+are wtitten into the whole CR Field (the exact same one
+about to be tested by the Branch Condition). Following the svstep
+update, the
 Branch Conditional instruction proceeds as normal (reading and testing
 the CR bit just updated, if the relevant `BO` bit is set).  Note that
-the SVSTATE fields are still updated, and the CR field still updated,
-even if `BO[0]` is set.
+the SVSTATE srcstep and dststep fields are still updated
+and the CR field still updated, even if `BO[0]` is set.
 
 Predication in both INT and CR modes may be applied to `sv.bc` and other
 SVP64 Branch Conditional operations, exactly as they may be applied to