Tidy up

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index ece45db792a8f7be2733c75053fd262297130a99..d2e68987b8d711a5c41231c6aa1b23c678c1d42d 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -32,40 +32,32 @@ module \$mul (A, B, Y);
        input [B_WIDTH-1:0] B;\r
        output [Y_WIDTH-1:0] Y;\r
 \r
-       wire [1023:0] _TECHMAP_DO_ = "proc; clean";\r
-\r
-  generate\r
-    if (A_WIDTH<B_WIDTH) begin\r
-       generate\r
-               \$__mul_gen #(\r
-                       .A_SIGNED(A_SIGNED),\r
-                       .B_SIGNED(B_SIGNED),\r
-                       .A_WIDTH(A_WIDTH),\r
-                       .B_WIDTH(B_WIDTH),\r
-                       .Y_WIDTH(Y_WIDTH)\r
-               ) mul_slice (\r
-                       .A(A),\r
-                       .B(B),\r
-                       .Y(Y[Y_WIDTH-1:0])\r
-               );\r
-       endgenerate\r
-       end\r
-    else begin\r
        generate\r
-               \$__mul_gen #(\r
-                       .A_SIGNED(B_SIGNED),\r
-                       .B_SIGNED(A_SIGNED),\r
-                       .A_WIDTH(B_WIDTH),\r
-                       .B_WIDTH(A_WIDTH),\r
-                       .Y_WIDTH(Y_WIDTH)\r
-               ) mul_slice (\r
-                       .A(B),\r
-                       .B(A),\r
-                       .Y(Y[Y_WIDTH-1:0])\r
-               );\r
+               if (A_WIDTH < B_WIDTH)\r
+                       \$__mul_gen #(\r
+                               .A_SIGNED(A_SIGNED),\r
+                               .B_SIGNED(B_SIGNED),\r
+                               .A_WIDTH(A_WIDTH),\r
+                               .B_WIDTH(B_WIDTH),\r
+                               .Y_WIDTH(Y_WIDTH)\r
+                       ) mul_slice (\r
+                               .A(A),\r
+                               .B(B),\r
+                               .Y(Y)\r
+                       );\r
+               else\r
+                       \$__mul_gen #(\r
+                               .A_SIGNED(B_SIGNED),\r
+                               .B_SIGNED(A_SIGNED),\r
+                               .A_WIDTH(B_WIDTH),\r
+                               .B_WIDTH(A_WIDTH),\r
+                               .Y_WIDTH(Y_WIDTH)\r
+                       ) mul_slice (\r
+                               .A(B),\r
+                               .B(A),\r
+                               .Y(Y)\r
+                       );\r
        endgenerate\r
-     end\r
-   endgenerate \r
 endmodule\r
 \r
 module \$__mul_gen (A, B, Y);\r
@@ -81,8 +73,9 @@ module \$__mul_gen (A, B, Y);
 \r
        wire [1023:0] _TECHMAP_DO_ = "proc; clean";\r
 \r
+       genvar i;\r
        generate\r
-       if (A_WIDTH > `DSP_A_MAXWIDTH) begin\r
+               if (A_WIDTH > `DSP_A_MAXWIDTH) begin\r
                        localparam n_floored = A_WIDTH/`DSP_A_MAXWIDTH;\r
                        localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0);\r
                        wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1];\r
@@ -101,8 +94,6 @@ module \$__mul_gen (A, B, Y);
                        );\r
                         assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0;\r
 \r
-                       genvar i;\r
-                       generate\r
                        for (i = 1; i < n-1; i=i+1) begin:slice\r
                                \$__mul_gen #(\r
                                        .A_SIGNED(A_SIGNED),\r
@@ -122,7 +113,6 @@ module \$__mul_gen (A, B, Y);
                                        partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0]\r
                                };\r
                        end\r
-                       endgenerate\r
 \r
                        \$__mul_gen #(\r
                                .A_SIGNED(A_SIGNED),\r
@@ -161,8 +151,6 @@ module \$__mul_gen (A, B, Y);
                        );\r
                         assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0;\r
 \r
-                       genvar i;\r
-                       generate\r
                        for (i = 1; i < n-1; i=i+1) begin:slice\r
                                \$__mul_gen #(\r
                                        .A_SIGNED(A_SIGNED),\r
@@ -187,7 +175,6 @@ module \$__mul_gen (A, B, Y);
                                        partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0] \r
                                };\r
                        end\r
-                       endgenerate\r
 \r
                        \$__mul_gen #(\r
                                .A_SIGNED(A_SIGNED),\r