X86: Implement LDMXCSR.

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 5d817d2c20cb81e2bb6d5d4e5cae783d701d2c05..dabc1bb75a0abf3a9d625eae21a33b8ea30ad71c 100644 (file)
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -828,7 +828,7 @@
                 0x6: decode MODRM_REG {
                     0x0: fxsave();
                     0x1: fxrstor();
-                    0x2: ldmxcsr();
+                    0x2: Inst::LDMXCSR(Md);
                     0x3: Inst::STMXCSR(Md);
                     0x4: Inst::UD2();
                     0x5: decode MODRM_MOD {

diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
index 831a266c79003999922cc9d0fecf96d38a82a4a5..2481b744f913014c21e9443cced031e726bcfec0 100644 (file)
--- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
+++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
@@ -64,5 +64,15 @@ def macroop STMXCSR_P {
     rdip t7
     st t1, seg, riprel, disp
 };
-# LDMXCSR
+
+def macroop LDMXCSR_M {
+    ld t1, seg, sib, disp
+    wrval "InstRegIndex(MISCREG_MXCSR)", t1
+};
+
+def macroop LDMXCSR_P {
+    rdip t7
+    ld t1, seg, riprel, disp
+    wrval "InstRegIndex(MISCREG_MXCSR)", t1
+};
 '''