arch-arm: R/W interface to AArch32 HCR2 misc reg

This patch implements read/write interfaces to HCR2 AArch32 register,
which is mapped to the upper 32 bits of HCR_EL2.

Change-Id: I996023f3ad8233457d19de8a506ebcf106409165
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22832
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 712b430406c4a9dd07263a1b7edb0210bce77c4f..14cc993d1ce30a590a7d55afa9d99b4ed622e6c8 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -479,12 +479,10 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
 
     switch (unflattenMiscReg(misc_reg)) {
       case MISCREG_HCR:
-        {
+      case MISCREG_HCR2:
             if (!haveVirtualization)
                 return 0;
-            else
-                return readMiscRegNoEffect(MISCREG_HCR);
-        }
+            break;
       case MISCREG_CPACR:
         {
             const uint32_t ones = (uint32_t)(-1);
@@ -1028,11 +1026,10 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
             }
             break;
           case MISCREG_HCR:
-            {
+          case MISCREG_HCR2:
                 if (!haveVirtualization)
                     return;
-            }
-            break;
+                break;
           case MISCREG_IFSR:
             {
                 // ARM ARM (ARM DDI 0406C.b) B4.1.96

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index bffb4446ab27d6258e35f63af0e48cb619b759b9..787ba2fafa7153c90c5803cacfcae47feeacb4bf 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -257,6 +257,8 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
                     return MISCREG_HDCR;
                   case 2:
                     return MISCREG_HCPTR;
+                  case 4:
+                    return MISCREG_HCR2;
                   case 3:
                     return MISCREG_HSTR;
                   case 7:
@@ -3215,7 +3217,11 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_HACTLR)
       .hyp().monNonSecure();
     InitReg(MISCREG_HCR)
-      .hyp().monNonSecure();
+      .hyp().monNonSecure()
+      .res0(0x90000000);
+    InitReg(MISCREG_HCR2)
+      .hyp().monNonSecure()
+      .res0(0xffa9ff8c);
     InitReg(MISCREG_HDCR)
       .hyp().monNonSecure();
     InitReg(MISCREG_HCPTR)
@@ -4003,7 +4009,7 @@ ISA::initializeMiscRegMetadata()
       .mapsTo(MISCREG_HACTLR);
     InitReg(MISCREG_HCR_EL2)
       .hyp().mon()
-      .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
+      .mapsTo(MISCREG_HCR, MISCREG_HCR2);
     InitReg(MISCREG_MDCR_EL2)
       .hyp().mon()
       .mapsTo(MISCREG_HDCR);

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 3ce371bfe531ecfcece30db789f8a070d52eebca..4f522f298b8ce05e563ba965fc669516e63c2577 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -182,6 +182,7 @@ namespace ArmISA
         MISCREG_HSCTLR,
         MISCREG_HACTLR,
         MISCREG_HCR,
+        MISCREG_HCR2,
         MISCREG_HDCR,
         MISCREG_HCPTR,
         MISCREG_HSTR,
@@ -1127,6 +1128,7 @@ namespace ArmISA
         "hsctlr",
         "hactlr",
         "hcr",
+        "hcr2",
         "hdcr",
         "hcptr",
         "hstr",

diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index 0d6775ec97b5ca5506dd8ba2b8ad5c63102d9752..20265e29463aa518177522689c326643a4526399 100644 (file)
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -234,8 +234,8 @@ namespace ArmISA
 
     BitUnion64(HCR)
         Bitfield<34>     e2h;   // AArch64
-        Bitfield<33>     id;    // AArch64
-        Bitfield<32>     cd;    // AArch64
+        Bitfield<33>     id;
+        Bitfield<32>     cd;
         Bitfield<31>     rw;    // AArch64
         Bitfield<30>     trvm;  // AArch64
         Bitfield<29>     hcd;   // AArch64

diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc
index ce2300ed553f4e5b1c7fdc36f8f157dd5b3d4cdf..1495c7a7424dc3dfa095e233290ab315f986d6f2 100644 (file)
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -168,6 +168,7 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
     { "hsctlr", MISCREG_HSCTLR },
     { "hactlr", MISCREG_HACTLR },
     { "hcr", MISCREG_HCR },
+    { "hcr2", MISCREG_HCR2 },
     { "hdcr", MISCREG_HDCR },
     { "hcptr", MISCREG_HCPTR },
     { "hstr", MISCREG_HSTR },