sorted out order of FPMULADD32 helper, only have rounding errors now

diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index 134ef84af8f67c018274a17f2cbe409a15302649..3549516a3709a2f639cfdfda14d1349e885ee18d 100644 (file)
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -289,7 +289,7 @@ def FPMUL32(FRA, FRB):
     return cvt
 
 
-def FPMULADD32(FRA, FRC, FRB, addsign, mulsign):
+def FPMULADD32(FRA, FRC, FRB, mulsign, addsign):
     from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
     #return FPMUL64(FRA, FRB)
     #FRA = DOUBLE(SINGLE(FRA))
@@ -298,12 +298,12 @@ def FPMULADD32(FRA, FRC, FRB, addsign, mulsign):
         if mulsign == 1:
             result = float(FRA) * float(FRC) + float(FRB) # fmadds
         elif mulsign == -1:
-            result = -(float(FRA) * float(FRC) + float(FRB))  # fnmadds
+            result = -(float(FRA) * float(FRC) - float(FRB))  # fnmsubs
     elif addsign == -1:
         if mulsign == 1:
             result = float(FRA) * float(FRC) - float(FRB) # fmsubs
         elif mulsign == -1:
-            result = -(float(FRA) * float(FRC) - float(FRB))  # fnmsubs
+            result = -(float(FRA) * float(FRC) + float(FRB))  # fnmadds
     elif addsign == 0:
         result = 0.0
     log ("FPMULADD32", FRA, FRB, FRC,