dev/etherlink.cc
dev/etherpkt.cc
dev/ethertap.cc
+ dev/i8254xGBe.cc
dev/ide_ctrl.cc
dev/ide_disk.cc
dev/io_device.cc
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/* @file
+ * Device model for Intel's 8254x line of gigabit ethernet controllers.
+ */
+
+#include "base/inet.hh"
+#include "dev/i8254xGBe.hh"
+#include "mem/packet.hh"
+#include "sim/builder.hh"
+#include "sim/stats.hh"
+#include "sim/system.hh"
+
+IGbE::IGbE(Params *p)
+ : PciDev(p), etherInt(NULL)
+{
+
+}
+
+
+Tick
+IGbE::writeConfig(Packet *pkt)
+{
+ int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
+ if (offset < PCI_DEVICE_SPECIFIC)
+ PciDev::writeConfig(pkt);
+ else
+ panic("Device specific PCI config space not implemented.\n");
+
+ ///
+ /// Some work may need to be done here based for the pci COMMAND bits.
+ ///
+
+ return pioDelay;
+}
+
+Tick
+IGbE::read(Packet *pkt)
+{
+ int bar;
+ Addr daddr;
+
+ if (!getBAR(pkt->getAddr(), bar, daddr))
+ panic("Invalid PCI memory access to unmapped memory.\n");
+
+ // Only Memory register BAR is allowed
+ assert(bar == 0);
+
+ DPRINTF(Ethernet, "Accessed devie register %#X\n", daddr);
+
+ pkt->allocate();
+
+
+ ///
+ /// Handle read of register here
+ ///
+
+ pkt->result = Packet::Success;
+ return pioDelay;
+}
+
+Tick
+IGbE::write(Packet *pkt)
+{
+ int bar;
+ Addr daddr;
+
+ if (!getBAR(pkt->getAddr(), bar, daddr))
+ panic("Invalid PCI memory access to unmapped memory.\n");
+
+ // Only Memory register BAR is allowed
+ assert(bar == 0);
+
+ DPRINTF(Ethernet, "Accessed devie register %#X\n", daddr);
+
+ ///
+ /// Handle write of register here
+ ///
+
+ pkt->result = Packet::Success;
+ return pioDelay;
+}
+
+
+bool
+IGbE::ethRxPkt(EthPacketPtr packet)
+{
+ panic("Need to implemenet\n");
+}
+
+
+void
+IGbE::ethTxDone()
+{
+ panic("Need to implemenet\n");
+}
+
+void
+IGbE::serialize(std::ostream &os)
+{
+ panic("Need to implemenet\n");
+}
+
+void
+IGbE::unserialize(Checkpoint *cp, const std::string §ion)
+{
+ panic("Need to implemenet\n");
+}
+
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
+
+ SimObjectParam<EtherInt *> peer;
+ SimObjectParam<IGbE *> device;
+
+END_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(IGbEInt)
+
+ INIT_PARAM_DFLT(peer, "peer interface", NULL),
+ INIT_PARAM(device, "Ethernet device of this interface")
+
+END_INIT_SIM_OBJECT_PARAMS(IGbEInt)
+
+CREATE_SIM_OBJECT(IGbEInt)
+{
+ IGbEInt *dev_int = new IGbEInt(getInstanceName(), device);
+
+ EtherInt *p = (EtherInt *)peer;
+ if (p) {
+ dev_int->setPeer(p);
+ p->setPeer(dev_int);
+ }
+
+ return dev_int;
+}
+
+REGISTER_SIM_OBJECT("IGbEInt", IGbEInt)
+
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE)
+
+ SimObjectParam<System *> system;
+ SimObjectParam<Platform *> platform;
+ SimObjectParam<PciConfigData *> configdata;
+ Param<uint32_t> pci_bus;
+ Param<uint32_t> pci_dev;
+ Param<uint32_t> pci_func;
+ Param<Tick> pio_latency;
+ Param<Tick> config_latency;
+
+END_DECLARE_SIM_OBJECT_PARAMS(IGbE)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE)
+
+ INIT_PARAM(system, "System pointer"),
+ INIT_PARAM(platform, "Platform pointer"),
+ INIT_PARAM(configdata, "PCI Config data"),
+ INIT_PARAM(pci_bus, "PCI bus ID"),
+ INIT_PARAM(pci_dev, "PCI device number"),
+ INIT_PARAM(pci_func, "PCI function code"),
+ INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
+ INIT_PARAM(config_latency, "Number of cycles for a config read or write")
+
+END_INIT_SIM_OBJECT_PARAMS(IGbE)
+
+
+CREATE_SIM_OBJECT(IGbE)
+{
+ IGbE::Params *params = new IGbE::Params;
+
+ params->name = getInstanceName();
+ params->platform = platform;
+ params->system = system;
+ params->configData = configdata;
+ params->busNum = pci_bus;
+ params->deviceNum = pci_dev;
+ params->functionNum = pci_func;
+ params->pio_delay = pio_latency;
+ params->config_delay = config_latency;
+
+ return new IGbE(params);
+}
+
+REGISTER_SIM_OBJECT("IGbE", IGbE)
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/* @file
+ * Device model for Intel's 8254x line of gigabit ethernet controllers.
+ */
+
+#ifndef __DEV_I8254XGBE_HH__
+#define __DEV_I8254XGBE_HH__
+
+#include "base/inet.hh"
+#include "base/statistics.hh"
+#include "dev/etherint.hh"
+#include "dev/etherpkt.hh"
+#include "dev/pcidev.hh"
+#include "dev/pktfifo.hh"
+#include "sim/eventq.hh"
+
+class IGbEInt;
+
+class IGbE : public PciDev
+{
+ private:
+ IGbEInt *etherInt;
+
+ public:
+ struct Params : public PciDev::Params
+ {
+ ;
+ };
+
+ IGbE(Params *params);
+ ~IGbE() {;}
+
+ virtual Tick read(Packet *pkt);
+ virtual Tick write(Packet *pkt);
+
+ virtual Tick writeConfig(Packet *pkt);
+
+ bool ethRxPkt(EthPacketPtr packet);
+ void ethTxDone();
+
+ void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
+
+ const Params *params() const {return (const Params *)_params; }
+
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string §ion);
+
+
+};
+
+class IGbEInt : public EtherInt
+{
+ private:
+ IGbE *dev;
+
+ public:
+ IGbEInt(const std::string &name, IGbE *d)
+ : EtherInt(name), dev(d)
+ { dev->setEthInt(this); }
+
+ virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
+ virtual void sendDone() { dev->ethTxDone(); }
+};
+
+
+
+
+
+#endif //__DEV_I8254XGBE_HH__
+
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/* @file
+ * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers.
+ */
+
+namespace iGbReg {
+
+const uint32_t CTRL = 0x00000;
+const uint32_t STATUS = 0x00008;
+const uint32_t EECD = 0x00010;
+const uint32_t CTRL_EXT = 0x00018;
+const uint32_t PBA = 0x01000;
+const uint32_t ICR = 0x000C0;
+const uint32_t ITR = 0x000C4;
+const uint32_t ICS = 0x000C8;
+const uint32_t IMS = 0x000D0;
+const uint32_t IMC = 0x000D8;
+const uint32_t RCTL = 0x00100;
+const uint32_t RDBAL = 0x02800;
+const uint32_t RDBAH = 0x02804;
+const uint32_t RDLEN = 0x02808;
+const uint32_t RDH = 0x02810;
+const uint32_t RDT = 0x02818;
+const uint32_t RDTR = 0x02820;
+const uint32_t RADV = 0x0282C;
+const uint32_t RSRPD = 0x02C00;
+const uint32_t TCTL = 0x00400;
+const uint32_t TDBAL = 0x03800;
+const uint32_t TDBAH = 0x03804;
+const uint32_t TDLEN = 0x03808;
+const uint32_t TDH = 0x03810;
+const uint32_t THT = 0x03818;
+const uint32_t TIDV = 0x03820;
+const uint32_t TXDMAC = 0x03000;
+const uint32_t TXDCTL = 0x03828;
+const uint32_t TADV = 0x0282C;
+const uint32_t TSPMT = 0x03830;
+const uint32_t RXDCTL = 0x02828;
+const uint32_t RXCSUM = 0x05000;
+
+struct RxDesc {
+ Addr buf;
+ uint16_t len;
+ uint16_t csum;
+ union {
+ uint8_t status;
+ struct { // these may be in the worng order
+ uint8_t dd:1; // descriptor done (hw is done when 1)
+ uint8_t eop:1; // end of packet
+ uint8_t xism:1; // ignore checksum
+ uint8_t vp:1; // packet is vlan packet
+ uint8_t rsv:1; // reserved
+ uint8_t tcpcs:1; // TCP checksum done
+ uint8_t ipcs:1; // IP checksum done
+ uint8_t pif:1; // passed in-exact filter
+ } st;
+ };
+ union {
+ uint8_t errors;
+ struct {
+ uint8_t ce:1; // crc error or alignment error
+ uint8_t se:1; // symbol error
+ uint8_t seq:1; // sequence error
+ uint8_t rsv:1; // reserved
+ uint8_t cxe:1; // carrier extension error
+ uint8_t tcpe:1; // tcp checksum error
+ uint8_t ipe:1; // ip checksum error
+ uint8_t rxe:1; // PX data error
+ } er;
+ };
+ union {
+ uint16_t special;
+ struct {
+ uint16_t vlan:12; //vlan id
+ uint16_t cfi:1; // canocial form id
+ uint16_t pri:3; // user priority
+ } sp;
+ };
+};
+
+union TxDesc {
+ uint8_t data[16];
+ struct {
+ Addr buf;
+ uint16_t len;
+ uint8_t cso;
+ union {
+ uint8_t command;
+ struct {
+ uint8_t eop:1; // end of packet
+ uint8_t ifcs:1; // insert crc
+ uint8_t ic:1; // insert checksum
+ uint8_t rs:1; // report status
+ uint8_t rps:1; // report packet sent
+ uint8_t dext:1; // extension
+ uint8_t vle:1; // vlan enable
+ uint8_t ide:1; // interrupt delay enable
+ } cmd;
+ };
+ union {
+ uint8_t status:4;
+ struct {
+ uint8_t dd:1; // descriptor done
+ uint8_t ec:1; // excess collisions
+ uint8_t lc:1; // late collision
+ uint8_t tu:1; // transmit underrun
+ } st;
+ };
+ uint8_t reserved:4;
+ uint8_t css;
+ union {
+ uint16_t special;
+ struct {
+ uint16_t vlan:12; //vlan id
+ uint16_t cfi:1; // canocial form id
+ uint16_t pri:3; // user priority
+ } sp;
+ };
+ } legacy;
+
+ // Type 0000 descriptor
+ struct {
+ uint8_t ipcss;
+ uint8_t ipcso;
+ uint16_t ipcse;
+ uint8_t tucss;
+ uint8_t tucso;
+ uint16_t tucse;
+ uint32_t paylen:20;
+ uint8_t dtype:4;
+ union {
+ uint8_t tucommand;
+ struct {
+ uint8_t tcp:1; // tcp/udp
+ uint8_t ip:1; // ip ipv4/ipv6
+ uint8_t tse:1; // tcp segment enbale
+ uint8_t rs:1; // report status
+ uint8_t rsv0:1; // reserved
+ uint8_t dext:1; // descriptor extension
+ uint8_t rsv1:1; // reserved
+ uint8_t ide:1; // interrupt delay enable
+ } tucmd;
+ };
+ union {
+ uint8_t status:4;
+ struct {
+ uint8_t dd:1;
+ uint8_t rsvd:3;
+ } sta;
+ };
+ uint8_t reserved:4;
+ uint8_t hdrlen;
+ uint16_t mss;
+ } t0;
+
+ // Type 0001 descriptor
+ struct {
+ Addr buf;
+ uint32_t dtalen:20;
+ uint8_t dtype:4;
+ union {
+ uint8_t dcommand;
+ struct {
+ uint8_t eop:1; // end of packet
+ uint8_t ifcs:1; // insert crc
+ uint8_t tse:1; // segmentation enable
+ uint8_t rs:1; // report status
+ uint8_t rps:1; // report packet sent
+ uint8_t dext:1; // extension
+ uint8_t vle:1; // vlan enable
+ uint8_t ide:1; // interrupt delay enable
+ } dcmd;
+ };
+ union {
+ uint8_t status:4;
+ struct {
+ uint8_t dd:1; // descriptor done
+ uint8_t ec:1; // excess collisions
+ uint8_t lc:1; // late collision
+ uint8_t tu:1; // transmit underrun
+ } sta;
+ };
+ union {
+ uint8_t pktopts;
+ struct {
+ uint8_t ixsm:1; // insert ip checksum
+ uint8_t txsm:1; // insert tcp checksum
+ };
+ };
+ union {
+ uint16_t special;
+ struct {
+ uint16_t vlan:12; //vlan id
+ uint16_t cfi:1; // canocial form id
+ uint16_t pri:3; // user priority
+ } sp;
+ };
+ } t1;
+
+ // Junk to test descriptor type!
+ struct {
+ uint64_t junk;
+ uint32_t junk1:20;
+ uint8_t dtype;
+ uint8_t junk2:5;
+ uint8_t dext:1;
+ uint8_t junk3:2;
+ uint8_t junk4:4;
+ uint32_t junk5;
+ } type;
+};
+
+}; // iGbReg namespace
data->config.baseAddr[5] = htole(BAR5);
data->config.cardbusCIS = htole(CardbusCIS);
data->config.subsystemVendorID = htole(SubsystemVendorID);
- data->config.subsystemID = htole(SubsystemVendorID);
+ data->config.subsystemID = htole(SubsystemID);
data->config.expansionROM = htole(ExpansionROM);
data->config.interruptLine = htole(InterruptLine);
data->config.interruptPin = htole(InterruptPin);
type = 'EtherDevInt'
device = Param.EtherDev("Ethernet device of this interface")
+
+class IGbE(PciDevice):
+ type = 'IGbE'
+ hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address")
+
+class IGbEPciData(PciConfigData):
+ VendorID = 0x8086
+ DeviceID = 0x1026
+ SubsystemID = 0x1008
+ SubsystemVendorID = 0x8086
+ Status = 0x0000
+ SubClassCode = 0x00
+ ClassCode = 0x02
+ ProgIF = 0x00
+ BAR0 = 0x00000000
+ BAR1 = 0x00000000
+ BAR2 = 0x00000000
+ BAR3 = 0x00000000
+ BAR4 = 0x00000000
+ BAR5 = 0x00000000
+ MaximumLatency = 0x00
+ MinimumGrant = 0xff
+ InterruptLine = 0x1e
+ InterruptPin = 0x01
+ BAR0Size = '128kB'
+
+class IGbEInt(EtherInt):
+ type = 'IGbEInt'
+ device = Param.IGbE("Ethernet device of this interface")
+
+
+
class EtherDevBase(PciDevice):
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
clock = Param.Clock('0ns', "State machine processor frequency")
- config_latency = Param.Latency('20ns', "Config read or write latency")
-
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
type = 'IdeController'
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
- config_latency = Param.Latency('20ns', "Config read or write latency")
-
configdata =IdeControllerPciData()
pci_func = Param.Int("PCI function code")
pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
configdata = Param.PciConfigData(Parent.any, "PCI Config data")
+ config_latency = Param.Latency('20ns', "Config read or write latency")
class PciFake(PciDevice):
type = 'PciFake'
projects / gem5.git / commitdiff