inorder: ISA-zero reg handling

ignore writes to the ISA zero register

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 01eab9af7dfb26e41fb06824e6833a55c75c79c3..f1c531c534f7b3cb1ef39a056ddc5f9f834437a5 100644 (file)
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -1135,10 +1135,16 @@ InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
 void
 InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
 {
-    DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
-            tid, reg_idx, val);
+    if (reg_idx == TheISA::ZeroReg) {
+        DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
+                "(Int. Reg %i) to %x\n", tid, reg_idx, val);
+        return;
+    } else {
+        DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
+                tid, reg_idx, val);
 
-    intRegs[tid][reg_idx] = val;
+        intRegs[tid][reg_idx] = val;
+    }
 }