split out instructions from openpower/isa/fixedload.mdwn

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 9d7d8ce642c4578be8d772439b5773dac3b8bcc2..04944542d788e753a077c426c1b2c0224898b95b 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -26,494 +26,58 @@
 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
 
 
-# Load Byte and Zero
+[[!inline pagenames="openpower/isa/fixedload/lbz" raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedload/lbzx" raw="yes"]]
 
-* lbz RT,D(RA)
+[[!inline pagenames="openpower/isa/fixedload/lbzu" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedload/lbzux" raw="yes"]]
 
-    b <- (RA|0)
-    EA <- b + EXTS(D)
-    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+[[!inline pagenames="openpower/isa/fixedload/lhz" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedload/lhzx" raw="yes"]]
 
-    None
+[[!inline pagenames="openpower/isa/fixedload/lhzu" raw="yes"]]
 
-# Load Byte and Zero Indexed
+[[!inline pagenames="openpower/isa/fixedload/lhzux" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fixedload/lha" raw="yes"]]
 
-* lbzx RT,RA,RB
+[[!inline pagenames="openpower/isa/fixedload/lhax" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedload/lhau" raw="yes"]]
 
-    b <- (RA|0)
-    EA <- b + (RB)
-    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+[[!inline pagenames="openpower/isa/fixedload/lhaux" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedload/lwz" raw="yes"]]
 
-    None
+[[!inline pagenames="openpower/isa/fixedload/lwzx" raw="yes"]]
 
-# Load Byte and Zero with Update
+[[!inline pagenames="openpower/isa/fixedload/lwzu" raw="yes"]]
 
-D-Form
+[[!inline pagenames="openpower/isa/fixedload/lwzux" raw="yes"]]
 
-* lbzu RT,D(RA)
+[[!inline pagenames="openpower/isa/fixedload/lwa" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedload/lwax" raw="yes"]]
 
-    EA <- (RA) + EXTS(D)
-    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
-    RA <- EA
+[[!inline pagenames="openpower/isa/fixedload/lwaux" raw="yes"]]
 
-Special Registers Altered:
+[[!inline pagenames="openpower/isa/fixedload/ld" raw="yes"]]
 
-    None
+[[!inline pagenames="openpower/isa/fixedload/ldx" raw="yes"]]
 
-# Load Byte and Zero with Update Indexed
+[[!inline pagenames="openpower/isa/fixedload/ldu" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/fixedload/ldux" raw="yes"]]
 
-* lbzux RT,RA,RB
+[[!inline pagenames="openpower/isa/fixedload/lq" raw="yes"]]
 
-Pseudo-code:
+[[!inline pagenames="openpower/isa/fixedload/lhbrx" raw="yes"]]
 
-    EA <- (RA) + (RB)
-    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
-    RA <- EA
+[[!inline pagenames="openpower/isa/fixedload/lwbrx" raw="yes"]]
 
-Special Registers Altered:
-
-    None
-
-# Load Halfword and Zero
-
-D-Form
-
-* lhz RT,D(RA)
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + EXTS(D)
-    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
-
-Special Registers Altered:
-
-    None
-
-# Load Halfword and Zero Indexed
-
-X-Form
-
-* lhzx RT,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
-
-Special Registers Altered:
-
-    None
-
-# Load Halfword and Zero with Update
-
-D-Form
-
-* lhzu RT,D(RA)
-
-Pseudo-code:
-
-    EA <- (RA) + EXTS(D)
-    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Halfword and Zero with Update Indexed
-
-X-Form
-
-* lhzux RT,RA,RB
-
-Pseudo-code:
-
-    EA <- (RA) + (RB)
-    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Halfword Algebraic
-
-D-Form
-
-* lha RT,D(RA)
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + EXTS(D)
-    RT <- EXTS(MEM(EA, 2))
-
-Special Registers Altered:
-
-    None
-
-# Load Halfword Algebraic Indexed
-
-X-Form
-
-* lhax RT,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    RT <- EXTS(MEM(EA, 2))
-
-Special Registers Altered:
-
-    None
-
-# Load Halfword Algebraic with Update
-
-D-Form
-
-* lhau RT,D(RA)
-
-Pseudo-code:
-
-    EA <- (RA) + EXTS(D)
-    RT <- EXTS(MEM(EA, 2))
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Halfword Algebraic with Update Indexed
-
-X-Form
-
-* lhaux RT,RA,RB
-
-Pseudo-code:
-
-    EA <- (RA) + (RB)
-    RT <- EXTS(MEM(EA, 2))
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Word and Zero
-
-D-Form
-
-* lwz RT,D(RA)
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + EXTS(D)
-    RT <- [0] * 32 || MEM(EA, 4)
-
-Special Registers Altered:
-
-    None
-
-# Load Word and Zero Indexed
-
-X-Form
-
-* lwzx RT,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    RT <- [0] * 32 || MEM(EA, 4)
-
-Special Registers Altered:
-
-    None
-
-# Load Word and Zero with Update
-
-D-Form
-
-* lwzu RT,D(RA)
-
-Pseudo-code:
-
-    EA <- (RA) + EXTS(D)
-    RT <- [0]*32 || MEM(EA, 4)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Word and Zero with Update Indexed
-
-X-Form
-
-* lwzux RT,RA,RB
-
-Pseudo-code:
-
-    EA <- (RA) + (RB)
-    RT <- [0] * 32 || MEM(EA, 4)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Word Algebraic
-
-DS-Form
-
-* lwa RT,DS(RA)
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + EXTS(DS || 0b00)
-    RT <- EXTS(MEM(EA, 4))
-
-Special Registers Altered:
-
-    None
-
-# Load Word Algebraic Indexed
-
-X-Form
-
-* lwax RT,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    RT <- EXTS(MEM(EA, 4))
-
-Special Registers Altered:
-
-    None
-
-# Load Word Algebraic with Update Indexed
-
-X-Form
-
-* lwaux RT,RA,RB
-
-Pseudo-code:
-
-    EA <- (RA) + (RB)
-    RT <- EXTS(MEM(EA, 4))
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Doubleword
-
-DS-Form
-
-* ld RT,DS(RA)
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + EXTS(DS || 0b00)
-    RT <- MEM(EA, 8)
-
-Special Registers Altered:
-
-    None
-
-# Load Doubleword Indexed
-
-X-Form
-
-* ldx RT,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    RT <- MEM(EA, 8)
-
-Special Registers Altered:
-
-    None
-
-# Load Doubleword with Update Indexed
-
-DS-Form
-
-* ldu RT,DS(RA)
-
-Pseudo-code:
-
-    EA <- (RA) + EXTS(DS || 0b00)
-    RT <- MEM(EA, 8)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-# Load Doubleword with Update Indexed
-
-X-Form
-
-* ldux RT,RA,RB
-
-Pseudo-code:
-
-    EA <- (RA) + (RB)
-    RT <- MEM(EA, 8)
-    RA <- EA
-
-Special Registers Altered:
-
-    None
-
-<!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
-
-<!-- The contents of register RS are stored into the byte, halfword, word, or -->
-<!-- doubleword in storage addressed by EA. -->
-
-<!-- Many of the Store instructions have an “update” form, in which register RA is -->
-<!-- updated with the effective address. For these forms, the following rules apply. -->
-
-<!-- If RA!=0, the effective address is placed into register RA. -->
-
-<!-- If RS=RA, the contents of register RS are copied to the target storage element -->
-<!-- and then EA is placed into RA (RS). -->
-
-<!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
-
-<!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
-
-<!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
-<!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
-<!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
-<!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
-<!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
-<!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
-<!-- by EA. -->
-
-# Load Quadword
-
-DQ-Form
-
-* lq RTp,DQ(RA)
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + EXTS(DQ || 0b0000)
-    RTp <- MEM(EA, 16)
-
-Special Registers Altered:
-
-    None
-
-<!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
-
-# Load Halfword Byte-Reverse Indexed
-
-X-Form
-
-* lhbrx RT,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    load_data <- MEM(EA, 2)
-    RT <- [0]*48 || load_data[8:15] || load_data[0:7]
-
-Special Registers Altered:
-
-    None
-
-# Load Word Byte-Reverse Indexed
-
-X-Form
-
-* lwbrx RT,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    load_data <- MEM(EA, 4)
-    RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
-                    || load_data[8:15]  || load_data[0:7])
-
-Special Registers Altered:
-
-    None
-
-
-<!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
-
-# Load Doubleword Byte-Reverse Indexed
-
-X-Form
-
-* ldbrx RT,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    load_data <- MEM(EA, 8)
-    RT <- (load_data[56:63] || load_data[48:55]
-        || load_data[40:47] || load_data[32:39]
-        || load_data[24:31] || load_data[16:23]
-        || load_data[8:15]  || load_data[0:7])
-
-Special Registers Altered:
-
-    None
-
-<!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
-
-# Load Multiple Word
-
-DQ-Form
-
-* lmw RT,D(RA)
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + EXTS(D)
-    r <- RT[0:63]
-    do while r <=  31
-        GPR(r) <- [0]*32 || MEM(EA, 4)
-        r <- r + 1
-        EA <- EA + 4
-
-Special Registers Altered:
-
-    None
+[[!inline pagenames="openpower/isa/fixedload/ldbrx" raw="yes"]]
 
+[[!inline pagenames="openpower/isa/fixedload/lmw" raw="yes"]]

diff --git a/openpower/isa/fixedload/lbz.mdwn b/openpower/isa/fixedload/lbz.mdwn
new file mode 100644 (file)
index 0000000..e115023
--- /dev/null
+++ b/openpower/isa/fixedload/lbz.mdwn
@@ -0,0 +1,13 @@
+# Load Byte and Zero
+
+D-Form
+
+* lbz RT,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lbz_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lbz_code.mdwn b/openpower/isa/fixedload/lbz_code.mdwn
new file mode 100644 (file)
index 0000000..e09492d
--- /dev/null
+++ b/openpower/isa/fixedload/lbz_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + EXTS(D)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)

diff --git a/openpower/isa/fixedload/lbzu.mdwn b/openpower/isa/fixedload/lbzu.mdwn
new file mode 100644 (file)
index 0000000..963b30f
--- /dev/null
+++ b/openpower/isa/fixedload/lbzu.mdwn
@@ -0,0 +1,13 @@
+# Load Byte and Zero with Update
+
+D-Form
+
+* lbzu RT,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lbzu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lbzu_code.mdwn b/openpower/isa/fixedload/lbzu_code.mdwn
new file mode 100644 (file)
index 0000000..a8de539
--- /dev/null
+++ b/openpower/isa/fixedload/lbzu_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + EXTS(D)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+    RA <- EA

diff --git a/openpower/isa/fixedload/lbzux.mdwn b/openpower/isa/fixedload/lbzux.mdwn
new file mode 100644 (file)
index 0000000..2c1008d
--- /dev/null
+++ b/openpower/isa/fixedload/lbzux.mdwn
@@ -0,0 +1,13 @@
+# Load Byte and Zero with Update Indexed
+
+X-Form
+
+* lbzux RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lbzux_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lbzux_code.mdwn b/openpower/isa/fixedload/lbzux_code.mdwn
new file mode 100644 (file)
index 0000000..fca78b9
--- /dev/null
+++ b/openpower/isa/fixedload/lbzux_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + (RB)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+    RA <- EA

diff --git a/openpower/isa/fixedload/lbzx.mdwn b/openpower/isa/fixedload/lbzx.mdwn
new file mode 100644 (file)
index 0000000..5fb9ba8
--- /dev/null
+++ b/openpower/isa/fixedload/lbzx.mdwn
@@ -0,0 +1,13 @@
+# Load Byte and Zero Indexed
+
+X-Form
+
+* lbzx RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lbzx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lbzx_code.mdwn b/openpower/isa/fixedload/lbzx_code.mdwn
new file mode 100644 (file)
index 0000000..ba2f6cb
--- /dev/null
+++ b/openpower/isa/fixedload/lbzx_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)

diff --git a/openpower/isa/fixedload/ld.mdwn b/openpower/isa/fixedload/ld.mdwn
new file mode 100644 (file)
index 0000000..eb28566
--- /dev/null
+++ b/openpower/isa/fixedload/ld.mdwn
@@ -0,0 +1,13 @@
+# Load Doubleword
+
+DS-Form
+
+* ld RT,DS(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/ld_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/ld_code.mdwn b/openpower/isa/fixedload/ld_code.mdwn
new file mode 100644 (file)
index 0000000..becd527
--- /dev/null
+++ b/openpower/isa/fixedload/ld_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + EXTS(DS || 0b00)
+    RT <- MEM(EA, 8)

diff --git a/openpower/isa/fixedload/ldbrx.mdwn b/openpower/isa/fixedload/ldbrx.mdwn
new file mode 100644 (file)
index 0000000..9daeffd
--- /dev/null
+++ b/openpower/isa/fixedload/ldbrx.mdwn
@@ -0,0 +1,15 @@
+# Load Doubleword Byte-Reverse Indexed
+
+X-Form
+
+* ldbrx RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/ldbrx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->

diff --git a/openpower/isa/fixedload/ldbrx_code.mdwn b/openpower/isa/fixedload/ldbrx_code.mdwn
new file mode 100644 (file)
index 0000000..5395b2d
--- /dev/null
+++ b/openpower/isa/fixedload/ldbrx_code.mdwn
@@ -0,0 +1,7 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    load_data <- MEM(EA, 8)
+    RT <- (load_data[56:63] || load_data[48:55]
+        || load_data[40:47] || load_data[32:39]
+        || load_data[24:31] || load_data[16:23]
+        || load_data[8:15]  || load_data[0:7])

diff --git a/openpower/isa/fixedload/ldu.mdwn b/openpower/isa/fixedload/ldu.mdwn
new file mode 100644 (file)
index 0000000..a64d062
--- /dev/null
+++ b/openpower/isa/fixedload/ldu.mdwn
@@ -0,0 +1,13 @@
+# Load Doubleword with Update Indexed
+
+DS-Form
+
+* ldu RT,DS(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/ldu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/ldu_code.mdwn b/openpower/isa/fixedload/ldu_code.mdwn
new file mode 100644 (file)
index 0000000..f43c310
--- /dev/null
+++ b/openpower/isa/fixedload/ldu_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + EXTS(DS || 0b00)
+    RT <- MEM(EA, 8)
+    RA <- EA

diff --git a/openpower/isa/fixedload/ldux.mdwn b/openpower/isa/fixedload/ldux.mdwn
new file mode 100644 (file)
index 0000000..5f1ca71
--- /dev/null
+++ b/openpower/isa/fixedload/ldux.mdwn
@@ -0,0 +1,38 @@
+# Load Doubleword with Update Indexed
+
+X-Form
+
+* ldux RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/ldux_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
+
+<!-- The contents of register RS are stored into the byte, halfword, word, or -->
+<!-- doubleword in storage addressed by EA. -->
+
+<!-- Many of the Store instructions have an “update” form, in which register RA is -->
+<!-- updated with the effective address. For these forms, the following rules apply. -->
+
+<!-- If RA!=0, the effective address is placed into register RA. -->
+
+<!-- If RS=RA, the contents of register RS are copied to the target storage element -->
+<!-- and then EA is placed into RA (RS). -->
+
+<!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
+
+<!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
+
+<!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
+<!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
+<!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
+<!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
+<!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
+<!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
+<!-- by EA. -->

diff --git a/openpower/isa/fixedload/ldux_code.mdwn b/openpower/isa/fixedload/ldux_code.mdwn
new file mode 100644 (file)
index 0000000..69925e6
--- /dev/null
+++ b/openpower/isa/fixedload/ldux_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + (RB)
+    RT <- MEM(EA, 8)
+    RA <- EA

diff --git a/openpower/isa/fixedload/ldx.mdwn b/openpower/isa/fixedload/ldx.mdwn
new file mode 100644 (file)
index 0000000..abf9d49
--- /dev/null
+++ b/openpower/isa/fixedload/ldx.mdwn
@@ -0,0 +1,13 @@
+# Load Doubleword Indexed
+
+X-Form
+
+* ldx RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/ldx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/ldx_code.mdwn b/openpower/isa/fixedload/ldx_code.mdwn
new file mode 100644 (file)
index 0000000..08e30ab
--- /dev/null
+++ b/openpower/isa/fixedload/ldx_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    RT <- MEM(EA, 8)

diff --git a/openpower/isa/fixedload/lha.mdwn b/openpower/isa/fixedload/lha.mdwn
new file mode 100644 (file)
index 0000000..60ea902
--- /dev/null
+++ b/openpower/isa/fixedload/lha.mdwn
@@ -0,0 +1,13 @@
+# Load Halfword Algebraic
+
+D-Form
+
+* lha RT,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lha_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lha_code.mdwn b/openpower/isa/fixedload/lha_code.mdwn
new file mode 100644 (file)
index 0000000..8b85e5e
--- /dev/null
+++ b/openpower/isa/fixedload/lha_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + EXTS(D)
+    RT <- EXTS(MEM(EA, 2))

diff --git a/openpower/isa/fixedload/lhau.mdwn b/openpower/isa/fixedload/lhau.mdwn
new file mode 100644 (file)
index 0000000..4b5f6f9
--- /dev/null
+++ b/openpower/isa/fixedload/lhau.mdwn
@@ -0,0 +1,13 @@
+# Load Halfword Algebraic with Update
+
+D-Form
+
+* lhau RT,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lhau_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lhau_code.mdwn b/openpower/isa/fixedload/lhau_code.mdwn
new file mode 100644 (file)
index 0000000..2111f04
--- /dev/null
+++ b/openpower/isa/fixedload/lhau_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + EXTS(D)
+    RT <- EXTS(MEM(EA, 2))
+    RA <- EA

diff --git a/openpower/isa/fixedload/lhaux.mdwn b/openpower/isa/fixedload/lhaux.mdwn
new file mode 100644 (file)
index 0000000..1d84382
--- /dev/null
+++ b/openpower/isa/fixedload/lhaux.mdwn
@@ -0,0 +1,13 @@
+# Load Halfword Algebraic with Update Indexed
+
+X-Form
+
+* lhaux RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lhaux_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lhaux_code.mdwn b/openpower/isa/fixedload/lhaux_code.mdwn
new file mode 100644 (file)
index 0000000..e09819f
--- /dev/null
+++ b/openpower/isa/fixedload/lhaux_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + (RB)
+    RT <- EXTS(MEM(EA, 2))
+    RA <- EA

diff --git a/openpower/isa/fixedload/lhax.mdwn b/openpower/isa/fixedload/lhax.mdwn
new file mode 100644 (file)
index 0000000..50557e2
--- /dev/null
+++ b/openpower/isa/fixedload/lhax.mdwn
@@ -0,0 +1,13 @@
+# Load Halfword Algebraic Indexed
+
+X-Form
+
+* lhax RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lhax_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lhax_code.mdwn b/openpower/isa/fixedload/lhax_code.mdwn
new file mode 100644 (file)
index 0000000..a63891d
--- /dev/null
+++ b/openpower/isa/fixedload/lhax_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    RT <- EXTS(MEM(EA, 2))

diff --git a/openpower/isa/fixedload/lhbrx.mdwn b/openpower/isa/fixedload/lhbrx.mdwn
new file mode 100644 (file)
index 0000000..14aeff7
--- /dev/null
+++ b/openpower/isa/fixedload/lhbrx.mdwn
@@ -0,0 +1,13 @@
+# Load Halfword Byte-Reverse Indexed
+
+X-Form
+
+* lhbrx RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lhbrx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lhbrx_code.mdwn b/openpower/isa/fixedload/lhbrx_code.mdwn
new file mode 100644 (file)
index 0000000..edecd33
--- /dev/null
+++ b/openpower/isa/fixedload/lhbrx_code.mdwn
@@ -0,0 +1,4 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    load_data <- MEM(EA, 2)
+    RT <- [0]*48 || load_data[8:15] || load_data[0:7]

diff --git a/openpower/isa/fixedload/lhz.mdwn b/openpower/isa/fixedload/lhz.mdwn
new file mode 100644 (file)
index 0000000..fa02b3b
--- /dev/null
+++ b/openpower/isa/fixedload/lhz.mdwn
@@ -0,0 +1,13 @@
+# Load Halfword and Zero
+
+D-Form
+
+* lhz RT,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lhz_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lhz_code.mdwn b/openpower/isa/fixedload/lhz_code.mdwn
new file mode 100644 (file)
index 0000000..b8a81e4
--- /dev/null
+++ b/openpower/isa/fixedload/lhz_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + EXTS(D)
+    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)

diff --git a/openpower/isa/fixedload/lhzu.mdwn b/openpower/isa/fixedload/lhzu.mdwn
new file mode 100644 (file)
index 0000000..126c7b5
--- /dev/null
+++ b/openpower/isa/fixedload/lhzu.mdwn
@@ -0,0 +1,13 @@
+# Load Halfword and Zero with Update
+
+D-Form
+
+* lhzu RT,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lhzu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lhzu_code.mdwn b/openpower/isa/fixedload/lhzu_code.mdwn
new file mode 100644 (file)
index 0000000..ea96683
--- /dev/null
+++ b/openpower/isa/fixedload/lhzu_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + EXTS(D)
+    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
+    RA <- EA

diff --git a/openpower/isa/fixedload/lhzux.mdwn b/openpower/isa/fixedload/lhzux.mdwn
new file mode 100644 (file)
index 0000000..bf52003
--- /dev/null
+++ b/openpower/isa/fixedload/lhzux.mdwn
@@ -0,0 +1,13 @@
+# Load Halfword and Zero with Update Indexed
+
+X-Form
+
+* lhzux RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lhzux_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lhzux_code.mdwn b/openpower/isa/fixedload/lhzux_code.mdwn
new file mode 100644 (file)
index 0000000..ce13da7
--- /dev/null
+++ b/openpower/isa/fixedload/lhzux_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + (RB)
+    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
+    RA <- EA

diff --git a/openpower/isa/fixedload/lhzx.mdwn b/openpower/isa/fixedload/lhzx.mdwn
new file mode 100644 (file)
index 0000000..7c152fc
--- /dev/null
+++ b/openpower/isa/fixedload/lhzx.mdwn
@@ -0,0 +1,13 @@
+# Load Halfword and Zero Indexed
+
+X-Form
+
+* lhzx RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lhzx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lhzx_code.mdwn b/openpower/isa/fixedload/lhzx_code.mdwn
new file mode 100644 (file)
index 0000000..ba0596f
--- /dev/null
+++ b/openpower/isa/fixedload/lhzx_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)

diff --git a/openpower/isa/fixedload/lmw.mdwn b/openpower/isa/fixedload/lmw.mdwn
new file mode 100644 (file)
index 0000000..2e8ef9d
--- /dev/null
+++ b/openpower/isa/fixedload/lmw.mdwn
@@ -0,0 +1,14 @@
+# Load Multiple Word
+
+DQ-Form
+
+* lmw RT,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lmw_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+

diff --git a/openpower/isa/fixedload/lmw_code.mdwn b/openpower/isa/fixedload/lmw_code.mdwn
new file mode 100644 (file)
index 0000000..3ff469b
--- /dev/null
+++ b/openpower/isa/fixedload/lmw_code.mdwn
@@ -0,0 +1,7 @@
+    b <- (RA|0)
+    EA <- b + EXTS(D)
+    r <- RT[0:63]
+    do while r <=  31
+        GPR(r) <- [0]*32 || MEM(EA, 4)
+        r <- r + 1
+        EA <- EA + 4

diff --git a/openpower/isa/fixedload/lq.mdwn b/openpower/isa/fixedload/lq.mdwn
new file mode 100644 (file)
index 0000000..188f50e
--- /dev/null
+++ b/openpower/isa/fixedload/lq.mdwn
@@ -0,0 +1,15 @@
+# Load Quadword
+
+DQ-Form
+
+* lq RTp,DQ(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lq_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->

diff --git a/openpower/isa/fixedload/lq_code.mdwn b/openpower/isa/fixedload/lq_code.mdwn
new file mode 100644 (file)
index 0000000..3a94613
--- /dev/null
+++ b/openpower/isa/fixedload/lq_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + EXTS(DQ || 0b0000)
+    RTp <- MEM(EA, 16)

diff --git a/openpower/isa/fixedload/lwa.mdwn b/openpower/isa/fixedload/lwa.mdwn
new file mode 100644 (file)
index 0000000..a8b8670
--- /dev/null
+++ b/openpower/isa/fixedload/lwa.mdwn
@@ -0,0 +1,13 @@
+# Load Word Algebraic
+
+DS-Form
+
+* lwa RT,DS(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lwa_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lwa_code.mdwn b/openpower/isa/fixedload/lwa_code.mdwn
new file mode 100644 (file)
index 0000000..6d7527f
--- /dev/null
+++ b/openpower/isa/fixedload/lwa_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + EXTS(DS || 0b00)
+    RT <- EXTS(MEM(EA, 4))

diff --git a/openpower/isa/fixedload/lwaux.mdwn b/openpower/isa/fixedload/lwaux.mdwn
new file mode 100644 (file)
index 0000000..d8551ed
--- /dev/null
+++ b/openpower/isa/fixedload/lwaux.mdwn
@@ -0,0 +1,13 @@
+# Load Word Algebraic with Update Indexed
+
+X-Form
+
+* lwaux RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lwaux_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lwaux_code.mdwn b/openpower/isa/fixedload/lwaux_code.mdwn
new file mode 100644 (file)
index 0000000..4f8cf3b
--- /dev/null
+++ b/openpower/isa/fixedload/lwaux_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + (RB)
+    RT <- EXTS(MEM(EA, 4))
+    RA <- EA

diff --git a/openpower/isa/fixedload/lwax.mdwn b/openpower/isa/fixedload/lwax.mdwn
new file mode 100644 (file)
index 0000000..e9c2994
--- /dev/null
+++ b/openpower/isa/fixedload/lwax.mdwn
@@ -0,0 +1,13 @@
+# Load Word Algebraic Indexed
+
+X-Form
+
+* lwax RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lwax_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lwax_code.mdwn b/openpower/isa/fixedload/lwax_code.mdwn
new file mode 100644 (file)
index 0000000..eaeb93a
--- /dev/null
+++ b/openpower/isa/fixedload/lwax_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    RT <- EXTS(MEM(EA, 4))

diff --git a/openpower/isa/fixedload/lwbrx.mdwn b/openpower/isa/fixedload/lwbrx.mdwn
new file mode 100644 (file)
index 0000000..158a3b8
--- /dev/null
+++ b/openpower/isa/fixedload/lwbrx.mdwn
@@ -0,0 +1,16 @@
+# Load Word Byte-Reverse Indexed
+
+X-Form
+
+* lwbrx RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lwbrx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+
+<!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->

diff --git a/openpower/isa/fixedload/lwbrx_code.mdwn b/openpower/isa/fixedload/lwbrx_code.mdwn
new file mode 100644 (file)
index 0000000..493dd30
--- /dev/null
+++ b/openpower/isa/fixedload/lwbrx_code.mdwn
@@ -0,0 +1,5 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    load_data <- MEM(EA, 4)
+    RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
+                    || load_data[8:15]  || load_data[0:7])

diff --git a/openpower/isa/fixedload/lwz.mdwn b/openpower/isa/fixedload/lwz.mdwn
new file mode 100644 (file)
index 0000000..b4dcb8e
--- /dev/null
+++ b/openpower/isa/fixedload/lwz.mdwn
@@ -0,0 +1,13 @@
+# Load Word and Zero
+
+D-Form
+
+* lwz RT,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lwz_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lwz_code.mdwn b/openpower/isa/fixedload/lwz_code.mdwn
new file mode 100644 (file)
index 0000000..766b4e0
--- /dev/null
+++ b/openpower/isa/fixedload/lwz_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + EXTS(D)
+    RT <- [0] * 32 || MEM(EA, 4)

diff --git a/openpower/isa/fixedload/lwzu.mdwn b/openpower/isa/fixedload/lwzu.mdwn
new file mode 100644 (file)
index 0000000..4dd813b
--- /dev/null
+++ b/openpower/isa/fixedload/lwzu.mdwn
@@ -0,0 +1,13 @@
+# Load Word and Zero with Update
+
+D-Form
+
+* lwzu RT,D(RA)
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lwzu_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lwzu_code.mdwn b/openpower/isa/fixedload/lwzu_code.mdwn
new file mode 100644 (file)
index 0000000..0eb0d41
--- /dev/null
+++ b/openpower/isa/fixedload/lwzu_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + EXTS(D)
+    RT <- [0]*32 || MEM(EA, 4)
+    RA <- EA

diff --git a/openpower/isa/fixedload/lwzux.mdwn b/openpower/isa/fixedload/lwzux.mdwn
new file mode 100644 (file)
index 0000000..dfb0c5e
--- /dev/null
+++ b/openpower/isa/fixedload/lwzux.mdwn
@@ -0,0 +1,13 @@
+# Load Word and Zero with Update Indexed
+
+X-Form
+
+* lwzux RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lwzux_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lwzux_code.mdwn b/openpower/isa/fixedload/lwzux_code.mdwn
new file mode 100644 (file)
index 0000000..4537416
--- /dev/null
+++ b/openpower/isa/fixedload/lwzux_code.mdwn
@@ -0,0 +1,3 @@
+    EA <- (RA) + (RB)
+    RT <- [0] * 32 || MEM(EA, 4)
+    RA <- EA

diff --git a/openpower/isa/fixedload/lwzx.mdwn b/openpower/isa/fixedload/lwzx.mdwn
new file mode 100644 (file)
index 0000000..40f4f36
--- /dev/null
+++ b/openpower/isa/fixedload/lwzx.mdwn
@@ -0,0 +1,13 @@
+# Load Word and Zero Indexed
+
+X-Form
+
+* lwzx RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/fixedload/lwzx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isa/fixedload/lwzx_code.mdwn b/openpower/isa/fixedload/lwzx_code.mdwn
new file mode 100644 (file)
index 0000000..d52786a
--- /dev/null
+++ b/openpower/isa/fixedload/lwzx_code.mdwn
@@ -0,0 +1,3 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    RT <- [0] * 32 || MEM(EA, 4)