build/sim: handle verilog $finish and if coverage is enabled, write report at the...

diff --git a/litex/build/sim/core/sim.c b/litex/build/sim/core/sim.c
index 0ab18516bcef1778f0b422a9898a0864e738b463..6e62c5cfcd811912cbfce7b7c235ecbc39dd24d3 100644 (file)
--- a/litex/build/sim/core/sim.c
+++ b/litex/build/sim/core/sim.c
@@ -32,6 +32,7 @@ struct session_list_s {
 };
 
 struct session_list_s *sesslist=NULL;
+struct event_base *base=NULL;
 
 static int litex_sim_initialize_all(void **dut, void *base)
 {
@@ -175,7 +176,6 @@ static void cb(int sock, short which, void *arg)
   tv.tv_usec = 0;
   int i;
 
-
   for(i = 0; i < 1000; i++)
   {
     for(s = sesslist; s; s=s->next)
@@ -192,6 +192,9 @@ static void cb(int sock, short which, void *arg)
     }
   }
 
+  if (litex_sim_got_finish())
+    event_base_loopbreak(base);
+
   if (!evtimer_pending(ev, NULL)) {
     event_del(ev);
     evtimer_add(ev, &tv);
@@ -201,7 +204,6 @@ static void cb(int sock, short which, void *arg)
 int main()
 {
   void *vdut=NULL;
-  struct event_base *base=NULL;
   struct timeval tv;
 
   int ret;
@@ -235,8 +237,10 @@ int main()
   tv.tv_usec = 0;
   ev = event_new(base, -1, EV_PERSIST, cb, vdut);
   event_add(ev, &tv);
-
   event_base_dispatch(base);
+#if VM_COVERAGE
+  litex_sim_coverage_dump();
+#endif
 out:
   return ret;
 }

diff --git a/litex/build/sim/core/veril.cpp b/litex/build/sim/core/veril.cpp
index cf5db23b5bd5e9eda9cc6f64c426740a9171f94e..ef43fb1df9bb58f95420f834bb0ff77f072f59cf 100644 (file)
--- a/litex/build/sim/core/veril.cpp
+++ b/litex/build/sim/core/veril.cpp
@@ -32,6 +32,17 @@ extern "C" void litex_sim_tracer_dump()
   tfp->dump(ticks++);
 }
 
+extern "C" int litex_sim_got_finish()
+{
+  return Verilated::gotFinish();
+}
+
+#if VM_COVERAGE
+extern "C" void litex_sim_coverage_dump()
+{
+  VerilatedCov::write("dut.cov");
+}
+#endif
 
 vluint64_t main_time = 0;
 double sc_time_stamp()

diff --git a/litex/build/sim/core/veril.h b/litex/build/sim/core/veril.h
index b780793bfd79c7a2dcf12b1d8661af93423cd0d3..35326ade6c407a7f15927662ccb3d02e829b9558 100644 (file)
--- a/litex/build/sim/core/veril.h
+++ b/litex/build/sim/core/veril.h
@@ -7,10 +7,18 @@
 extern "C" void litex_sim_eval(void *vdut);
 extern "C" void litex_sim_init_tracer(void *vdut);
 extern "C" void litex_sim_tracer_dump();
+extern "C" int litex_sim_got_finish();
+#if VM_COVERAGE
+extern "C" void litex_sim_coverage_dump();
+#endif
 #else
 void litex_sim_eval(void *vdut);
 void litex_sim_init_tracer(void *vdut);
 void litex_sim_tracer_dump();
+int litex_sim_got_finish();
+#if VM_COVERAGE
+void litex_sim_coverage_dump();
+#endif
 #endif
 
 #endif

diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 0d3c63f2eedd4ad800b2773ef195f2774412f68f..76f607f023ae6258b905503ec4602be598361ed3 100644 (file)
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -160,8 +160,9 @@ def _run_sim(build_name, as_root=False):
         if r != 0:
             raise OSError("Subprocess failed")
     except:
-        if sys.platform != "win32":
-            termios.tcsetattr(sys.stdin.fileno(), termios.TCSAFLUSH, termios_settings)
+        pass
+    if sys.platform != "win32":
+        termios.tcsetattr(sys.stdin.fileno(), termios.TCSAFLUSH, termios_settings)
 
 
 class SimVerilatorToolchain: