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Merge pull request #2453 from YosysHQ/mmicko/verilog_assignments
authorMiodrag Milanović <mmicko@gmail.com>
Wed, 25 Nov 2020 18:15:11 +0000 (19:15 +0100)
committerGitHub <noreply@github.com>
Wed, 25 Nov 2020 18:15:11 +0000 (19:15 +0100)
Generate only simple assignments in verilog backend


Trivial merge