if (!PC_PAL(regs.pc))
return Unimplemented_Opcode_Fault;
- kernelStats.hwrei();
-
- regs.npc = ipr[AlphaISA::IPR_EXC_ADDR];
+ setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
if (!misspeculating()) {
+ kernelStats.hwrei();
+
if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
AlphaISA::swap_palshadow(®s, false);
case PAL::bpt:
case PAL::bugchk:
- if (system->breakpoint())
+ if (!misspeculating() && system->breakpoint())
return false;
break;
}
format BasicOperate {
0xe000: rc({{
Ra = xc->regs.intrflag;
- xc->regs.intrflag = 0;
+ if (!xc->misspeculating()) {
+ xc->regs.intrflag = 0;
+ }
}}, No_OpClass);
0xf000: rs({{
Ra = xc->regs.intrflag;
- xc->regs.intrflag = 1;
+ if (!xc->misspeculating()) {
+ xc->regs.intrflag = 1;
+ }
}}, No_OpClass);
}
#else
// on this PAL call (including maybe suppress it)
bool dopal = xc->simPalCheck(palFunc);
- Annotate::Callpal(xc, palFunc);
+ if (!xc->misspeculating()) {
+ Annotate::Callpal(xc, palFunc);
+ }
if (dopal) {
if (!xc->misspeculating()) {
if (!xc->misspeculating())
SimExit("halt instruction encountered");
}});
- 0x83: callsys({{ xc->syscall(); }});
+ 0x83: callsys({{
+ if (!xc->misspeculating())
+ xc->syscall();
+ }});
// Read uniq reg into ABI return value register (r0)
0x9e: rduniq({{ R0 = Runiq; }});
// Write uniq reg with value from ABI arg register (r16)