add ARM NEON as best can be done

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index 1881b1623e777852fb126071917bbeacdfc984a2..6f4e1e1794263c6a242205867ec903a7b9771178 100644 (file)
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -1,13 +1,19 @@
 # ISA Comparison Table
 
-| Name | Num of <br />opcodes | Scalable | Predicate <br /> Masks | Twin <br /> Predication |  Explicit <br /> Vector regs | 128-bit | Bigint <br /> capability | LDST <br /> Fault-First | Data-dependent <br /> Fail-first | Predicate-<br /> Result |
-|------|----------------------|----------|------------------------|-------------------------|------------------------------|---------|--------------------------|-------------------------|----------------------------------|-------------------------|
-| SVP64| 5 (plus prefixing)   | yes      | yes                    | yes{1}                  | no{2}                        | n/a{3}  | yes{4}                   | yes{5}                  | yes{6}                           | yes{7}                  |
+| Name | Num <br />opcodes | Scalable | Predicate <br /> Masks | Twin <br /> Predication |  Explicit <br /> Vector regs | 128-bit | Bigint <br /> capability | LDST <br /> Fault-First | Data-dependent <br /> Fail-first | Predicate-<br /> Result |
+|------|-------------------|----------|------------------------|-------------------------|------------------------------|---------|--------------------------|-------------------------|----------------------------------|-------------------------|
+| SVP64| 5{1}              | yes      | yes                    | yes{2}                  | no{3}                        | n/a{4}  | yes{5}                   | yes{6}                  | yes{7}                           | yes{8}                  |
+| VSX  | 700+              | no       | no                     | no                      | yes{9}                       | yes     | no                       | no                      | no                               | no                      |
+| NEON | ~250[10]          | no       | yes                    | no                      | yes                          | yes     | no                       | no                      | no                               | no                      |
 
-* {1}: on specific operations.
-* {2}: SVP64 provides the Vector register concept on top of the *Scalar* GPR, FPR and CR register files
-* {3}: SVP64 Vectorises Scalar instructions. When applied to e.g. VSX QP instructions, SVP64 "gains" 128-bit.
-* {4}: big-integer add is just `sv.adde`. Mul and divide require addition of two scalar operations
-* {5} See [[sv/svp64/appendix]]
-* {6} Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]]
-* {7} Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]]
+* {1}: plus EXT001 24-bit prefixing. See [[sv/svp64]]
+* {2}: on specific operations.  See [[opcode_regs_deduped]]
+* {3}: SVP64 provides the Vector register concept on top of the *Scalar* GPR, FPR and CR register files
+* {4}: SVP64 Vectorises Scalar instructions. When applied to e.g. VSX QP instructions, SVP64 "gains" 128-bit.
+* {5}: big-integer add is just `sv.adde`. Mul and divide require addition of two scalar operations
+* {6} See [[sv/svp64/appendix]]
+* {7} Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]]
+* {8} Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]]
+* {9} VSX's Vector Registers are mis-named: they are PackedSIMD.
+* {10} difficult to ascertain, see [NEON/VFP](https://developer.arm.com/documentation/den0018/a/NEON-and-VFP-Instruction-Summary/List-of-all-NEON-and-VFP-instructions).
+       critically depends on ARM Scalar instructions