freedreno/a6xx: Update headers

This pulls in changes for compute shaders and a6xx ssbo/image support.
FACENESS bit moved from position 1 to 2 and there's a global invert
bit for point coord.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>

diff --git a/src/freedreno/registers/a2xx.xml.h b/src/freedreno/registers/a2xx.xml.h
index 95be019bbe0731dfe0036bf5af7a7f5dc34a29f0..9c2e6f50dd739149a036d48eb76e49b244842c72 100644 (file)
--- a/src/freedreno/registers/a2xx.xml.h
+++ b/src/freedreno/registers/a2xx.xml.h
@@ -8,12 +8,19 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- ./rnndb/adreno/a2xx.xml          (  79608 bytes, from 2018-12-21 03:07:09)
-- ./rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-09-02 13:35:19)
-- ./rnndb/adreno/adreno_common.xml (  14201 bytes, from 2018-09-07 18:12:21)
-- ./rnndb/adreno/adreno_pm4.xml    (  42626 bytes, from 2018-09-17 18:20:14)
-
-Copyright (C) 2013-2018 by the following authors:
+- /work/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a2xx.xml          (  79608 bytes, from 2019-02-11 18:07:21)
+- /work/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-17 18:59:13)
+- /work/envytools/rnndb/adreno/adreno_pm4.xml    (  43155 bytes, from 2019-02-12 18:24:48)
+- /work/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-09-28 22:41:49)
+- /work/envytools/rnndb/adreno/a6xx.xml          ( 145596 bytes, from 2019-02-13 18:14:29)
+- /work/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-28 22:41:49)
+- /work/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-10 14:59:32)
+
+Copyright (C) 2013-2019 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
 

diff --git a/src/freedreno/registers/a3xx.xml.h b/src/freedreno/registers/a3xx.xml.h
index 03be4aab0b6afb89e9f4d280af48f4b08fd313df..21434d92154bb264ba08d040cb105bab7b67a4b6 100644 (file)
--- a/src/freedreno/registers/a3xx.xml.h
+++ b/src/freedreno/registers/a3xx.xml.h
@@ -8,17 +8,17 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  42463 bytes, from 2018-11-19 13:44:03)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-05 15:25:53)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  43052 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 141895 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-14 13:03:07)
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
+- /work/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a2xx.xml          (  79608 bytes, from 2019-02-11 18:07:21)
+- /work/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-17 18:59:13)
+- /work/envytools/rnndb/adreno/adreno_pm4.xml    (  43155 bytes, from 2019-02-12 18:24:48)
+- /work/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-09-28 22:41:49)
+- /work/envytools/rnndb/adreno/a6xx.xml          ( 145596 bytes, from 2019-02-13 18:14:29)
+- /work/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-28 22:41:49)
+- /work/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-10 14:59:32)
 
 Copyright (C) 2013-2018 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)

diff --git a/src/freedreno/registers/a4xx.xml.h b/src/freedreno/registers/a4xx.xml.h
index 3dfc03cd2d2b85db17256aa6826bb8a4ac0feb4c..eb3339803f476b66cdbbab6832cc0e01c752ee09 100644 (file)
--- a/src/freedreno/registers/a4xx.xml.h
+++ b/src/freedreno/registers/a4xx.xml.h
@@ -8,17 +8,17 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  42463 bytes, from 2018-11-19 13:44:03)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-05 15:25:53)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  43052 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 141895 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-14 13:03:07)
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
+- /work/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a2xx.xml          (  79608 bytes, from 2019-02-11 18:07:21)
+- /work/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-17 18:59:13)
+- /work/envytools/rnndb/adreno/adreno_pm4.xml    (  43155 bytes, from 2019-02-12 18:24:48)
+- /work/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-09-28 22:41:49)
+- /work/envytools/rnndb/adreno/a6xx.xml          ( 145596 bytes, from 2019-02-13 18:14:29)
+- /work/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-28 22:41:49)
+- /work/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-10 14:59:32)
 
 Copyright (C) 2013-2018 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)

diff --git a/src/freedreno/registers/a5xx.xml.h b/src/freedreno/registers/a5xx.xml.h
index 89e8f230a730a2c10479438e026af428ae78f5ba..994cf83355080709e6e1561358e1ca4ae9682258 100644 (file)
--- a/src/freedreno/registers/a5xx.xml.h
+++ b/src/freedreno/registers/a5xx.xml.h
@@ -8,17 +8,17 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  42463 bytes, from 2018-11-19 13:44:03)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-05 15:25:53)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  43052 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 141895 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-14 13:03:07)
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
+- /work/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a2xx.xml          (  79608 bytes, from 2019-02-11 18:07:21)
+- /work/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-17 18:59:13)
+- /work/envytools/rnndb/adreno/adreno_pm4.xml    (  43155 bytes, from 2019-02-12 18:24:48)
+- /work/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-09-28 22:41:49)
+- /work/envytools/rnndb/adreno/a6xx.xml          ( 145596 bytes, from 2019-02-13 18:14:29)
+- /work/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-28 22:41:49)
+- /work/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-10 14:59:32)
 
 Copyright (C) 2013-2018 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)

diff --git a/src/freedreno/registers/a6xx.xml.h b/src/freedreno/registers/a6xx.xml.h
index 9dd70e16472578d9c8d9750cea101b9cc88c36a7..0bfd11311bf63e3d38947d8c1c050d30ea16c64d 100644 (file)
--- a/src/freedreno/registers/a6xx.xml.h
+++ b/src/freedreno/registers/a6xx.xml.h
@@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are:
 - /work/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-10 14:59:32)
 - /work/envytools/rnndb/adreno/a2xx.xml          (  79608 bytes, from 2019-02-11 18:07:21)
 - /work/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-17 18:59:13)
-- /work/envytools/rnndb/adreno/adreno_pm4.xml    (  43052 bytes, from 2018-12-17 18:59:13)
+- /work/envytools/rnndb/adreno/adreno_pm4.xml    (  43155 bytes, from 2019-02-12 18:24:48)
 - /work/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-10 14:59:32)
 - /work/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-10 14:59:32)
 - /work/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-09-28 22:41:49)
-- /work/envytools/rnndb/adreno/a6xx.xml          ( 142565 bytes, from 2019-02-11 18:07:21)
+- /work/envytools/rnndb/adreno/a6xx.xml          ( 145596 bytes, from 2019-02-13 18:14:29)
 - /work/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-28 22:41:49)
 - /work/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-10 14:59:32)
 
@@ -3197,7 +3197,7 @@ static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
 
 #define REG_A6XX_RB_RENDER_CONTROL1                            0x0000880a
 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK                     0x00000001
-#define A6XX_RB_RENDER_CONTROL1_FACENESS                       0x00000002
+#define A6XX_RB_RENDER_CONTROL1_FACENESS                       0x00000004
 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID                       0x00000008
 
 #define REG_A6XX_RB_FS_OUTPUT_CNTL0                            0x0000880b
@@ -3996,6 +3996,12 @@ static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x000
 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
 
 #define REG_A6XX_VPC_UNKNOWN_9236                              0x00009236
+#define A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__MASK         0x00000001
+#define A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__SHIFT                0
+static inline uint32_t A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(uint32_t val)
+{
+       return ((val) << A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__SHIFT) & A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT__MASK;
+}
 
 #define REG_A6XX_VPC_UNKNOWN_9300                              0x00009300
 
@@ -4318,12 +4324,18 @@ static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
 {
        return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
 }
-#define A6XX_SP_VS_CONFIG_NSAMP__MASK                          0x01fe0000
+#define A6XX_SP_VS_CONFIG_NSAMP__MASK                          0x003e0000
 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT                         17
 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
 {
        return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
 }
+#define A6XX_SP_VS_CONFIG_NIBO__MASK                           0x3fc00000
+#define A6XX_SP_VS_CONFIG_NIBO__SHIFT                          22
+static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
+{
+       return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
+}
 
 #define REG_A6XX_SP_VS_INSTRLEN                                        0x0000a824
 
@@ -4372,12 +4384,18 @@ static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
 {
        return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
 }
-#define A6XX_SP_HS_CONFIG_NSAMP__MASK                          0x01fe0000
+#define A6XX_SP_HS_CONFIG_NSAMP__MASK                          0x003e0000
 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT                         17
 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
 {
        return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
 }
+#define A6XX_SP_HS_CONFIG_NIBO__MASK                           0x3fc00000
+#define A6XX_SP_HS_CONFIG_NIBO__SHIFT                          22
+static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
+{
+       return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
+}
 
 #define REG_A6XX_SP_HS_INSTRLEN                                        0x0000a83c
 
@@ -4424,12 +4442,18 @@ static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
 {
        return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
 }
-#define A6XX_SP_DS_CONFIG_NSAMP__MASK                          0x01fe0000
+#define A6XX_SP_DS_CONFIG_NSAMP__MASK                          0x003e0000
 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT                         17
 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
 {
        return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
 }
+#define A6XX_SP_DS_CONFIG_NIBO__MASK                           0x3fc00000
+#define A6XX_SP_DS_CONFIG_NIBO__SHIFT                          22
+static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
+{
+       return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
+}
 
 #define REG_A6XX_SP_DS_INSTRLEN                                        0x0000a864
 
@@ -4478,12 +4502,18 @@ static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
 {
        return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
 }
-#define A6XX_SP_GS_CONFIG_NSAMP__MASK                          0x01fe0000
+#define A6XX_SP_GS_CONFIG_NSAMP__MASK                          0x003e0000
 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT                         17
 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
 {
        return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
 }
+#define A6XX_SP_GS_CONFIG_NIBO__MASK                           0x3fc00000
+#define A6XX_SP_GS_CONFIG_NIBO__SHIFT                          22
+static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
+{
+       return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
+}
 
 #define REG_A6XX_SP_GS_INSTRLEN                                        0x0000a895
 
@@ -4653,6 +4683,12 @@ static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val)
 
 #define REG_A6XX_SP_UNKNOWN_A9A8                               0x0000a9a8
 
+#define REG_A6XX_SP_CS_UNKNOWN_A9B1                            0x0000a9b1
+
+#define REG_A6XX_SP_CS_UNKNOWN_A9B3                            0x0000a9b3
+
+#define REG_A6XX_SP_CS_TEX_COUNT                               0x0000a9ba
+
 #define REG_A6XX_SP_FS_TEX_SAMP_LO                             0x0000a9e0
 
 #define REG_A6XX_SP_FS_TEX_SAMP_HI                             0x0000a9e1
@@ -4713,8 +4749,35 @@ static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
 
 #define REG_A6XX_SP_CS_OBJ_START_HI                            0x0000a9b5
 
+#define REG_A6XX_SP_CS_CONFIG                                  0x0000a9bb
+#define A6XX_SP_CS_CONFIG_ENABLED                              0x00000100
+#define A6XX_SP_CS_CONFIG_NTEX__MASK                           0x0001fe00
+#define A6XX_SP_CS_CONFIG_NTEX__SHIFT                          9
+static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
+{
+       return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
+}
+#define A6XX_SP_CS_CONFIG_NSAMP__MASK                          0x003e0000
+#define A6XX_SP_CS_CONFIG_NSAMP__SHIFT                         17
+static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
+{
+       return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
+}
+#define A6XX_SP_CS_CONFIG_NIBO__MASK                           0x3fc00000
+#define A6XX_SP_CS_CONFIG_NIBO__SHIFT                          22
+static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
+{
+       return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
+}
+
 #define REG_A6XX_SP_CS_INSTRLEN                                        0x0000a9bc
 
+#define REG_A6XX_SP_CS_IBO_LO                                  0x0000a9f2
+
+#define REG_A6XX_SP_CS_IBO_HI                                  0x0000a9f3
+
+#define REG_A6XX_SP_CS_IBO_COUNT                               0x0000aa00
+
 #define REG_A6XX_SP_UNKNOWN_AB00                               0x0000ab00
 
 #define REG_A6XX_SP_FS_CONFIG                                  0x0000ab04
@@ -4725,16 +4788,26 @@ static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
 {
        return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
 }
-#define A6XX_SP_FS_CONFIG_NSAMP__MASK                          0x01fe0000
+#define A6XX_SP_FS_CONFIG_NSAMP__MASK                          0x003e0000
 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT                         17
 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
 {
        return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
 }
+#define A6XX_SP_FS_CONFIG_NIBO__MASK                           0x3fc00000
+#define A6XX_SP_FS_CONFIG_NIBO__SHIFT                          22
+static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
+{
+       return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
+}
 
 #define REG_A6XX_SP_FS_INSTRLEN                                        0x0000ab05
 
-#define REG_A6XX_SP_UNKNOWN_AB20                               0x0000ab20
+#define REG_A6XX_SP_IBO_LO                                     0x0000ab1a
+
+#define REG_A6XX_SP_IBO_HI                                     0x0000ab1b
+
+#define REG_A6XX_SP_IBO_COUNT                                  0x0000ab20
 
 #define REG_A6XX_SP_2D_SRC_FORMAT                              0x0000acc0
 #define A6XX_SP_2D_SRC_FORMAT_NORM                             0x00000001
@@ -4849,6 +4922,7 @@ static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
        assert(!(val & 0x3));
        return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
 }
+#define A6XX_HLSQ_VS_CNTL_ENABLED                              0x00000100
 
 #define REG_A6XX_HLSQ_HS_CNTL                                  0x0000b801
 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK                       0x000000ff
@@ -4858,6 +4932,7 @@ static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
        assert(!(val & 0x3));
        return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
 }
+#define A6XX_HLSQ_HS_CNTL_ENABLED                              0x00000100
 
 #define REG_A6XX_HLSQ_DS_CNTL                                  0x0000b802
 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK                       0x000000ff
@@ -4867,6 +4942,7 @@ static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
        assert(!(val & 0x3));
        return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
 }
+#define A6XX_HLSQ_DS_CNTL_ENABLED                              0x00000100
 
 #define REG_A6XX_HLSQ_GS_CNTL                                  0x0000b803
 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK                       0x000000ff
@@ -4876,6 +4952,7 @@ static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
        assert(!(val & 0x3));
        return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
 }
+#define A6XX_HLSQ_GS_CNTL_ENABLED                              0x00000100
 
 #define REG_A6XX_HLSQ_UNKNOWN_B980                             0x0000b980
 
@@ -4925,6 +5002,16 @@ static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
 
 #define REG_A6XX_HLSQ_CONTROL_5_REG                            0x0000b986
 
+#define REG_A6XX_HLSQ_CS_CNTL                                  0x0000b987
+#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK                       0x000000ff
+#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT                      0
+static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
+{
+       assert(!(val & 0x3));
+       return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
+}
+#define A6XX_HLSQ_CS_CNTL_ENABLED                              0x00000100
+
 #define REG_A6XX_HLSQ_CS_NDRANGE_0                             0x0000b990
 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK                 0x00000003
 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT                        0
@@ -5025,6 +5112,8 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
        return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
 }
 
+#define REG_A6XX_HLSQ_CS_UNKNOWN_B998                          0x0000b998
+
 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X                                0x0000b999
 
 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y                                0x0000b99a
@@ -5041,6 +5130,7 @@ static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
        assert(!(val & 0x3));
        return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
 }
+#define A6XX_HLSQ_FS_CNTL_ENABLED                              0x00000100
 
 #define REG_A6XX_HLSQ_UNKNOWN_BB11                             0x0000bb11
 
@@ -5200,6 +5290,7 @@ static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
 }
 
 #define REG_A6XX_TEX_CONST_2                                   0x00000002
+#define A6XX_TEX_CONST_2_UNK4                                  0x00000010
 #define A6XX_TEX_CONST_2_FETCHSIZE__MASK                       0x0000000f
 #define A6XX_TEX_CONST_2_FETCHSIZE__SHIFT                      0
 static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val)
@@ -5218,6 +5309,7 @@ static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
 {
        return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
 }
+#define A6XX_TEX_CONST_2_UNK31                                 0x80000000
 
 #define REG_A6XX_TEX_CONST_3                                   0x00000003
 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK                     0x00003fff
@@ -5307,6 +5399,75 @@ static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
 
 #define REG_A6XX_TEX_CONST_15                                  0x0000000f
 
+#define REG_A6XX_IBO_0                                         0x00000000
+#define A6XX_IBO_0_FMT__MASK                                   0x3fc00000
+#define A6XX_IBO_0_FMT__SHIFT                                  22
+static inline uint32_t A6XX_IBO_0_FMT(enum a6xx_tex_fmt val)
+{
+       return ((val) << A6XX_IBO_0_FMT__SHIFT) & A6XX_IBO_0_FMT__MASK;
+}
+
+#define REG_A6XX_IBO_1                                         0x00000001
+#define A6XX_IBO_1_WIDTH__MASK                                 0x00007fff
+#define A6XX_IBO_1_WIDTH__SHIFT                                        0
+static inline uint32_t A6XX_IBO_1_WIDTH(uint32_t val)
+{
+       return ((val) << A6XX_IBO_1_WIDTH__SHIFT) & A6XX_IBO_1_WIDTH__MASK;
+}
+#define A6XX_IBO_1_HEIGHT__MASK                                        0x3fff8000
+#define A6XX_IBO_1_HEIGHT__SHIFT                               15
+static inline uint32_t A6XX_IBO_1_HEIGHT(uint32_t val)
+{
+       return ((val) << A6XX_IBO_1_HEIGHT__SHIFT) & A6XX_IBO_1_HEIGHT__MASK;
+}
+
+#define REG_A6XX_IBO_2                                         0x00000002
+#define A6XX_IBO_2_UNK4                                                0x00000010
+#define A6XX_IBO_2_PITCH__MASK                                 0x1fffff80
+#define A6XX_IBO_2_PITCH__SHIFT                                        7
+static inline uint32_t A6XX_IBO_2_PITCH(uint32_t val)
+{
+       return ((val) << A6XX_IBO_2_PITCH__SHIFT) & A6XX_IBO_2_PITCH__MASK;
+}
+#define A6XX_IBO_2_TYPE__MASK                                  0x60000000
+#define A6XX_IBO_2_TYPE__SHIFT                                 29
+static inline uint32_t A6XX_IBO_2_TYPE(enum a6xx_tex_type val)
+{
+       return ((val) << A6XX_IBO_2_TYPE__SHIFT) & A6XX_IBO_2_TYPE__MASK;
+}
+#define A6XX_IBO_2_UNK31                                       0x80000000
+
+#define REG_A6XX_IBO_3                                         0x00000003
+#define A6XX_IBO_3_ARRAY_PITCH__MASK                           0x00003fff
+#define A6XX_IBO_3_ARRAY_PITCH__SHIFT                          0
+static inline uint32_t A6XX_IBO_3_ARRAY_PITCH(uint32_t val)
+{
+       assert(!(val & 0xfff));
+       return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK;
+}
+
+#define REG_A6XX_IBO_4                                         0x00000004
+#define A6XX_IBO_4_BASE_LO__MASK                               0xffffffff
+#define A6XX_IBO_4_BASE_LO__SHIFT                              0
+static inline uint32_t A6XX_IBO_4_BASE_LO(uint32_t val)
+{
+       return ((val) << A6XX_IBO_4_BASE_LO__SHIFT) & A6XX_IBO_4_BASE_LO__MASK;
+}
+
+#define REG_A6XX_IBO_5                                         0x00000005
+#define A6XX_IBO_5_BASE_HI__MASK                               0x0001ffff
+#define A6XX_IBO_5_BASE_HI__SHIFT                              0
+static inline uint32_t A6XX_IBO_5_BASE_HI(uint32_t val)
+{
+       return ((val) << A6XX_IBO_5_BASE_HI__SHIFT) & A6XX_IBO_5_BASE_HI__MASK;
+}
+#define A6XX_IBO_5_DEPTH__MASK                                 0x3ffe0000
+#define A6XX_IBO_5_DEPTH__SHIFT                                        17
+static inline uint32_t A6XX_IBO_5_DEPTH(uint32_t val)
+{
+       return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK;
+}
+
 #define REG_A6XX_PDC_GPU_ENABLE_PDC                            0x00001140
 
 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR                                0x00001148

diff --git a/src/freedreno/registers/adreno_common.xml.h b/src/freedreno/registers/adreno_common.xml.h
index 43c18630cef9189654f40c7423b8e914002ee7a6..46c08b18d49ffb9234b0eb8beda33511970c5b8a 100644 (file)
--- a/src/freedreno/registers/adreno_common.xml.h
+++ b/src/freedreno/registers/adreno_common.xml.h
@@ -8,17 +8,17 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  42463 bytes, from 2018-11-19 13:44:03)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-05 15:25:53)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  43052 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 141895 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-14 13:03:07)
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
+- /work/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a2xx.xml          (  79608 bytes, from 2019-02-11 18:07:21)
+- /work/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-17 18:59:13)
+- /work/envytools/rnndb/adreno/adreno_pm4.xml    (  43155 bytes, from 2019-02-12 18:24:48)
+- /work/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-09-28 22:41:49)
+- /work/envytools/rnndb/adreno/a6xx.xml          ( 145596 bytes, from 2019-02-13 18:14:29)
+- /work/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-28 22:41:49)
+- /work/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-10 14:59:32)
 
 Copyright (C) 2013-2018 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)

diff --git a/src/freedreno/registers/adreno_pm4.xml.h b/src/freedreno/registers/adreno_pm4.xml.h
index 03efbfb29ca73c4123092d54731873895a07c2c3..e2bf63814173bd32d5e503b327c3958855d1857a 100644 (file)
--- a/src/freedreno/registers/adreno_pm4.xml.h
+++ b/src/freedreno/registers/adreno_pm4.xml.h
@@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  42463 bytes, from 2018-11-19 13:44:03)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-05 15:25:53)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  43052 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 141895 bytes, from 2018-12-21 18:21:34)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-14 13:03:07)
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
-
-Copyright (C) 2013-2018 by the following authors:
+- /work/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a2xx.xml          (  79608 bytes, from 2019-02-11 18:07:21)
+- /work/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-17 18:59:13)
+- /work/envytools/rnndb/adreno/adreno_pm4.xml    (  43155 bytes, from 2019-02-12 18:24:48)
+- /work/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-10 14:59:32)
+- /work/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-09-28 22:41:49)
+- /work/envytools/rnndb/adreno/a6xx.xml          ( 145596 bytes, from 2019-02-13 18:14:29)
+- /work/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-28 22:41:49)
+- /work/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-10 14:59:32)
+
+Copyright (C) 2013-2019 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
 
@@ -232,6 +232,7 @@ enum adreno_pm4_type3_packets {
        CP_SET_MODE = 99,
        CP_LOAD_STATE6_GEOM = 50,
        CP_LOAD_STATE6_FRAG = 52,
+       CP_LOAD_STATE6 = 54,
        IN_IB_PREFETCH_END = 23,
        IN_SUBBLK_PREFETCH = 31,
        IN_INSTR_PREFETCH = 32,
@@ -242,7 +243,6 @@ enum adreno_pm4_type3_packets {
        IN_INCR_UPDT_INSTR = 87,
        PKT4 = 4,
        CP_UNK_A6XX_14 = 20,
-       CP_UNK_A6XX_36 = 54,
        CP_UNK_A6XX_55 = 85,
        CP_REG_WRITE = 109,
 };
@@ -312,13 +312,14 @@ enum a6xx_state_block {
        SB6_GS_SHADER = 11,
        SB6_FS_SHADER = 12,
        SB6_CS_SHADER = 13,
-       SB6_SSBO = 14,
-       SB6_CS_SSBO = 15,
+       SB6_IBO = 14,
+       SB6_CS_IBO = 15,
 };
 
 enum a6xx_state_type {
        ST6_SHADER = 0,
        ST6_CONSTANTS = 1,
+       ST6_IBO = 3,
 };
 
 enum a6xx_state_src {
@@ -471,7 +472,7 @@ static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
 {
        return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
 }
-#define CP_LOAD_STATE6_0_STATE_TYPE__MASK                      0x00004000
+#define CP_LOAD_STATE6_0_STATE_TYPE__MASK                      0x0000c000
 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT                     14
 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
 {

diff --git a/src/freedreno/registers/update-headers.sh b/src/freedreno/registers/update-headers.sh
new file mode 100755 (executable)
index 0000000..4e521e8
--- /dev/null
+++ b/src/freedreno/registers/update-headers.sh
@@ -0,0 +1,14 @@
+#!/bin/sh
+
+d=$(dirname $0)
+
+rnndb=$1
+
+if [ ! -f $rnndb/rnndb/adreno/adreno_common.xml ]; then
+       echo directory does not look like envytools: $rnndb
+       exit 1
+fi
+
+for f in $d/*.xml.h; do
+       cp -v $rnndb/rnndb/adreno/$(basename $f) $d
+done

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index befb025930e1563da831690cfa91ae269c7fcfac..fad3c09a733a5257ed3274b9234fff2943e18b6f 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -458,8 +458,8 @@ emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
                return;
 
        switch (sb) {
-       case SB6_SSBO:
-       case SB6_CS_SSBO:
+       case SB6_IBO:
+       case SB6_CS_IBO:
                opcode = CP_LOAD_STATE6_GEOM;
                break;
        default:
@@ -922,7 +922,7 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
                emit_border_color(ctx, ring);
 
        if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
-               emit_ssbos(ctx, ring, SB6_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
+               emit_ssbos(ctx, ring, SB6_IBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
 
        if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_IMAGE)
                fd6_emit_images(ctx, ring, PIPE_SHADER_FRAGMENT);
@@ -992,7 +992,7 @@ fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 #endif
 
        if (dirty & FD_DIRTY_SHADER_SSBO)
-               emit_ssbos(ctx, ring, SB6_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
+               emit_ssbos(ctx, ring, SB6_CS_IBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
 
        if (dirty & FD_DIRTY_SHADER_IMAGE)
                fd6_emit_images(ctx, ring, PIPE_SHADER_COMPUTE);
@@ -1036,7 +1036,7 @@ t7              opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
        WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
        WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
        WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
-       WRITE(REG_A6XX_SP_UNKNOWN_AB20, 0);
+       WRITE(REG_A6XX_SP_IBO_COUNT, 0);
        WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
        WRITE(REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
        WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_image.c b/src/gallium/drivers/freedreno/a6xx/fd6_image.c
index cc33a00c4cd4107bec1405f7b5c37e364a872978..f4e3492154dccaad6dfaed8e24e1e10187d20244 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_image.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_image.c
@@ -38,8 +38,8 @@ static enum a6xx_state_block texsb[] = {
 };
 
 static enum a6xx_state_block imgsb[] = {
-       [PIPE_SHADER_COMPUTE] = SB6_CS_SSBO,
-       [PIPE_SHADER_FRAGMENT] = SB6_SSBO,
+       [PIPE_SHADER_COMPUTE] = SB6_CS_IBO,
+       [PIPE_SHADER_FRAGMENT] = SB6_IBO,
 };
 
 struct fd6_image {