{"addaw", one(0150300), one(0170700), "*wAd", m68000up },
{"addal", one(0150700), one(0170700), "*lAd", m68000up | mcf5200 },
-{"addib", one(0003000), one(0177700), "#b$b", m68000up },
-{"addiw", one(0003100), one(0177700), "#w$w", m68000up },
-{"addil", one(0003200), one(0177700), "#l$l", m68000up | mcf5200 },
+{"addib", one(0003000), one(0177700), "#b$s", m68000up },
+{"addiw", one(0003100), one(0177700), "#w$s", m68000up },
+{"addil", one(0003200), one(0177700), "#l$s", m68000up | mcf5200 },
{"addqb", one(0050000), one(0170700), "Qd$b", m68000up },
{"addqw", one(0050100), one(0170700), "Qd%w", m68000up },
/* The add opcode can generate the adda, addi, and addq instructions. */
{"addb", one(0050000), one(0170700), "Qd$b", m68000up },
-{"addb", one(0003000), one(0177700), "#b$b", m68000up },
+{"addb", one(0003000), one(0177700), "#b$s", m68000up },
{"addb", one(0150000), one(0170700), ";bDd", m68000up },
{"addb", one(0150400), one(0170700), "Dd~b", m68000up },
{"addw", one(0050100), one(0170700), "Qd%w", m68000up },
{"addw", one(0150300), one(0170700), "*wAd", m68000up },
-{"addw", one(0003100), one(0177700), "#w$w", m68000up },
+{"addw", one(0003100), one(0177700), "#w$s", m68000up },
{"addw", one(0150100), one(0170700), "*wDd", m68000up },
{"addw", one(0150500), one(0170700), "Dd~w", m68000up },
{"addl", one(0050200), one(0170700), "Qd%l", m68000up | mcf5200 },
-{"addl", one(0003200), one(0177700), "#l$l", m68000up | mcf5200 },
+{"addl", one(0003200), one(0177700), "#l$s", m68000up | mcf5200 },
{"addl", one(0150700), one(0170700), "*lAd", m68000up | mcf5200 },
{"addl", one(0150200), one(0170700), "*lDd", m68000up | mcf5200 },
{"addl", one(0150600), one(0170700), "Dd~l", m68000up | mcf5200 },
{"addxl", one(0150600), one(0170770), "DsDd", m68000up | mcf5200 },
{"addxl", one(0150610), one(0170770), "-s-d", m68000up },
-{"andib", one(0001000), one(0177700), "#b$b", m68000up },
-{"andib", one(0001074), one(0177777), "#bCb", m68000up },
-{"andiw", one(0001100), one(0177700), "#w$w", m68000up },
-{"andiw", one(0001174), one(0177777), "#wSw", m68000up },
-{"andil", one(0001200), one(0177700), "#l$l", m68000up | mcf5200 },
-{"andi", one(0001100), one(0177700), "#w$w", m68000up },
-{"andi", one(0001074), one(0177777), "#bCb", m68000up },
-{"andi", one(0001174), one(0177777), "#wSw", m68000up },
+{"andib", one(0001000), one(0177700), "#b$s", m68000up },
+{"andib", one(0001074), one(0177777), "#bCs", m68000up },
+{"andiw", one(0001100), one(0177700), "#w$s", m68000up },
+{"andiw", one(0001174), one(0177777), "#wSs", m68000up },
+{"andil", one(0001200), one(0177700), "#l$s", m68000up | mcf5200 },
+{"andi", one(0001100), one(0177700), "#w$s", m68000up },
+{"andi", one(0001074), one(0177777), "#bCs", m68000up },
+{"andi", one(0001174), one(0177777), "#wSs", m68000up },
/* The and opcode can generate the andi instruction. */
-{"andb", one(0001000), one(0177700), "#b$b", m68000up },
-{"andb", one(0001074), one(0177777), "#bCb", m68000up },
+{"andb", one(0001000), one(0177700), "#b$s", m68000up },
+{"andb", one(0001074), one(0177777), "#bCs", m68000up },
{"andb", one(0140000), one(0170700), ";bDd", m68000up },
{"andb", one(0140400), one(0170700), "Dd~b", m68000up },
-{"andw", one(0001100), one(0177700), "#w$w", m68000up },
-{"andw", one(0001174), one(0177777), "#wSw", m68000up },
+{"andw", one(0001100), one(0177700), "#w$s", m68000up },
+{"andw", one(0001174), one(0177777), "#wSs", m68000up },
{"andw", one(0140100), one(0170700), ";wDd", m68000up },
{"andw", one(0140500), one(0170700), "Dd~w", m68000up },
-{"andl", one(0001200), one(0177700), "#l$l", m68000up | mcf5200 },
+{"andl", one(0001200), one(0177700), "#l$s", m68000up | mcf5200 },
{"andl", one(0140200), one(0170700), ";lDd", m68000up | mcf5200 },
{"andl", one(0140600), one(0170700), "Dd~l", m68000up | mcf5200 },
{"and", one(0001100), one(0177700), "#w$w", m68000up },
-{"and", one(0001074), one(0177777), "#bCb", m68000up },
-{"and", one(0001174), one(0177777), "#wSw", m68000up },
+{"and", one(0001074), one(0177777), "#bCs", m68000up },
+{"and", one(0001174), one(0177777), "#wSs", m68000up },
{"and", one(0140100), one(0170700), ";wDd", m68000up },
{"and", one(0140500), one(0170700), "Dd~w", m68000up },
{"cpusha", one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up },
{"cpushl", one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up },
+{"cpushl", one(0x04e8), one(0xfff8), "as", mcf5200 },
{"cpushp", one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up },
#undef SCOPE_LINE
{"cmpaw", one(0130300), one(0170700), "*wAd", m68000up },
{"cmpal", one(0130700), one(0170700), "*lAd", m68000up | mcf5200 },
-{"cmpib", one(0006000), one(0177700), "#b;b", m68000up },
-{"cmpiw", one(0006100), one(0177700), "#w;w", m68000up },
-{"cmpil", one(0006200), one(0177700), "#l;l", m68000up | mcf5200 },
+{"cmpib", one(0006000), one(0177700), "#b;s", m68000up },
+{"cmpiw", one(0006100), one(0177700), "#w;s", m68000up },
+{"cmpil", one(0006200), one(0177700), "#l;s", m68000up | mcf5200 },
{"cmpmb", one(0130410), one(0170770), "+s+d", m68000up },
{"cmpmw", one(0130510), one(0170770), "+s+d", m68000up },
{"cmpml", one(0130610), one(0170770), "+s+d", m68000up | mcf5200 },
/* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */
-{"cmpb", one(0006000), one(0177700), "#b;b", m68000up },
+{"cmpb", one(0006000), one(0177700), "#b;s", m68000up },
{"cmpb", one(0130410), one(0170770), "+s+d", m68000up },
{"cmpb", one(0130000), one(0170700), ";bDd", m68000up },
{"cmpw", one(0130300), one(0170700), "*wAd", m68000up },
-{"cmpw", one(0006100), one(0177700), "#w;w", m68000up },
+{"cmpw", one(0006100), one(0177700), "#w;s", m68000up },
{"cmpw", one(0130510), one(0170770), "+s+d", m68000up },
{"cmpw", one(0130100), one(0170700), "*wDd", m68000up },
{"cmpl", one(0130700), one(0170700), "*lAd", m68000up | mcf5200 },
-{"cmpl", one(0006200), one(0177700), "#l;l", m68000up | mcf5200 },
+{"cmpl", one(0006200), one(0177700), "#l;s", m68000up | mcf5200 },
{"cmpl", one(0130610), one(0170770), "+s+d", m68000up | mcf5200 },
{"cmpl", one(0130200), one(0170700), "*lDd", m68000up | mcf5200 },
{"fmovecrx", two(0xF000, 0x5C00), two(0xF1FF, 0xFC00), "Ii#CF7", mfloat },
{"fmovemx", two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat },
+{"fmovemx", two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat },
{"fmovemx", two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat },
+{"fmovemx", two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat },
{"fmovemx", two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat },
{"fmovemx", two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat },
{"fmovemx", two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat },
{"fmovemx", two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat },
-{"fmovemx", two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat },
{"fmovemx", two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat },
{"fmovemx", two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat },
-{"fmovemx", two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat },
{"fmovemx", two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat },
{"fmovemx", two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat },
{"pea", one(0044100), one(0177700), "!s", m68000up|mcf5200 },
-{"pflusha", two(0xf000,0x2400), two(0xffff,0xffff), "", m68030 | m68851 },
{"pflusha", one(0xf518), one(0xfff8), "", m68040up },
+{"pflusha", two(0xf000,0x2400), two(0xffff,0xffff), "", m68030 | m68851 },
{"pflush", two(0xf000,0x3010), two(0xffc0,0xfe10), "T3T9", m68030|m68851 },
{"pflush", two(0xf000,0x3810), two(0xffc0,0xfe10), "T3T9&s", m68030|m68851 },