fhdl/namer: support ClockSignal and ResetSignal. Closes #24

diff --git a/migen/fhdl/namer.py b/migen/fhdl/namer.py
index eaf23a0c2718e86f64b029a08a03bf46f03f1651..e6c18cb08ebebecec322a3305ba1384c6ff67b18 100644 (file)
--- a/migen/fhdl/namer.py
+++ b/migen/fhdl/namer.py
@@ -227,8 +227,17 @@ class Namespace:
         self.counts = {k: 1 for k in reserved_keywords}
         self.sigs = {}
         self.pnd = pnd
+        self.clock_domains = dict()
 
     def get_name(self, sig):
+        if isinstance(sig, ClockSignal):
+            sig = self.clock_domains[sig.cd].clk
+        if isinstance(sig, ResetSignal):
+            sig = self.clock_domains[sig.cd].rst
+            if sig is None:
+                raise ValueError("Attempted to obtain name of non-existent "
+                                 "reset signal of domain "+sig.cd)
+
         if sig.name_override is not None:
             sig_name = sig.name_override
         else:

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index d5d878c9bf7459d495796490bcd239aa329c234e..232073052d90884cc8875d97a798732052d03a71 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -342,6 +342,7 @@ def convert(f, ios=None, name="top",
     ns = build_namespace(list_signals(f) \
         | list_special_ios(f, True, True, True) \
         | ios, _reserved_keywords)
+    ns.clock_domains = f.clock_domains
     r.ns = ns
 
     src = "/* Machine-generated using Migen */\n"