fhdl/specials: MemoryPort.clock should always be a ClockSignal

diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
index e4bc606033f59c6e8456a519f5709d1a16fb7c05..4137d746a7deb4d4f9ab192260811284c4020892 100644 (file)
--- a/migen/fhdl/specials.py
+++ b/migen/fhdl/specials.py
@@ -193,10 +193,7 @@ class _MemoryPort(Special):
         self.re = re
         self.we_granularity = we_granularity
         self.mode = mode
-        if isinstance(clock_domain, str):
-            self.clock = ClockSignal(clock_domain)
-        else:
-            self.clock = clock_domain
+        self.clock = ClockSignal(clock_domain)
 
     def iter_expressions(self):
         for attr, target_context in [