ILO_TEXTURE_CPU_WRITE;
unsigned i;
- assert(tex->base.target != PIPE_BUFFER && tex->hiz.bo);
+ assert(tex->base.target != PIPE_BUFFER &&
+ ilo_texture_can_enable_hiz(tex, level, first_slice, num_slices));
if (flags & ILO_TEXTURE_RENDER_WRITE) {
/*
* As it is only used to resolve HiZ right now, return early when there is
* no HiZ.
*/
- if (!tex->hiz.bo)
+ if (!ilo_texture_can_enable_hiz(tex, level, first_slice, num_slices))
return;
/*
* It is assumed there is at most one writer, and that readers read before
* writers write.
*/
- if (tex->hiz.bo) {
+ if (ilo_texture_can_enable_hiz(tex, level, first_slice, num_slices)) {
ilo_blit_resolve_slices_for_hiz(ilo, res, level,
first_slice, num_slices, flags);
}
struct pipe_depth_stencil_alpha_state dsa_state;
uint32_t uses;
- if (!tex->hiz.bo)
+ if (!ilo_texture_can_enable_hiz(tex,
+ zs->u.tex.level, zs->u.tex.first_layer,
+ zs->u.tex.last_layer - zs->u.tex.first_layer + 1))
return false;
if (!hiz_can_clear_zs(blitter, tex))
struct ilo_texture *tex = ilo_texture(res);
struct pipe_depth_stencil_alpha_state dsa_state;
- if (!tex->hiz.bo)
+ if (!ilo_texture_can_enable_hiz(tex, level, slice, 1))
return;
/*
struct ilo_texture *tex = ilo_texture(res);
struct pipe_depth_stencil_alpha_state dsa_state;
- if (!tex->hiz.bo)
+ if (!ilo_texture_can_enable_hiz(tex, level, slice, 1))
return;
/*
* same value (enabled or disabled) as Hierarchical Depth Buffer
* Enable."
*/
- separate_stencil = (tex->hiz.bo != NULL);
+ separate_stencil =
+ ilo_texture_can_enable_hiz(tex, level, first_layer, num_layers);
}
/*
}
}
- if (tex->hiz.bo) {
+ if (ilo_texture_can_enable_hiz(tex, level, first_layer, num_layers)) {
info->hiz.bo = tex->hiz.bo;
info->hiz.stride = tex->hiz.bo_stride;
info->hiz.tiling = INTEL_TILING_Y;
}
}
+static inline bool
+ilo_texture_can_enable_hiz(const struct ilo_texture *tex, unsigned level,
+ unsigned first_slice, unsigned num_slices)
+{
+ return (tex->hiz.bo != NULL);
+}
+
#endif /* ILO_RESOURCE_H */