Remove -waveform from xdc files

A 50% duty cycle is the default, so no need to use -waveform.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/fpga/arty_a7.xdc b/fpga/arty_a7.xdc
index 64e040537b3b78791a164b7c6fb4c238d7f0c311..309b12fe6393acbeefae5a172937ef77ce980c84 100644 (file)
--- a/fpga/arty_a7.xdc
+++ b/fpga/arty_a7.xdc
@@ -531,7 +531,7 @@ set_property CONFIG_MODE SPIx4 [current_design]
 # Clock constraints
 ################################################################################
 
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }];
+create_clock -add -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
 
 create_clock -name eth_rx_clk -period 40.0 [get_ports { eth_clocks_rx }]
 

diff --git a/fpga/cmod_a7-35.xdc b/fpga/cmod_a7-35.xdc
index 3492d54c425ab3ca008922a7155bf2e3941cc65a..4444e2a19eeb8bcfd8801f96223b89140a446705 100644 (file)
--- a/fpga/cmod_a7-35.xdc
+++ b/fpga/cmod_a7-35.xdc
@@ -1,6 +1,6 @@
 ## Clock signal 12 MHz
 set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
-create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {ext_clk}];
+create_clock -add -name sys_clk_pin -period 83.33 [get_ports {ext_clk}];
 
 set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
 set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd  }];

diff --git a/fpga/genesys2.xdc b/fpga/genesys2.xdc
index 826e5f4670774c1d64adde796ba54a215d367f34..967a1686ec74008218b46e34f58558ccd7d07537 100644 (file)
--- a/fpga/genesys2.xdc
+++ b/fpga/genesys2.xdc
@@ -3,8 +3,8 @@
 ## Clock & Reset
 set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { clk200_n }]
 set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { clk200_p }]
-create_clock -period 5.000 -name tc_clk100_p -waveform {0.000 2.500} [get_ports clk200_p]
-create_clock -period 5.000 -name tc_clk100_n -waveform {2.500 5.000} [get_ports clk200_n]
+create_clock -period 5.000 -name tc_clk100_p [get_ports clk200_p]
+create_clock -period 5.000 -name tc_clk100_n [get_ports clk200_n]
 
 set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { ext_rst }]
 

diff --git a/fpga/nexys-video.xdc b/fpga/nexys-video.xdc
index 85c73316e3b77f2495390d775ee81bf3d52b3d47..6a46627b9de883b94558a0c2df49358f3213543e 100644 (file)
--- a/fpga/nexys-video.xdc
+++ b/fpga/nexys-video.xdc
@@ -313,7 +313,7 @@ set_property CONFIG_MODE SPIx4 [current_design]
 # Clock constraints
 ################################################################################
 
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }];
+create_clock -add -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
 
 ################################################################################
 # False path constraints (from LiteX as they relate to LiteDRAM)

diff --git a/fpga/nexys_a7.xdc b/fpga/nexys_a7.xdc
index a572772e6e144dbf7fa464ab5601ebd3bb95cd5e..aa1af2259a6e1f721ec1190c4b5226df3d188889 100644 (file)
--- a/fpga/nexys_a7.xdc
+++ b/fpga/nexys_a7.xdc
@@ -1,5 +1,5 @@
 set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports ext_clk]
-create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports ext_clk]
+create_clock -period 10.000 -name sys_clk_pin -add [get_ports ext_clk]
 
 set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports ext_rst]