and currently responsible for coordinating the design of a fully Libre
RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
+* Xing GUO(xing) - undergraduate (3rd year) from Southeast
+ University, EE student, C/C++, Python, Verilog, assembly(not very proficient),
+ Haskell(not very proficient). RTL design, server maintenance.
+ Email: higuoxing at gmail dot com
+
Hardware available:
* lkcl: ZC706