[AArch64] Use scvtf fbits option where appropriate
authorJoel Hutton <Joel.Hutton@arm.com>
Mon, 19 Aug 2019 16:55:20 +0000 (16:55 +0000)
committerAndre Vieira <avieira@gcc.gnu.org>
Mon, 19 Aug 2019 16:55:20 +0000 (16:55 +0000)
gcc/ChangeLog:
2019-08-19  Joel Hutton  <Joel.Hutton@arm.com>

* config/aarch64/aarch64-protos.h (aarch64_fpconst_pow2_recip): New prototype
* config/aarch64/aarch64.c (aarch64_fpconst_pow2_recip): New function
* config/aarch64/aarch64.md (*aarch64_<su_optab>cvtf<fcvt_target><GPF:mode>2_mult): New pattern
(*aarch64_<su_optab>cvtf<fcvt_iesize><GPF:mode>2_mult): New pattern
* config/aarch64/constraints.md (Dt): New constraint
* config/aarch64/predicates.md (aarch64_fpconst_pow2_recip): New predicate

gcc/testsuite/ChangeLog:
2019-08-19  Joel Hutton  <Joel.Hutton@arm.com>

* gcc.target/aarch64/fmul_scvtf_1.c: New test.

From-SVN: r274676

gcc/ChangeLog
gcc/config/aarch64/aarch64-protos.h
gcc/config/aarch64/aarch64.c
gcc/config/aarch64/aarch64.md
gcc/config/aarch64/constraints.md
gcc/config/aarch64/predicates.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/aarch64/fmul_scvtf_1.c [new file with mode: 0644]

index ccc63c24a711d3d9b6c75b7a65f9ec3b2ccc8282..895e5f12792cb0120bedb30905f46d908a52890a 100644 (file)
@@ -1,3 +1,12 @@
+2019-08-19  Joel Hutton  <Joel.Hutton@arm.com>
+
+       * config/aarch64/aarch64-protos.h (aarch64_fpconst_pow2_recip): New prototype
+       * config/aarch64/aarch64.c (aarch64_fpconst_pow2_recip): New function
+       * config/aarch64/aarch64.md (*aarch64_<su_optab>cvtf<fcvt_target><GPF:mode>2_mult): New pattern
+       (*aarch64_<su_optab>cvtf<fcvt_iesize><GPF:mode>2_mult): New pattern
+       * config/aarch64/constraints.md (Dt): New constraint
+       * config/aarch64/predicates.md (aarch64_fpconst_pow2_recip): New predicate
+
 2019-08-19  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/91403
index 89e5e28aeeba0d0a5403c7b614d8db31c99001d0..c4b73d26df608df153a58f877d67f61487805c46 100644 (file)
@@ -525,6 +525,7 @@ enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx);
 enum reg_class aarch64_regno_regclass (unsigned);
 int aarch64_asm_preferred_eh_data_format (int, int);
 int aarch64_fpconst_pow_of_2 (rtx);
+int aarch64_fpconst_pow2_recip (rtx);
 machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
                                                       machine_mode);
 int aarch64_uxt_size (int, HOST_WIDE_INT);
index 84341c041cf22b021916d3dbcff0a0a19377fdd7..be0162244a28ea1609087648e45a763445826969 100644 (file)
@@ -19750,6 +19750,29 @@ aarch64_fpconst_pow_of_2 (rtx x)
   return exact_log2 (real_to_integer (r));
 }
 
+/* If X is a positive CONST_DOUBLE with a value that is the reciprocal of a
+   power of 2 (i.e 1/2^n) return the number of float bits. e.g. for x==(1/2^n)
+   return n. Otherwise return -1.  */
+
+int
+aarch64_fpconst_pow2_recip (rtx x)
+{
+  REAL_VALUE_TYPE r0;
+
+  if (!CONST_DOUBLE_P (x))
+    return -1;
+
+  r0 = *CONST_DOUBLE_REAL_VALUE (x);
+  if (exact_real_inverse (DFmode, &r0)
+      && !REAL_VALUE_NEGATIVE (r0))
+    {
+       int ret = exact_log2 (real_to_integer (&r0));
+       if (ret >= 1 && ret <= 32)
+           return ret;
+    }
+  return -1;
+}
+
 /* If X is a vector of equal CONST_DOUBLE values and that value is
    Y, return the aarch64_fpconst_pow_of_2 of Y.  Otherwise return -1.  */
 
index cf561f00bb0bcd995adc4c2633ab1b5319339ae1..9a07f631010f16edc82fa6d990e61336196f17ec 100644 (file)
   [(set_attr "type" "f_cvtf2i")]
 )
 
+;; Equal width integer to fp and multiply combine.
+(define_insn "*aarch64_<su_optab>cvtf<fcvt_target><GPF:mode>2_mult"
+  [(set (match_operand:GPF 0 "register_operand" "=w,w")
+       (mult:GPF (FLOATUORS:GPF
+                  (match_operand:<FCVT_TARGET> 1 "register_operand" "w,?r"))
+                  (match_operand:GPF 2 "aarch64_fp_pow2_recip" "Dt,Dt")))]
+  "TARGET_FLOAT"
+  {
+    operands[2] = GEN_INT (aarch64_fpconst_pow2_recip (operands[2]));
+    switch (which_alternative)
+    {
+      case 0:
+       return "<su_optab>cvtf\t%<GPF:s>0, %<s>1, #%2";
+      case 1:
+       return "<su_optab>cvtf\t%<GPF:s>0, %<w1>1, #%2";
+      default:
+       gcc_unreachable ();
+    }
+  }
+  [(set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f")
+   (set_attr "arch" "simd,fp")]
+)
+
+;; Unequal width integer to fp and multiply combine.
+(define_insn "*aarch64_<su_optab>cvtf<fcvt_iesize><GPF:mode>2_mult"
+  [(set (match_operand:GPF 0 "register_operand" "=w")
+       (mult:GPF (FLOATUORS:GPF
+                  (match_operand:<FCVT_IESIZE> 1 "register_operand" "r"))
+                  (match_operand:GPF 2 "aarch64_fp_pow2_recip" "Dt")))]
+  "TARGET_FLOAT"
+  {
+    operands[2] = GEN_INT (aarch64_fpconst_pow2_recip (operands[2]));
+    return "<su_optab>cvtf\t%<GPF:s>0, %<w2>1, #%2";
+  }
+  [(set_attr "type" "f_cvti2f")]
+)
+
+;; Equal width integer to fp conversion.
 (define_insn "<optab><fcvt_target><GPF:mode>2"
   [(set (match_operand:GPF 0 "register_operand" "=w,w")
         (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,?r")))]
    (set_attr "arch" "simd,fp")]
 )
 
+;; Unequal width integer to fp conversions.
 (define_insn "<optab><fcvt_iesize><GPF:mode>2"
   [(set (match_operand:GPF 0 "register_operand" "=w")
         (FLOATUORS:GPF (match_operand:<FCVT_IESIZE> 1 "register_operand" "r")))]
index 1a43beee994af5a8279a883f5edcc2d2fca461f7..9326beca87d9ffa1d0b0977bcb556fdee861d2a1 100644 (file)
       (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
                                                 QImode)")))
 
+(define_constraint "Dt"
+  "@internal
+ A const_double which is the reciprocal of an exact power of two, can be
+ used in an scvtf with fract bits operation"
+ (and (match_code "const_double")
+      (match_test "aarch64_fpconst_pow2_recip (op) > 0")))
+
 (define_constraint "Dl"
   "@internal
  A constraint that matches vector of immediates for left shifts."
index 593b1be29df9b0eca39e0c75e93f7e51ad61ac7b..d8c377994d6f11a58683b19d7ae9d594e5033561 100644 (file)
   (and (match_code "const_double")
        (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
 
+(define_predicate "aarch64_fp_pow2_recip"
+  (and (match_code "const_double")
+       (match_test "aarch64_fpconst_pow2_recip (op) > 0")))
+
 (define_predicate "aarch64_fp_vec_pow2"
   (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
 
index ad514b11b8aa0c0c78e0b4f409f054d593d18e19..6f0bec89379eec92b016148a1c2fca42544b1be9 100644 (file)
@@ -1,3 +1,7 @@
+2019-08-19  Joel Hutton  <Joel.Hutton@arm.com>
+
+       * gcc.target/aarch64/fmul_scvtf_1.c: New test.
+
 2019-08-19  Marek Polacek  <polacek@redhat.com>
 
        PR c++/91264 - detect modifying const objects in constexpr.
diff --git a/gcc/testsuite/gcc.target/aarch64/fmul_scvtf_1.c b/gcc/testsuite/gcc.target/aarch64/fmul_scvtf_1.c
new file mode 100644 (file)
index 0000000..8bfe06a
--- /dev/null
@@ -0,0 +1,140 @@
+/* { dg-do run } */
+/* { dg-options "-save-temps -O2 -fno-inline" } */
+
+#define FUNC_DEFS(__a)                         \
+float                                          \
+fsfoo##__a (int x)                             \
+{                                              \
+  return ((float) x)/(1lu << __a);             \
+}                                              \
+float                                          \
+fusfoo##__a (unsigned int x)                   \
+{                                              \
+  return ((float) x)/(1lu << __a);             \
+}                                              \
+float                                          \
+fslfoo##__a (long long x)                      \
+{                                              \
+  return ((float) x)/(1lu << __a);             \
+}                                              \
+float                                          \
+fulfoo##__a (unsigned long long x)             \
+{                                              \
+  return ((float) x)/(1lu << __a);             \
+}                                              \
+
+#define FUNC_DEFD(__a)                         \
+double                                         \
+dsfoo##__a (int x)                             \
+{                                              \
+  return ((double) x)/(1lu << __a);            \
+}                                              \
+double                                         \
+dusfoo##__a (unsigned int x)                   \
+{                                              \
+  return ((double) x)/(1lu << __a);            \
+}                                              \
+double                                         \
+dslfoo##__a (long long x)                      \
+{                                              \
+  return ((double) x)/(1lu << __a);            \
+}                                              \
+double                                         \
+dulfoo##__a (unsigned long long x)             \
+{                                              \
+  return ((double) x)/(1lu << __a);            \
+}
+
+FUNC_DEFS (4)
+       /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#4" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#4" 1 } } */
+       /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#4" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#4" 1 } } */
+
+FUNC_DEFD (4)
+       /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#4" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#4" 1 } } */
+       /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#4" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#4" 1 } } */
+
+FUNC_DEFS (8)
+       /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#8" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#8" 1 } } */
+       /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#8" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#8" 1 } } */
+
+FUNC_DEFD (8)
+       /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#8" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#8" 1 } } */
+       /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#8" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#8" 1 } } */
+
+FUNC_DEFS (16)
+       /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#16" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#16" 1 } } */
+       /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#16" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#16" 1 } } */
+
+FUNC_DEFD (16)
+       /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#16" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#16" 1 } } */
+       /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#16" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#16" 1 } } */
+
+FUNC_DEFS (32)
+       /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#32" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#32" 1 } } */
+       /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#32" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#32" 1 } } */
+
+FUNC_DEFD (32)
+       /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#32" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#32" 1 } } */
+       /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#32" 1 } } */
+       /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#32" 1 } } */
+
+#define FUNC_TESTS(__a, __b)                                   \
+do                                                             \
+{                                                              \
+  if (fsfoo##__a (__b) !=  ((int) i) * (1.0f/(1lu << __a)) )   \
+    __builtin_abort ();                                                \
+  if (fusfoo##__a (__b) != ((int) i) * (1.0f/(1lu << __a)) )   \
+    __builtin_abort ();                                                \
+  if (fslfoo##__a (__b) != ((int) i) * (1.0f/(1lu << __a)) )   \
+    __builtin_abort ();                                                \
+  if (fulfoo##__a (__b) != ((int) i) * (1.0f/(1lu << __a)) )   \
+    __builtin_abort ();                                                \
+} while (0)
+
+#define FUNC_TESTD(__a, __b)                                   \
+do                                                             \
+{                                                              \
+  if (dsfoo##__a (__b) !=  ((int) i) * (1.0d/(1lu << __a)) )   \
+    __builtin_abort ();                                                \
+  if (dusfoo##__a (__b) != ((int) i) * (1.0d/(1lu << __a)) )   \
+    __builtin_abort ();                                                \
+  if (dslfoo##__a (__b) != ((int) i) * (1.0d/(1lu << __a)) )   \
+    __builtin_abort ();                                                \
+  if (dulfoo##__a (__b) != ((int) i) * (1.0d/(1lu << __a)) )   \
+    __builtin_abort ();                                                \
+} while (0)
+
+int
+main (void)
+{
+       int i;
+
+       for (i = 0; i < 32; i ++)
+       {
+               FUNC_TESTS (4, i);
+               FUNC_TESTS (8, i);
+               FUNC_TESTS (16, i);
+               FUNC_TESTS (32, i);
+
+               FUNC_TESTD (4, i);
+               FUNC_TESTD (8, i);
+               FUNC_TESTD (16, i);
+               FUNC_TESTD (32, i);
+       }
+       return 0;
+}