(no commit message)

diff --git a/openpower/sv/major_opcode_allocation.mdwn b/openpower/sv/major_opcode_allocation.mdwn
index 3778a137a384a19c5e5d6c6fddc00fc44199ae77..3f15c180ffa4344e42ab88d8affa3f7372b4db73 100644 (file)
--- a/openpower/sv/major_opcode_allocation.mdwn
+++ b/openpower/sv/major_opcode_allocation.mdwn
@@ -15,14 +15,17 @@ This **only** in "LibreSOC Mode".  Candidates for moving elsewhere
 include mulli, twi and tdi.
 
 * 2 opcodes for 16-bit Compressed instructions with 11 bits available
-* 2 opcodes are required in order to give SV-P48 (and SV-C32) the 11 bits needed for prefixing
-* 2 opcodes are likewise required for SV-P64 (and SV-C48) to have 27 bits available
-* 2 opcodes for SV VBLOCK
+* 2 opcodes are required in order to give SV-P48 the 11 bits needed for prefixing
+* 2 opcodes are likewise required for SV-P64 to have 27 bits available
+* 2 opcodes for SV-C32 and SV-C48 (32 bit versions of P48 and P64)
 
 With only 11 bits for 16-bit Compressed, it may be better to use the
-opportunity to switch into "16 bit mode".  Interestingly SV-P32 could
+opportunity to switch into "16 bit mode".  Interestingly SV-C32 could
 likewise switch into the same.
 
+VBLOCK can be added later by using further VSX dedicated major opcodes
+(EXT62, EXT63)
+
 # LE/BE complications.
 
 See <https://bugs.libre-soc.org/show_bug.cgi?id=529> for discussion
@@ -56,6 +59,10 @@ With the Major Opcode then always being in the 1st 2 bytes it becomes
 much simpler for the pre-analysis phase to determine instruction length,
 regardless of what that length is (16/32/48/64/VBLOCK).
 
+Option 3:
+
+Just as in VLE, require instructions to be in BE order. Data, which has nothing to do with instruction order, may optionally remain in LE order.
+
 # 16 bit Compressed
 
 See [[16_bit_compressed]]