* config/h8300.h: Fix comment typos.
* config/h8300/h8300.md: Likewise.
* config/h8300/lib1funcs.asm: Likewise.
From-SVN: r36248
+2000-09-07 Kazu Hirata <kazu@hxi.com>
+
+ * config/h8300.h: Fix comment typos.
+ * config/h8300/h8300.md: Likewise.
+ * config/h8300/lib1funcs.asm: Likewise.
+
Thu 07-Sep-2000 21:29:00 BST Neil Booth <NeilB@earthling.net>
* Makefile.in: Remove references to cppulp.{c,o}.
This is for debugging the compiler only. */
#define TARGET_RTL_DUMP (target_flags & 2048)
-/* Select between the h8/300 and h8/300h cpus. */
+/* Select between the H8/300 and H8/300H CPUs. */
#define TARGET_H8300 (! TARGET_H8300H && ! TARGET_H8300S)
#define TARGET_H8300H (target_flags & 4096)
#define TARGET_H8300S (target_flags & 1)
-/* Align all values on the h8/300h the same way as the h8/300. Specifically,
+/* Align all values on the H8/300H the same way as the H8/300. Specifically,
32 bit and larger values are aligned on 16 bit boundaries.
- This is all the hardware requires, but the default is 32 bits for the 300h.
+ This is all the hardware requires, but the default is 32 bits for the 300H.
??? Now watch someone add hardware floating point requiring 32 bit
alignment. */
#define TARGET_ALIGN_300 (target_flags & 8192)
;; Long term, we want to expose the "e" half to the compiler (gives us
;; 8 more 16bit registers). At that point addhi and subhi can't use adds/subs.
-;; There's currently no way to have a insv/extzv expander for the h8/300h
-;; because word_mode is different for the h8/300 and h8/300h.
+;; There's currently no way to have a insv/extzv expander for the H8/300H
+;; because word_mode is different for the H8/300 and H8/300H.
;; Shifts/rotates by small constants should be handled by special
;; patterns so we get the length and cc status correct.
"
{
/* Force operand1 into a register if we're compiling
- for the h8/300. */
+ for the H8/300. */
if (GET_CODE (operands[1]) != REG && TARGET_H8300)
operands[1] = force_reg (HImode, operands[1]);
}")
;; MULTIPLY INSTRUCTIONS
;; ----------------------------------------------------------------------
-;; Note that the h8/300 can only handle umulqihi3.
+;; Note that the H8/300 can only handle umulqihi3.
(define_insn "mulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
;; give the optimizer more cracks at the code. However, we wish to do things
;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
-;; There is rtl to handle this (rotate + and), but the h8/300 doesn't handle
+;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
;; to detect cases it can optimize.
;;
-;; libgcc1 routines for the Hitachi h8/300 cpu.
-;; Contributed by Steve Chamberlain.
-;; sac@cygnus.com
+;; libgcc1 routines for the Hitachi H8/300 CPU.
+;; Contributed by Steve Chamberlain <sac@cygnus.com>
-/* Copyright (C) 1994 Free Software Foundation, Inc.
+/* Copyright (C) 1994, 2000 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the