arch-arm: Disable HVC when SCR_EL3.HCE is 0

This was already implemented for AArch32 but it had been wrongly
removed by:

https://gem5-review.googlesource.com/c/public/gem5/+/31394

Change-Id: Ida303d5ccb5d8568ca4e7faaedf9b4efd1cd88b5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32636
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 3ee0d618fc91f5c2a03d072f6edd90f5c2889e5c..5439baae6876add2974a7fe929448f6475a5059e 100644 (file)
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -119,12 +119,15 @@ let {{
     exec_output += PredOpExecute.subst(smcIop)
 
     hvcCode = '''
+    HCR  hcr  = Hcr;
     CPSR cpsr = Cpsr;
+    SCR  scr  = Scr;
 
     // Filter out the various cases where this instruction isn't defined
     if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
         (cpsr.mode == MODE_USER) ||
-        (isSecure(xc->tcBase()) && !IsSecureEL2Enabled(xc->tcBase()))) {
+        (isSecure(xc->tcBase()) && !IsSecureEL2Enabled(xc->tcBase())) ||
+        (ArmSystem::haveSecurity(xc->tcBase()) ? !scr.hce : hcr.hcd)) {
         fault = disabledFault();
     } else {
         fault = std::make_shared<HypervisorCall>(machInst, imm);