# License: BSD
import math
-from copy import copy
from migen import *
from migen.util.misc import xdir
-from migen.genlib.record import *
from migen.genlib import fifo
from migen.genlib.cdc import MultiReg, PulseSynchronizer
last_n.eq(last)
)
first = first_n
- last = last_n
+ last = last_n
self.comb += [
source.first.eq(first),
source.last.eq(last)
class _FIFOWrapper(Module):
def __init__(self, fifo_class, layout, depth):
- self.sink = Endpoint(layout)
- self.source = Endpoint(layout)
+ self.sink = sink = Endpoint(layout)
+ self.source = source = Endpoint(layout)
# # #
- description = self.sink.description
+ description = sink.description
fifo_layout = [
("payload", description.payload_layout),
("param", description.param_layout),
("last", 1)
]
- self.submodules.fifo = fifo_class(layout_len(fifo_layout), depth)
+ self.submodules.fifo = fifo = fifo_class(layout_len(fifo_layout), depth)
fifo_in = Record(fifo_layout)
fifo_out = Record(fifo_layout)
self.comb += [
- self.fifo.din.eq(fifo_in.raw_bits()),
- fifo_out.raw_bits().eq(self.fifo.dout)
+ fifo.din.eq(fifo_in.raw_bits()),
+ fifo_out.raw_bits().eq(fifo.dout)
]
self.comb += [
- self.sink.ready.eq(self.fifo.writable),
- self.fifo.we.eq(self.sink.valid),
- fifo_in.first.eq(self.sink.first),
- fifo_in.last.eq(self.sink.last),
- fifo_in.payload.eq(self.sink.payload),
- fifo_in.param.eq(self.sink.param),
-
- self.source.valid.eq(self.fifo.readable),
- self.source.first.eq(fifo_out.first),
- self.source.last.eq(fifo_out.last),
- self.source.payload.eq(fifo_out.payload),
- self.source.param.eq(fifo_out.param),
- self.fifo.re.eq(self.source.ready)
+ sink.ready.eq(fifo.writable),
+ fifo.we.eq(sink.valid),
+ fifo_in.first.eq(sink.first),
+ fifo_in.last.eq(sink.last),
+ fifo_in.payload.eq(sink.payload),
+ fifo_in.param.eq(sink.param),
+
+ source.valid.eq(fifo.readable),
+ source.first.eq(fifo_out.first),
+ source.last.eq(fifo_out.last),
+ source.payload.eq(fifo_out.payload),
+ source.param.eq(fifo_out.param),
+ fifo.re.eq(source.ready)
]
shift_register = Signal(io_lcm)
i_cases = {}
- i_data = Signal(i_dw)
+ i_data = Signal(i_dw)
if msb_first:
self.comb += i_data.eq(sink.data)
else:
self.sync += If(sink.valid & sink.ready, Case(i_count, i_cases))
o_cases = {}
- o_data = Signal(o_dw)
+ o_data = Signal(o_dw)
for i in range(io_lcm//o_dw):
o_cases[i] = o_data.eq(shift_register[io_lcm - o_dw*(i+1):io_lcm - o_dw*i])
self.comb += Case(o_count, o_cases)
class Unpack(Module):
def __init__(self, n, layout_to, reverse=False):
self.source = source = Endpoint(layout_to)
- description_from = copy(source.description)
+ description_from = Endpoint(layout_to).description
description_from.payload_layout = pack_layout(description_from.payload_layout, n)
self.sink = sink = Endpoint(description_from)
class Pack(Module):
def __init__(self, layout_from, n, reverse=False):
self.sink = sink = Endpoint(layout_from)
- description_to = copy(sink.description)
+ description_to = Endpoint(layout_from).description
description_to.payload_layout = pack_layout(description_to.payload_layout, n)
self.source = source = Endpoint(description_to)
demux = Signal(max=n)
- load_part = Signal()
+ load_part = Signal()
strobe_all = Signal()
cases = {}
for i in range(n):