(no commit message)

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index d438df69339881d3ae47a8e33f4d96e0fa53c84e..a57331cb4b5be1a38305e807fca1fcaa6deeaa6a 100644 (file)
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -222,7 +222,7 @@ four aspects:
 
 ## answers to 2, RM Modes
 
-Normal Mode:
+**Normal Mode:**
 
 * simple mode is straight vectorisation.
 * reduce mode
@@ -232,9 +232,15 @@ Normal Mode:
 
 simple mode is fine including on predication but has a CHANGE OF BEHAVIOUR. first bit of src/dest is used when zeroing is on, but first ENABLED bit of predicate is used when VL>1.
 
-reduce mode is unaffected (meaningless)
+reduce mode is unaffected (meaningless) on a scalar operation
 
-## answers to 4, loops
+fail-first with or without VLI, should be unaffected, but what should VL be truncated to? the override VL=1? (or VL=0 when VLI is set?)
+
+saturation mode is fine
+
+predicate-result should be fine as well.
+
+## answers to 4, loops/uses
 
 **REMAP**