i965: sandybridge pipe control workaround before write cache flush

Must issue a pipe control with any non-zero post sync op before
write cache flush = 1 pipe control.

diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index ff741fc39ab28bbba863cea01f65ed980e74015f..9b39823917243a85cb51e6df425ebe8809280a3b 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -264,10 +264,18 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
    struct intel_context *intel = batch->intel;
 
    if (intel->gen >= 6) {
-      BEGIN_BATCH(4);
+      BEGIN_BATCH(8);
+
+      /* XXX workaround: issue any post sync != 0 before write cache flush = 1 */
+      OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+      OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
+      OUT_BATCH(0); /* write address */
+      OUT_BATCH(0); /* write data */
+
       OUT_BATCH(_3DSTATE_PIPE_CONTROL);
       OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
                PIPE_CONTROL_WRITE_FLUSH |
+               PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                PIPE_CONTROL_NO_WRITE);
       OUT_BATCH(0); /* write address */
       OUT_BATCH(0); /* write data */

diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h
index c1a281f261ed607b360bf14e9d4caa60df20fe92..955b100b212e088b921badfebcd397665e42c434 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_reg.h
+++ b/src/mesa/drivers/dri/intel/intel_reg.h
@@ -55,6 +55,11 @@
  * additional flushing control.
  */
 #define _3DSTATE_PIPE_CONTROL          (CMD_3D | (3 << 27) | (2 << 24) | 2)
+#define PIPE_CONTROL_CS_STALL          (1 << 20)
+#define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET       (1 << 19)
+#define PIPE_CONTROL_TLB_INVALIDATE    (1 << 18)
+#define PIPE_CONTROL_SYNC_GFDT         (1 << 17)
+#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1 << 16)
 #define PIPE_CONTROL_NO_WRITE          (0 << 14)
 #define PIPE_CONTROL_WRITE_IMMEDIATE   (1 << 14)
 #define PIPE_CONTROL_WRITE_DEPTH_COUNT (2 << 14)
@@ -62,7 +67,14 @@
 #define PIPE_CONTROL_DEPTH_STALL       (1 << 13)
 #define PIPE_CONTROL_WRITE_FLUSH       (1 << 12)
 #define PIPE_CONTROL_INSTRUCTION_FLUSH (1 << 11)
+#define PIPE_CONTROL_TC_FLUSH          (1 << 10) /* GM45+ only */
+#define PIPE_CONTROL_ISP_DIS           (1 << 9)
 #define PIPE_CONTROL_INTERRUPT_ENABLE  (1 << 8)
+/* GT */
+#define PIPE_CONTROL_VF_CACHE_INVALIDATE       (1 << 4)
+#define PIPE_CONTROL_CONST_CACHE_INVALIDATE    (1 << 3)
+#define PIPE_CONTROL_STATE_CACHE_INVALIDATE    (1 << 2)
+#define PIPE_CONTROL_DEPTH_CACHE_FLUSH         (1 << 0)
 #define PIPE_CONTROL_PPGTT_WRITE       (0 << 2)
 #define PIPE_CONTROL_GLOBAL_GTT_WRITE  (1 << 2)