Output has priority over input when stitching in abc9

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index f2662e0cba3149c918dfed474ca14a4cd5967552..6fdf987f0b4529077bdcad20718b926d7a25b068 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -694,30 +694,27 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                int in_wires = 0, out_wires = 0;
 
                // Stitch in mapped_mod's inputs/outputs into module
-               for (auto &it : mapped_mod->wires_) {
-                       RTLIL::Wire *w = it.second;
-                       if (!w->port_input && !w->port_output)
-                               continue;
-                       RTLIL::Wire *wire = module->wire(w->name);
+               for (auto port : mapped_mod->ports) {
+                       RTLIL::Wire *w = mapped_mod->wire(port);
+                       RTLIL::Wire *wire = module->wire(port);
                        log_assert(wire);
-                       RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
+                       RTLIL::Wire *remap_wire = module->wire(remap_name(port));
                        RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
                        log_assert(GetSize(signal) >= GetSize(remap_wire));
 
-                       log_assert(w->port_input || w->port_output);
                        RTLIL::SigSig conn;
-                       if (w->port_input) {
-                               conn.first = remap_wire;
-                               conn.second = signal;
-                               in_wires++;
-                               module->connect(conn);
-                       }
                        if (w->port_output) {
                                conn.first = signal;
                                conn.second = remap_wire;
                                out_wires++;
                                module->connect(conn);
                        }
+                       else if (w->port_input) {
+                               conn.first = remap_wire;
+                               conn.second = signal;
+                               in_wires++;
+                               module->connect(conn);
+                       }
                }
 
                for (auto &it : bit_users)