add images

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 1ca0cab719f2127f74bb42f9a8add8e9d8d682c8..c100bdf41b57a1db6b54c55ccaa9d97012c089eb 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -366,8 +366,8 @@ for (int i = 0; i < VL; ++i)
    \item key is int regfile number or FP regfile number (1 bit)\vspace{6pt}
    \item register to be predicated if referred to (5 bits, key)\vspace{6pt}
    \item register to store actual predication in (5 bits, value)\vspace{6pt}
-   \item predication is inverted (1 bit)\vspace{6pt}
-   \item non-predicated elements are to be zero'd (1 bit)\vspace{6pt}
+   \item predication is inverted Y/N (1 bit)\vspace{6pt}
+   \item non-predicated elements are to be zero'd Y/N (1 bit)\vspace{6pt}
   \end{itemize}
   Notes:\vspace{10pt}
    \begin{itemize}