FDCE_1 does not have IS_CLR_INVERTED

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index ee9d486840d4bf071703705c4494fffe253b170d..cf39bd45b06556de204307aa3b5091ddd1c197fc 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -408,7 +408,7 @@ module FDCE_1 (
   always @* Q = \$nextQ ;
 `else
   assign \$currQ = Q;
-  always @(negedge C, posedge CLR) if (CLR == !IS_CLR_INVERTED) Q <= 1'b0; else Q <= \$nextQ ;
+  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
 `endif
 endmodule