radv_flush_indirect_descriptor_sets(cmd_buffer, pipeline);
}
+ MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
+ cmd_buffer->cs,
+ MAX_SETS * MESA_SHADER_STAGES * 4);
+
for (i = 0; i < MAX_SETS; i++) {
if (!(cmd_buffer->state.descriptors_dirty & (1u << i)))
continue;
}
cmd_buffer->state.descriptors_dirty = 0;
cmd_buffer->state.push_descriptors_dirty = false;
+ assert(cmd_buffer->cs->cdw <= cdw_max);
}
static void
va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo);
va += offset;
+ MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
+ cmd_buffer->cs, MESA_SHADER_STAGES * 4);
if (stages & VK_SHADER_STAGE_VERTEX_BIT)
radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,
AC_UD_PUSH_CONSTANTS, va);
AC_UD_PUSH_CONSTANTS, va);
cmd_buffer->push_constant_stages &= ~stages;
+ assert(cmd_buffer->cs->cdw <= cdw_max);
}
static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,