arch-sparc: Replace any getDTBPtr/getITBPtr usage

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I931b7b4203b9ae18f46e2d985c7c7b5b339cb9e6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34982
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 33ba921db69f790915c650685e88547222289001..53e75765fcc147589a4af405d923764d066f4649 100644 (file)
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -30,9 +30,9 @@
 
 #include <algorithm>
 
+#include "arch/sparc/mmu.hh"
 #include "arch/sparc/process.hh"
 #include "arch/sparc/se_workload.hh"
-#include "arch/sparc/tlb.hh"
 #include "arch/sparc/types.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
@@ -669,8 +669,9 @@ FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
     // false for syscall emulation mode regardless of whether the
     // address is real in preceding code. Not sure sure that this is
     // correct, but also not sure if it matters at all.
-    dynamic_cast<TLB *>(tc->getITBPtr())->
-        insert(alignedvaddr, partition_id, context_id, false, entry.pte);
+    static_cast<MMU *>(tc->getMMUPtr())->insertItlbEntry(
+        alignedvaddr, partition_id, context_id,
+        false, entry.pte);
 }
 
 void
@@ -756,8 +757,9 @@ FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
     // false for syscall emulation mode regardless of whether the
     // address is real in preceding code. Not sure sure that this is
     // correct, but also not sure if it matters at all.
-    dynamic_cast<TLB *>(tc->getDTBPtr())->
-        insert(alignedvaddr, partition_id, context_id, false, entry.pte);
+    static_cast<MMU *>(tc->getMMUPtr())->insertDtlbEntry(
+        alignedvaddr, partition_id, context_id,
+        false, entry.pte);
 }
 
 void

diff --git a/src/arch/sparc/mmu.hh b/src/arch/sparc/mmu.hh
index 39f5008e4ee322a241148baf415dff00c012e80c..f784015e214926819a4fedd0cb02b4589c5f0551 100644 (file)
--- a/src/arch/sparc/mmu.hh
+++ b/src/arch/sparc/mmu.hh
@@ -39,6 +39,7 @@
 #define __ARCH_SPARC_MMU_HH__
 
 #include "arch/generic/mmu.hh"
+#include "arch/sparc/tlb.hh"
 
 #include "params/SparcMMU.hh"
 
@@ -50,6 +51,22 @@ class MMU : public BaseMMU
     MMU(const SparcMMUParams &p)
       : BaseMMU(p)
     {}
+
+    void
+    insertItlbEntry(Addr vpn, int partition_id, int context_id, bool real,
+        const PageTableEntry& PTE, int entry=-1)
+    {
+        static_cast<TLB*>(itb)->insert(vpn, partition_id,
+            context_id, real, PTE, entry);
+    }
+
+    void
+    insertDtlbEntry(Addr vpn, int partition_id, int context_id, bool real,
+        const PageTableEntry& PTE, int entry=-1)
+    {
+        static_cast<TLB*>(dtb)->insert(vpn, partition_id,
+            context_id, real, PTE, entry);
+    }
 };
 
 } // namespace SparcISA

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 20f316f21a37259298fd4e3227b7be0973c4e5dd..9dde4ef781a04f8f3455d9094707e5c9564e3b0d 100644 (file)
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -33,6 +33,7 @@
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/interrupts.hh"
+#include "arch/sparc/mmu.hh"
 #include "arch/sparc/registers.hh"
 #include "base/bitfield.hh"
 #include "base/compiler.hh"
@@ -955,7 +956,7 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
     DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
          (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
 
-    TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
+    TLB *itb = static_cast<TLB *>(tc->getMMUPtr()->itb);
 
     switch (asi) {
       case ASI_LSU_CONTROL_REG:
@@ -1151,7 +1152,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
     DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
          (uint32_t)asi, va, data);
 
-    TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
+    TLB *itb = static_cast<TLB *>(tc->getMMUPtr()->itb);
 
     switch (asi) {
       case ASI_LSU_CONTROL_REG:
@@ -1388,7 +1389,7 @@ void
 TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
 {
     uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
-    TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
+    TLB *itb = static_cast<TLB *>(tc->getMMUPtr()->itb);
     ptrs[0] = MakeTsbPtr(Ps0, tag_access,
                 c0_tsb_ps0,
                 c0_config,

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 9291343083dc0927e3c48cf23ee50b8030ae4ab1..4a15b8f7f7cbc9a8401ccf9c31d00d933c780f4a 100644 (file)
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -49,9 +49,7 @@ const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
 
 class TLB : public BaseTLB
 {
-    // These faults need to be able to populate the tlb in SE mode.
-    friend class FastInstructionAccessMMUMiss;
-    friend class FastDataAccessMMUMiss;
+    friend class MMU;
 
     // TLB state
   protected: