if RA = 0 then RT <- EXTS(SI)
else RT <- (RA) + EXTS(SI)
+Special Registers Altered:
+ None
+
# Add Immediate Shifted
D-Form
if RA = 0 then RT <- EXTS(SI || 160)
else RT <- (RA) + EXTS(SI || [0]*16)
+Special Registers Altered:
+ None
+
# Add PC Immediate Shifted
DX-Form
D <- d0||d1||d2
RT <- NIA + EXTS(D || [0]*16)
+Special Registers Altered:
+ None
# Add
RT <- (RA) + (RB)
+Special Registers Altered:
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Subtract From
XO-Form
RT <- ¬(RA) + (RB) + 1
+Special Registers Altered:
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Add Immediate Carrying
D-Form
RT <- (RA) + EXTS(SI)
+Special Registers Altered:
+ CA CA32
+
# Add Immediate Carrying and Record
D-Form
RT <- (RA) + EXTS(SI)
+Special Registers Altered:
+ CR0 CA CA32
+
# Subtract From Immediate Carrying
D-Form
RT <- ¬(RA) + EXTS(SI) + 1
+Special Registers Altered:
+ CA CA32
+
# Add Carrying
XO-Form
RT <- (RA) + (RB)
+Special Registers Altered:
+ CA CA32
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Subtract From Carrying
XO-Form
RT <- ¬(RA) + (RB) + 1
+Special Registers Altered:
+ CA CA32
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Add Extended
XO-Form
RT <- (RA) + (RB) + CA
+Special Registers Altered:
+ CA CA32
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Subtract From Extended
XO-Form
RT <- ¬(RA) + (RB) + CA
+Special Registers Altered:
+ CA CA32
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Add to Minus One Extended
XO-Form
RT <- (RA) + CA - 1
+Special Registers Altered:
+ CA CA32
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Subtract From Minus One Extended
XO-Form
RT <- ¬(RA) + CA - 1
+Special Registers Altered:
+ CA CA32
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Add Extended using alternate carry bit
Z23-Form
if CY=0 then RT <- (RA) + (RB) + OV
+Special Registers Altered:
+ OV OV32 (if CY=0 )
+
# Subtract From Zero Extended
XO-form
RT <- ¬(RA) + CA
+Special Registers Altered:
+ CA CA32
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Add to Zero Extended
XO-form
RT <- (RA) + CA
+Special Registers Altered:
+ CA CA32
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Negate
XO-form
RT <- ¬(RA) + 1
+Special Registers Altered:
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Multiply Low Immediate
D-form
prod[0:127] <- (RA) * EXTS(SI)
RT <- prod[64:127]
+Special Registers Altered:
+ None
+
# Multiply High Word
XO-form
RT[32:63] <- prod[0:31]
RT[0:31] <- undefined
+Special Registers Altered:
+ CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
+
# Multiply Low Word
XO-form
RT <- (RA)[32:63] * (RB)[32:63]
+Special Registers Altered:
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Multiply High Word Unsigned
XO-form
RT[32:63] <- prod[0:31]
RT[0:31] <- undefined
+Special Registers Altered:
+ CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
+
# Divide Word
XO-form
RT[32:63] <- dividend / divisor
RT[0:31] <- undefined
+Special Registers Altered:
+ CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Divide Word Unsigned
XO-form
RT[32:63] <- dividend / divisor
RT[0:31] <- undefined
+Special Registers Altered:
+ CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Divide Word Extended
XO-form
RT[32:63] <- dividend / divisor
RT[0:31] <- undefined
+Special Registers Altered:
+ CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Divide Word Extended Unsigned
XO-form
RT[32:63] <- dividend / divisor
RT[0:31] <- undefined
-# Modulo Signed Word X-form
+Special Registers Altered:
+ CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
+ SO OV OV32 (if OE=1)
+
+# Modulo Signed Word
X-form
RT[32:63] <- dividend % divisor
RT[0:31 ] <- undefined
-# Modulo Unsigned Word X-form
+Special Registers Altered:
+ None
+
+# Modulo Unsigned Word
X-form
RT[32:63] <- dividend % divisor
RT[0:31 ] <- undefined
+Special Registers Altered:
+ None
# Deliver A Random Number
RT <- random(L)
+Special Registers Altered:
+ none
+
# Multiply Low Doubleword
XO-form
prod[0:127] <- (RA) * (RB)
RT <- prod[64:127]
+Special Registers Altered:
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Multiply High Doubleword
XO-form
prod[0:127] <- (RA) * (RB)
RT <- prod[0:63]
+Special Registers Altered:
+ CR0 (if Rc=1)
+
# Multiply High Doubleword Unsigned
XO-form
prod[0:127] <- (RA) * (RB)
RT <- prod[0:63]
+Special Registers Altered:
+ CR0 (if Rc=1)
+
# Multiply-Add High Doubleword VA-form
VA-form
sum[0:127] <- prod + EXTS(RC)
RT <- sum[0:63]
+Special Registers Altered:
+ None
+
# Multiply-Add High Doubleword Unsigned
VA-form
sum[0:127] <- prod + EXTZ(RC)
RT <- sum[0:63]
+Special Registers Altered:
+ None
+
# Multiply-Add Low Doubleword
VA-form
sum[0:127] <- prod + EXTS(RC)
RT <- sum[64:127]
+Special Registers Altered:
+ None
+
# Divide Doubleword
XO-form
divisor[0:63] <- (RB)
RT <- dividend / divisor
+Special Registers Altered:
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Divide Doubleword Unsigned
XO-form
divisor[0:63] <- (RB)
RT <- dividend / divisor
+Special Registers Altered:
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Divide Doubleword Extended
XO-form
divisor[0:63] <- (RB)
RT <- dividend / divisor
+Special Registers Altered:
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Divide Doubleword Extended Unsigned
XO-form
divisor[0:63] <- (RB)
RT <- dividend / divisor
+Special Registers Altered:
+ CR0 (if Rc=1)
+ SO OV OV32 (if OE=1)
+
# Modulo Signed Doubleword
X-form
divisor <- (RB)
RT <- dividend % divisor
+Special Registers Altered:
+ None
+
# Modulo Unsigned Doubleword
X-form
divisor <- (RB)
RT <- dividend % divisor
+Special Registers Altered:
+ None
+
projects / libreriscv.git / commitdiff