arch-mips: Implement GDB XML target description for MIPS

Change-Id: Icff3b2c3e60d5989978de854247232afbb3b0dae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31574
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

diff --git a/ext/gdb-xml/mips.xml b/ext/gdb-xml/mips.xml
new file mode 100644 (file)
index 0000000..23133d7
--- /dev/null
+++ b/ext/gdb-xml/mips.xml
@@ -0,0 +1,94 @@
+<?xml version="1.0"?>
+<!--
+GDB feature descriptor defining the structure of the G packet,
+i.e., the representation of register contents on the wire.
+This file does not model any real variant of 32-bit MIPS in particular;
+it simply reflects BaseGdbRegCache's fields in mips/remote_gdb.hh.
+
+As such, this description is something of an oversimplification
+relative to the XML files in the GDB source, in that it does not
+take into account possible variations in features resulting in
+non-sequential numbering of registers.
+-->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>mips</architecture>
+ <feature name="org.gem5.mips">
+  <reg name="r0" bitsize="32" regnum="0"/>
+  <reg name="r1" bitsize="32"/>
+  <reg name="r2" bitsize="32"/>
+  <reg name="r3" bitsize="32"/>
+  <reg name="r4" bitsize="32"/>
+  <reg name="r5" bitsize="32"/>
+  <reg name="r6" bitsize="32"/>
+  <reg name="r7" bitsize="32"/>
+  <reg name="r8" bitsize="32"/>
+  <reg name="r9" bitsize="32"/>
+  <reg name="r10" bitsize="32"/>
+  <reg name="r11" bitsize="32"/>
+  <reg name="r12" bitsize="32"/>
+  <reg name="r13" bitsize="32"/>
+  <reg name="r14" bitsize="32"/>
+  <reg name="r15" bitsize="32"/>
+  <reg name="r16" bitsize="32"/>
+  <reg name="r17" bitsize="32"/>
+  <reg name="r18" bitsize="32"/>
+  <reg name="r19" bitsize="32"/>
+  <reg name="r20" bitsize="32"/>
+  <reg name="r21" bitsize="32"/>
+  <reg name="r22" bitsize="32"/>
+  <reg name="r23" bitsize="32"/>
+  <reg name="r24" bitsize="32"/>
+  <reg name="r25" bitsize="32"/>
+  <reg name="r26" bitsize="32"/>
+  <reg name="r27" bitsize="32"/>
+  <reg name="r28" bitsize="32"/>
+  <reg name="r29" bitsize="32"/>
+  <reg name="r30" bitsize="32"/>
+  <reg name="r31" bitsize="32"/>
+
+  <reg name="sr" bitsize="32"/>
+  <reg name="lo" bitsize="32"/>
+  <reg name="hi" bitsize="32"/>
+  <reg name="badvaddr" bitsize="32"/>
+  <reg name="cause" bitsize="32"/>
+  <reg name="pc" bitsize="32"/>
+
+  <reg name="f0" bitsize="32"/>
+  <reg name="f1" bitsize="32"/>
+  <reg name="f2" bitsize="32"/>
+  <reg name="f3" bitsize="32"/>
+  <reg name="f4" bitsize="32"/>
+  <reg name="f5" bitsize="32"/>
+  <reg name="f6" bitsize="32"/>
+  <reg name="f7" bitsize="32"/>
+  <reg name="f8" bitsize="32"/>
+  <reg name="f9" bitsize="32"/>
+  <reg name="f10" bitsize="32"/>
+  <reg name="f11" bitsize="32"/>
+  <reg name="f12" bitsize="32"/>
+  <reg name="f13" bitsize="32"/>
+  <reg name="f14" bitsize="32"/>
+  <reg name="f15" bitsize="32"/>
+  <reg name="f16" bitsize="32"/>
+  <reg name="f17" bitsize="32"/>
+  <reg name="f18" bitsize="32"/>
+  <reg name="f19" bitsize="32"/>
+  <reg name="f20" bitsize="32"/>
+  <reg name="f21" bitsize="32"/>
+  <reg name="f22" bitsize="32"/>
+  <reg name="f23" bitsize="32"/>
+  <reg name="f24" bitsize="32"/>
+  <reg name="f25" bitsize="32"/>
+  <reg name="f26" bitsize="32"/>
+  <reg name="f27" bitsize="32"/>
+  <reg name="f28" bitsize="32"/>
+  <reg name="f29" bitsize="32"/>
+  <reg name="f30" bitsize="32"/>
+  <reg name="f31" bitsize="32"/>
+
+  <reg name="fsr" bitsize="32"/>
+  <reg name="fir" bitsize="32"/>
+ </feature>
+</target>

diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index cac589f8ecc5bfd9b4bb0609898099f628ff6893..d8771de8ce57009a0e66a1d43ee644a7e4a51b85 100644 (file)
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -1,6 +1,7 @@
 # -*- mode:python -*-
 
 # Copyright (c) 2004-2006 The Regents of The University of Michigan
+# Copyright (c) 2020 LabWare
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -50,3 +51,5 @@ if env['TARGET_ISA'] == 'mips':
     DebugFlag('MipsPRA')
 
     ISADesc('isa/main.isa')
+
+    GdbXml('mips.xml', 'gdb_xml_mips')

diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index 48138eec785549bb342a912b61ebf8e2e9f45f97..bd9a40f68646987f4c2b6ed39fe938ff97247489 100644 (file)
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 LabWare
+ * Copyright 2015-2020 LabWare
  * Copyright 2014 Google, Inc.
  * Copyright (c) 2010 ARM Limited
  * All rights reserved
@@ -136,6 +136,7 @@
 #include <string>
 
 #include "arch/mips/decoder.hh"
+#include "blobs/gdb_xml_mips.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
 #include "debug/GDBMisc.hh"
@@ -201,3 +202,20 @@ RemoteGDB::gdbRegs()
 {
     return &regCache;
 }
+
+bool
+RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
+{
+#define GDB_XML(x, s) \
+        { x, std::string(reinterpret_cast<const char *>(Blobs::s), \
+        Blobs::s ## _len) }
+    static const std::map<std::string, std::string> annexMap {
+        GDB_XML("target.xml", gdb_xml_mips),
+    };
+#undef GDB_XML
+    auto it = annexMap.find(annex);
+    if (it == annexMap.end())
+        return false;
+    output = it->second;
+    return true;
+}

diff --git a/src/arch/mips/remote_gdb.hh b/src/arch/mips/remote_gdb.hh
index 407a5574f599ec4e6f36b248984443a089421f5d..2119d8e1d6d1479f6103ef94c4c1af74b72465c6 100644 (file)
--- a/src/arch/mips/remote_gdb.hh
+++ b/src/arch/mips/remote_gdb.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 LabWare
+ * Copyright 2015-2020 LabWare
  * Copyright 2014 Google, Inc.
  * Copyright (c) 2007 The Regents of The University of Michigan
  * All rights reserved.
@@ -79,6 +79,12 @@ class RemoteGDB : public BaseRemoteGDB
   public:
     RemoteGDB(System *_system, ThreadContext *tc, int _port);
     BaseGdbRegCache *gdbRegs();
+    std::vector<std::string>
+    availableFeatures() const
+    {
+        return {"qXfer:features:read+"};
+    };
+    bool getXferFeaturesRead(const std::string &annex, std::string &output);
 };
 
 } // namespace MipsISA