Uart fix.

dev/uart8250.cc:
    Fixed implementation of "transmit interrupt clear".

--HG--
extra : convert_revision : cb69d61413ea799d5d3825fe2f0891dd72995561

diff --git a/dev/uart8250.cc b/dev/uart8250.cc
index bbde147692e858500eceb01af9635c1fa7ae1964..2ad020462b9c76d0365b5fcbbc14d0091d59080b 100644 (file)
--- a/dev/uart8250.cc
+++ b/dev/uart8250.cc
@@ -147,13 +147,15 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
         case 0x2: // Intr Identification Register (IIR)
             DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
 
-            //Tx interrupts are cleared on IIR reads
-            status &= ~TX_INT;
-
-            if (status & RX_INT)
+            if (status & RX_INT) /* Rx data interrupt has a higher priority */
                 *(uint8_t*)data = IIR_RXID;
+            else if (status & TX_INT)
+                *(uint8_t*)data = IIR_TXID;
             else
                 *(uint8_t*)data = IIR_NOPEND;
+
+            //Tx interrupts are cleared on IIR reads
+            status &= ~TX_INT;
             break;
         case 0x3: // Line Control Register (LCR)
             *(uint8_t*)data = LCR;