add checks for RVC registers to sv template

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 3ff09e8061842ca190d7af2aa6f3034db3fb1d53..83c9b441cdd9d95b6d8ffe5acaa33c49ca98fb1a 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -35,6 +35,18 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 #endif
 #ifdef USING_REG_RS2
  insn.sv_check_reg(true, s_insn.rs3()) |
+#endif
+#ifdef USING_REG_RVC_RS1
+ insn.sv_check_reg(true, s_insn.rvc_rs1()) |
+#endif
+#ifdef USING_REG_RVC_RS1S
+ insn.sv_check_reg(true, s_insn.rvc_rs1s()) |
+#endif
+#ifdef USING_REG_RVC_RS2
+ insn.sv_check_reg(true, s_insn.rvc_rs2()) |
+#endif
+#ifdef USING_REG_RVC_RS2S
+ insn.sv_check_reg(true, s_insn.rvc_rs2s()) |
 #endif
   // fp ops, RD, RS1, RS2, RS3 (use sv_fp_tb)
 #ifdef USING_REG_FRD
@@ -48,6 +60,12 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 #endif
 #ifdef USING_REG_FRS2
   insn.sv_check_reg(false, s_insn.rs3()) |
+#endif
+#ifdef USING_REG_RVC_FRS2
+  insn.sv_check_reg(false, s_insn.rvc_rs2()) |
+#endif
+#ifdef USING_REG_RVC_FRS2S
+  insn.sv_check_reg(false, s_insn.rvc_rs2s()) |
 #endif
   false; // save a few cycles by |ing the checks together.