import argparse
-from litex.gen import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import arty
import argparse
-from litex.gen import *
+from migen import *
+
from litex.boards.platforms import de0nano
from litex.soc.integration.soc_sdram import *
import argparse
-from litex.gen import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import kc705
import argparse
from fractions import Fraction
-from litex.gen import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
from litex.boards.platforms import minispartan6
from litex.soc.integration.soc_sdram import *
import argparse
-from litex.gen import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import nexys4ddr
import argparse
-from litex.gen import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import nexys_video
import argparse
import importlib
-from litex.gen import *
+from migen import *
+from migen.genlib.io import CRG
+
from litex.boards.platforms import sim
-from litex.gen.genlib.io import CRG
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
import argparse
import importlib
-from litex.gen import *
-from litex.gen.genlib.io import CRG
+from migen import *
+from migen.genlib.io import CRG
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
-from litex.gen.fhdl.module import Module
-from litex.gen.fhdl.specials import Instance
-from litex.gen.genlib.io import DifferentialInput, DifferentialOutput
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
+from migen.genlib.io import DifferentialInput, DifferentialOutput
class AlteraDifferentialInputImpl(Module):
import os
import subprocess
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import Pins, IOStandard, Misc
from litex.build import tools
import os
-from litex.gen.fhdl.structure import Signal
-from litex.gen.genlib.record import Record
-from litex.gen.genlib.io import CRG
-from litex.gen.fhdl import verilog
+from migen.fhdl.structure import Signal
+from migen.genlib.record import Record
+from migen.genlib.io import CRG
+from migen.fhdl import verilog
+
from litex.build import tools
-from litex.gen.fhdl.module import Module
-from litex.gen.fhdl.specials import Instance
-from litex.gen.genlib.io import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
+from migen.genlib.io import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
class DiamondAsyncResetSynchronizerImpl(Module):
import subprocess
import shutil
-from litex.gen.fhdl.structure import _Fragment
-from litex.gen.fhdl.verilog import DummyAttrTranslate
+from migen.fhdl.structure import _Fragment
+from migen.fhdl.verilog import DummyAttrTranslate
from litex.build.generic_platform import *
from litex.build import tools
import sys
import subprocess
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools
-from litex.gen.fhdl.structure import Signal
-from litex.gen.genlib.record import Record
+from migen.fhdl.structure import Signal
+from migen.genlib.record import Record
+
from litex.build.generic_platform import GenericPlatform
from litex.build.sim import common, verilator
import os
import subprocess
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl.structure import _Fragment
+
from litex.build import tools
from litex.build.generic_platform import *
except ImportError:
_have_colorama = False
-from litex.gen.fhdl.structure import *
-from litex.gen.fhdl.specials import Instance
-from litex.gen.fhdl.module import Module
-from litex.gen.genlib.cdc import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
-from litex.gen.genlib.io import *
+from migen.fhdl.structure import *
+from migen.fhdl.specials import Instance
+from migen.fhdl.module import Module
+from migen.genlib.cdc import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.io import *
from litex.build import tools
import subprocess
import sys
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl.structure import _Fragment
+
from litex.build.generic_platform import *
from litex.build import tools
from litex.build.xilinx import common
import subprocess
import sys
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl.structure import _Fragment
+
from litex.build.generic_platform import *
from litex.build import tools
from litex.build.xilinx import common
-from litex.gen.fhdl.structure import *
-from litex.gen.fhdl.module import *
-from litex.gen.fhdl.specials import *
-from litex.gen.fhdl.bitcontainer import *
-from litex.gen.fhdl.decorators import *
-from litex.gen.fhdl.simplify import *
-
from litex.gen.sim import *
-
-from litex.gen.genlib.record import *
-from litex.gen.genlib.fsm import *
from operator import itemgetter
import collections
-from litex.gen.fhdl.structure import *
-from litex.gen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
-from litex.gen.fhdl.tools import *
-from litex.gen.fhdl.namer import build_namespace
-from litex.gen.fhdl.conv_output import ConvOutput
+from migen.fhdl.structure import *
+from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
+from migen.fhdl.tools import *
+from migen.fhdl.namer import build_namespace
+from migen.fhdl.conv_output import ConvOutput
_reserved_keywords = {
-from litex.gen.sim.core import Simulator, run_simulation, passive
+from migen.sim.core import Simulator, run_simulation, passive
import inspect
from functools import wraps
-from litex.gen.fhdl.structure import *
-from litex.gen.fhdl.structure import (_Value, _Statement,
+from migen.fhdl.structure import *
+from migen.fhdl.structure import (_Value, _Statement,
_Operator, _Slice, _ArrayProxy,
_Assign, _Fragment)
-from litex.gen.fhdl.bitcontainer import value_bits_sign
-from litex.gen.fhdl.tools import (list_targets, list_signals,
+from migen.fhdl.bitcontainer import value_bits_sign
+from migen.fhdl.tools import (list_targets, list_signals,
insert_resets, lower_specials)
-from litex.gen.fhdl.simplify import MemoryToArray
-from litex.gen.fhdl.specials import _MemoryLocation
-from litex.gen.fhdl.module import Module
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
-from litex.gen.sim.vcd import VCDWriter, DummyVCDWriter
+from migen.fhdl.simplify import MemoryToArray
+from migen.fhdl.specials import _MemoryLocation
+from migen.fhdl.module import Module
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.sim.vcd import VCDWriter, DummyVCDWriter
class ClockState:
from collections import OrderedDict
import shutil
-from litex.gen.fhdl.namer import build_namespace
+from migen.fhdl.namer import build_namespace
def vcd_codes():
scheme called TMDS).
"""
-from litex.gen import *
+from migen import *
def disparity(word, nbits):
from math import atan, atanh, log, sqrt, pi
-from litex.gen import *
+from migen import *
class TwoQuadrantCordic(Module):
import os
-from litex.gen import *
+from migen import *
from litex.soc.interconnect import wishbone
import os
-from litex.gen import *
+from migen import *
from litex.soc.interconnect import wishbone
import os
-from litex.gen import *
+from migen import *
from litex.soc.interconnect import wishbone
# Copyright 2014-2015 Robert Jordens <jordens@gmail.com>
-from litex.gen import *
+from migen import *
+
from litex.soc.interconnect.csr import *
-from litex.gen import *
-from litex.gen.genlib.cdc import MultiReg, GrayCounter
-from litex.gen.genlib.cdc import GrayDecoder
+from migen import *
+from migen.genlib.cdc import MultiReg, GrayCounter
+from migen.genlib.cdc import GrayDecoder
from litex.soc.interconnect.csr import *
-from litex.gen import *
-from litex.gen.genlib.cdc import MultiReg
+from migen import *
+from migen.genlib.cdc import MultiReg
from litex.soc.interconnect.csr import *
-from litex.gen import *
+from migen import *
class Identifier(Module):
-from litex.gen import *
-from litex.gen.genlib.fsm import FSM, NextState
+from migen import *
+from migen.genlib.fsm import FSM, NextState
from litex.soc.interconnect import wishbone
from itertools import product
-from litex.gen import *
+from migen import *
+
from litex.soc.interconnect.csr import *
-from litex.gen import *
-from litex.gen.genlib.misc import timeline
+from migen import *
+from migen.genlib.misc import timeline
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus
-from litex.gen import *
+from migen import *
from litex.soc.interconnect.csr import *
from litex.soc.interconnect.csr_eventmanager import *
-from litex.gen import *
-from litex.gen.genlib.record import Record
-from litex.gen.genlib.cdc import MultiReg
+from migen import *
+from migen.genlib.record import Record
+from migen.genlib.cdc import MultiReg
from litex.soc.interconnect.csr import *
from litex.soc.interconnect.csr_eventmanager import *
# Copyright 2014-2015 Robert Jordens <jordens@gmail.com>
-from litex.gen import *
+from migen import *
+
from litex.soc.interconnect.csr import *
import os
-from litex.gen import *
+from migen import *
from litex.soc.interconnect.csr import CSRStatus
-from litex.gen import log2_int
+from migen import log2_int
def get_sdram_phy_header(sdram_phy_settings):
from operator import itemgetter
-from litex.gen import *
+from migen import *
from litex.soc.cores import identifier, timer, uart
from litex.soc.cores.cpu import lm32, mor1kx, picorv32
-from litex.gen import *
-from litex.gen.genlib.record import *
+from migen import *
+from migen.genlib.record import *
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import AutoCSR
# Remove this workaround when fixed by Xilinx.
from litex.build.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
- from litex.gen.fhdl.simplify import FullMemoryWE
+ from migen.fhdl.simplify import FullMemoryWE
self.submodules.l2_cache = FullMemoryWE()(l2_cache)
else:
self.submodules.l2_cache = l2_cache
import math
-from litex.gen import *
-from litex.gen.genlib.record import *
+from migen import *
+from migen.genlib.record import *
+
from litex.soc.interconnect import csr_bus
# Layout of AXI4 Lite Bus
)
-from litex.gen.sim import run_simulation
+from migen.sim import run_simulation
from litex.soc.interconnect import csr, csr_bus
def test_axilite2csr():
CSR and memory attributes and return their list.
"""
-from litex.gen import *
-from litex.gen.util.misc import xdir
-from litex.gen.fhdl.tracer import get_obj_var_name
+from migen import *
+from migen.util.misc import xdir
+from migen.fhdl.tracer import get_obj_var_name
class _CSRBase(DUID):
the configuration and status registers of cores from software.
"""
-from litex.gen import *
-from litex.gen.genlib.record import *
-from litex.gen.genlib.misc import chooser
-from litex.gen.util.misc import xdir
+from migen import *
+from migen.genlib.record import *
+from migen.genlib.misc import chooser
+from migen.util.misc import xdir
from litex.soc.interconnect import csr
from litex.soc.interconnect.csr import CSRStorage
from functools import reduce
from operator import or_
-from litex.gen import *
-from litex.gen.util.misc import xdir
+from migen import *
+from migen.util.misc import xdir
from litex.soc.interconnect.csr import *
-from litex.gen import *
-from litex.gen.genlib.record import *
-from litex.gen.genlib import fifo
+from migen import *
+from migen.genlib.record import *
+from migen.genlib import fifo
(DIR_SINK, DIR_SOURCE) = range(2)
-def _make_m2s(layout, reset_less=False):
+def _make_m2s(layout):
r = []
for f in layout:
if isinstance(f[1], (int, tuple)):
- r.append((f[0], f[1], DIR_M_TO_S, reset_less))
+ r.append((f[0], f[1], DIR_M_TO_S))
else:
- r.append((f[0], _make_m2s(f[1], reset_less)))
+ r.append((f[0], _make_m2s(f[1])))
return r
("ready", 1, DIR_S_TO_M),
("first", 1, DIR_M_TO_S),
("last", 1, DIR_M_TO_S),
- ("payload", _make_m2s(self.payload_layout, True)),
- ("param", _make_m2s(self.param_layout, True))
+ ("payload", _make_m2s(self.payload_layout)),
+ ("param", _make_m2s(self.param_layout))
]
return full_layout
# XXX
from copy import copy
-from litex.gen.util.misc import xdir
+from migen.util.misc import xdir
def _rawbits_layout(l):
if isinstance(l, int):
-from litex.gen import *
-from litex.gen.genlib.roundrobin import *
-from litex.gen.genlib.record import *
-from litex.gen.genlib.fsm import FSM, NextState
+from migen import *
+from migen.genlib.roundrobin import *
+from migen.genlib.record import *
+from migen.genlib.fsm import FSM, NextState
from litex.soc.interconnect import stream
import math
from copy import deepcopy
-from litex.gen import *
+from migen import *
+
from litex.soc.interconnect import stream
# TODO: clean up code below
from functools import reduce
from operator import or_
-from litex.gen import *
-from litex.gen.genlib import roundrobin
-from litex.gen.genlib.record import *
-from litex.gen.genlib.misc import split, displacer, chooser
-from litex.gen.genlib.fsm import FSM, NextState
+from migen import *
+from migen.genlib import roundrobin
+from migen.genlib.record import *
+from migen.genlib.misc import split, displacer, chooser
+from migen.genlib.fsm import FSM, NextState
from litex.soc.interconnect import csr
-from litex.gen import *
-from litex.gen.genlib.misc import timeline
+from migen import *
+from migen.genlib.misc import timeline
from litex.soc.interconnect import csr_bus, wishbone
-from litex.gen import *
+from migen import *
-from litex.gen.genlib.misc import chooser, WaitTimer
-from litex.gen.genlib.record import Record
-from litex.gen.genlib.fsm import FSM, NextState
+from migen.genlib.misc import chooser, WaitTimer
+from migen.genlib.record import Record
+from migen.genlib.fsm import FSM, NextState
from litex.soc.interconnect import wishbone
from litex.soc.interconnect import stream
import unittest
import random
-from litex.gen import *
-from litex.gen.genlib.misc import BitSlip
+from migen import *
+from migen.genlib.misc import BitSlip
class BitSlipModel:
import random
from collections import namedtuple
-from litex.gen import *
+from migen import *
from litex.soc.cores import code_8b10b
import unittest
import random
-from litex.gen import *
-from litex.gen.genlib.cdc import Gearbox
+from migen import *
+from migen.genlib.cdc import Gearbox
# TODO:
# connect two gearbox together:
import unittest
import os
-from litex.gen import *
+from migen import *
from litex.soc.integration.builder import *
projects / litex.git / commitdiff