help="Show the release notes")
# Options for configuring the base simulator
-add_option('-d', "--outdir", metavar="DIR", default=".",
+add_option('-d', "--outdir", metavar="DIR", default="m5out",
help="Set the output directory to DIR [Default: %default]")
add_option('-r', "--redirect-stdout", action="store_true", default=False,
help="Redirect stdout (& stderr, without -e) to file")
# Statistics options
set_group("Statistics Options")
-add_option("--stats-file", metavar="FILE", default="m5stats.txt",
+add_option("--stats-file", metavar="FILE", default="stats.txt",
help="Sets the output file for statistics [Default: %default]")
+# Configuration Options
+set_group("Configuration Options")
+add_option("--dump-config", metavar="FILE", default="config.ini",
+ help="Dump configuration output file [Default: %default]")
+
# Debugging options
set_group("Debugging Options")
add_option("--debug-break", metavar="TIME[,TIME]", action='append', split=',',
root.unproxy_all()
- ini_file = file(os.path.join(options.outdir, 'config.ini'), 'w')
- root.print_ini(ini_file)
- ini_file.close() # close config.ini
+ if options.dump_config:
+ ini_file = file(os.path.join(options.outdir, options.dump_config), 'w')
+ root.print_ini(ini_file)
+ ini_file.close()
# Initialize the global statistics
internal.stats.initSimStats()
if os.path.exists(t.abspath):
Execute(Delete(t.abspath))
# Run diff on output & ref directories to find differences.
- # Exclude m5stats.txt since we will use diff-out on that.
+ # Exclude the stats file since we will use diff-out on that.
Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' +
'-I "^command line:" ' + # for stdout file
'-I "^M5 compiled " ' + # for stderr file
'-I "^Simulation complete at" ' + # for stderr file
'-I "^Listening for" ' + # for stderr file
'-I "listening for remote gdb" ' + # for stderr file
- '--exclude=m5stats.txt --exclude=SCCS ' +
+ '--exclude=stats.txt --exclude=SCCS ' +
'--exclude=${TARGETS[0].file} ' +
'> ${TARGETS[0]}', target=target, source=source), None)
print "===== Output differences ====="
print contents(target[0])
- # Run diff-out on m5stats.txt file
+ # Run diff-out on stats.txt file
status = Execute(env.subst('$DIFFOUT $SOURCES > ${TARGETS[1]}',
target=target, source=source),
strfunction=None)
inputs and are ignored.
'''
# - reference files always needed
-needed_files = set(['stdout', 'stderr', 'm5stats.txt', 'config.ini'])
+needed_files = set(['simout', 'simerr', 'stats.txt', 'config.ini'])
# - source files we always want to ignore
known_ignores = set(['status', 'outdiff', 'statsdiff'])
def update_test(target, source, env):
"""Update reference test outputs.
- Target is phony. First two sources are the ref & new m5stats.txt
+ Target is phony. First two sources are the ref & new stats.txt file
files, respectively. We actually copy everything in the
respective directories except the status & diff output files.
def tgt(f):
return os.path.join(tgt_dir, f)
- ref_stats = os.path.join(ref_dir, 'm5stats.txt')
- new_stats = tgt('m5stats.txt')
+ ref_stats = os.path.join(ref_dir, 'stats.txt')
+ new_stats = tgt('stats.txt')
status_file = tgt('status')
# Base command for running test. We mess around with indirectly
# referring to files via SOURCES and TARGETS so that scons can
# mess with paths all it wants to and we still get the right
# files.
- cmd = '${SOURCES[0]} -d $TARGET.dir'
- cmd += ' -re --stdout-file stdout --stderr-file stderr'
- cmd += ' ${SOURCES[1]} %s' % tgt_dir
+ cmd = '${SOURCES[0]} -d $TARGET.dir -re ${SOURCES[1]} %s' % tgt_dir
# Prefix test run with batch job submission command if appropriate.
# Batch command also supports timeout arg (in seconds, not minutes).
if env['BATCH']:
cmd = '%s -t %d %s' % (env['BATCH_CMD'], timeout, cmd)
- env.Command([tgt('stdout'), tgt('stderr'), new_stats],
+ env.Command([tgt('simout'), tgt('simerr'), new_stats],
[env.M5Binary, 'run.py'], cmd)
# order of targets is important... see check_test
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 65718859 # Number of BTB hits
-global.BPredUnit.BTBLookups 73181368 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted
-global.BPredUnit.lookups 76039018 # Number of BP lookups
-global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target.
-host_inst_rate 193677 # Simulator instruction rate (inst/s)
-host_mem_usage 202220 # Number of bytes of host memory used
-host_seconds 2920.07 # Real time elapsed on the host
-host_tick_rate 57217081 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 565552443 # Number of instructions simulated
-sim_seconds 0.167078 # Number of seconds simulated
-sim_ticks 167078146500 # Number of ticks simulated
-system.cpu.commit.COM:branches 62547159 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 322711249
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 108088757 3349.40%
- 1 100475751 3113.49%
- 2 37367184 1157.91%
- 3 9733028 301.60%
- 4 10676883 330.85%
- 5 22147835 686.31%
- 6 13251874 410.64%
- 7 3269687 101.32%
- 8 17700250 548.49%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 601856963 # Number of instructions committed
-system.cpu.commit.COM:loads 115049510 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 154862033 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 565552443 # Number of Instructions Simulated
-system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
-system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 37121636 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 76416692881 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.059052 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2329685 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1992407 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 149415339 # number of overall hits
-system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 3182768 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 468828 # number of replacements
-system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use
-system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 334123 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 163077390 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 163013880 # DTB hits
-system.cpu.dtb.misses 63510 # DTB misses
-system.cpu.dtb.read_accesses 122284109 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 122260496 # DTB read hits
-system.cpu.dtb.read_misses 23613 # DTB read misses
-system.cpu.dtb.write_accesses 40793281 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 40753384 # DTB write hits
-system.cpu.dtb.write_misses 39897 # DTB write misses
-system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched
-system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 332581112
-system.cpu.fetch.rateDist.min_value 0
- 0 201466223 6057.66%
- 1 10360747 311.53%
- 2 15882081 477.54%
- 3 14599006 438.96%
- 4 12362950 371.73%
- 5 14822134 445.67%
- 6 6008311 180.66%
- 7 3307530 99.45%
- 8 53772130 1616.81%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency
-system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 66013237 # number of overall hits
-system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1169 # number of overall misses
-system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 34 # number of replacements
-system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use
-system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 67316859 # Number of branches executed
-system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate
-system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 41189464 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value
-system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 395375802 # num instructions producing a value
-system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle
-system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 14447 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 0 0.00% # Type of FU issued
- IntAlu 438834840 72.45% # Type of FU issued
- IntMult 6546 0.00% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 29 0.00% # Type of FU issued
- FloatCmp 5 0.00% # Type of FU issued
- FloatCvt 5 0.00% # Type of FU issued
- FloatMult 4 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 124855453 20.61% # Type of FU issued
- MemWrite 42021230 6.94% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 5390831 74.54% # attempts to use FU when none available
- IntMult 67 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 1490139 20.60% # attempts to use FU when none available
- MemWrite 351286 4.86% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 332581112
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 92203773 2772.37%
- 1 67051353 2016.09%
- 2 80133780 2409.45%
- 3 36043478 1083.75%
- 4 30084945 904.59%
- 5 14579095 438.36%
- 6 10850493 326.25%
- 7 1143008 34.37%
- 8 491187 14.77%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate
-system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 66014446 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 66014406 # ITB hits
-system.cpu.itb.misses 40 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 8792814000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 256647 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34136.391255 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31030.684622 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 2752861000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 80643 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2502407500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs 5083.333333 # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 78 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 181383 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 292443 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 85262 # number of replacements
-system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 63236 # number of writebacks
-system.cpu.numCycles 334156294 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed
-system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:25:12
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 65718859 # Number of BTB hits
+global.BPredUnit.BTBLookups 73181368 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted
+global.BPredUnit.lookups 76039018 # Number of BP lookups
+global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target.
+host_inst_rate 193677 # Simulator instruction rate (inst/s)
+host_mem_usage 202220 # Number of bytes of host memory used
+host_seconds 2920.07 # Real time elapsed on the host
+host_tick_rate 57217081 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 565552443 # Number of instructions simulated
+sim_seconds 0.167078 # Number of seconds simulated
+sim_ticks 167078146500 # Number of ticks simulated
+system.cpu.commit.COM:branches 62547159 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 322711249
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 108088757 3349.40%
+ 1 100475751 3113.49%
+ 2 37367184 1157.91%
+ 3 9733028 301.60%
+ 4 10676883 330.85%
+ 5 22147835 686.31%
+ 6 13251874 410.64%
+ 7 3269687 101.32%
+ 8 17700250 548.49%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 601856963 # Number of instructions committed
+system.cpu.commit.COM:loads 115049510 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 154862033 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 565552443 # Number of Instructions Simulated
+system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
+system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 37121636 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 76416692881 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.059052 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2329685 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1992407 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 149415339 # number of overall hits
+system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 3182768 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 468828 # number of replacements
+system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use
+system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 334123 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 163077390 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 163013880 # DTB hits
+system.cpu.dtb.misses 63510 # DTB misses
+system.cpu.dtb.read_accesses 122284109 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 122260496 # DTB read hits
+system.cpu.dtb.read_misses 23613 # DTB read misses
+system.cpu.dtb.write_accesses 40793281 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 40753384 # DTB write hits
+system.cpu.dtb.write_misses 39897 # DTB write misses
+system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched
+system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 332581112
+system.cpu.fetch.rateDist.min_value 0
+ 0 201466223 6057.66%
+ 1 10360747 311.53%
+ 2 15882081 477.54%
+ 3 14599006 438.96%
+ 4 12362950 371.73%
+ 5 14822134 445.67%
+ 6 6008311 180.66%
+ 7 3307530 99.45%
+ 8 53772130 1616.81%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency
+system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 66013237 # number of overall hits
+system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1169 # number of overall misses
+system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 34 # number of replacements
+system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use
+system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 67316859 # Number of branches executed
+system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate
+system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 41189464 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value
+system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 395375802 # num instructions producing a value
+system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle
+system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 14447 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 0 0.00% # Type of FU issued
+ IntAlu 438834840 72.45% # Type of FU issued
+ IntMult 6546 0.00% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 29 0.00% # Type of FU issued
+ FloatCmp 5 0.00% # Type of FU issued
+ FloatCvt 5 0.00% # Type of FU issued
+ FloatMult 4 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 124855453 20.61% # Type of FU issued
+ MemWrite 42021230 6.94% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 5390831 74.54% # attempts to use FU when none available
+ IntMult 67 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 1490139 20.60% # attempts to use FU when none available
+ MemWrite 351286 4.86% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 332581112
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 92203773 2772.37%
+ 1 67051353 2016.09%
+ 2 80133780 2409.45%
+ 3 36043478 1083.75%
+ 4 30084945 904.59%
+ 5 14579095 438.36%
+ 6 10850493 326.25%
+ 7 1143008 34.37%
+ 8 491187 14.77%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate
+system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 66014446 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 66014406 # ITB hits
+system.cpu.itb.misses 40 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 8792814000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 256647 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34136.391255 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31030.684622 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 2752861000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 80643 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2502407500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs 5083.333333 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 78 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 181383 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 292443 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 85262 # number of replacements
+system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 63236 # number of writebacks
+system.cpu.numCycles 334156294 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed
+system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:25:12
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Duplicating 262144 bytes
-Duplicating 524288 bytes
-Input data 1048576 bytes in length
-Compressing Input Data, level 1
-Compressed data 108074 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 3
-Compressed data 97831 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 5
-Compressed data 83382 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 7
-Compressed data 76606 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 73189 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 3417919 # Simulator instruction rate (inst/s)
-host_mem_usage 193752 # Number of bytes of host memory used
-host_seconds 176.09 # Real time elapsed on the host
-host_tick_rate 1708971531 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 601856964 # Number of instructions simulated
-sim_seconds 0.300931 # Number of seconds simulated
-sim_ticks 300930958000 # Number of ticks simulated
-system.cpu.dtb.accesses 153970296 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 153965363 # DTB hits
-system.cpu.dtb.misses 4933 # DTB misses
-system.cpu.dtb.read_accesses 114516673 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 114514042 # DTB read hits
-system.cpu.dtb.read_misses 2631 # DTB read misses
-system.cpu.dtb.write_accesses 39453623 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 39451321 # DTB write hits
-system.cpu.dtb.write_misses 2302 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 601861917 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 601861897 # ITB hits
-system.cpu.itb.misses 20 # ITB misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 601861917 # number of cpu cycles simulated
-system.cpu.num_insts 601856964 # Number of instructions executed
-system.cpu.num_refs 154866966 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:47
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 3417919 # Simulator instruction rate (inst/s)
+host_mem_usage 193752 # Number of bytes of host memory used
+host_seconds 176.09 # Real time elapsed on the host
+host_tick_rate 1708971531 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 601856964 # Number of instructions simulated
+sim_seconds 0.300931 # Number of seconds simulated
+sim_ticks 300930958000 # Number of ticks simulated
+system.cpu.dtb.accesses 153970296 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 153965363 # DTB hits
+system.cpu.dtb.misses 4933 # DTB misses
+system.cpu.dtb.read_accesses 114516673 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 114514042 # DTB read hits
+system.cpu.dtb.read_misses 2631 # DTB read misses
+system.cpu.dtb.write_accesses 39453623 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 39451321 # DTB write hits
+system.cpu.dtb.write_misses 2302 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 601861917 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 601861897 # ITB hits
+system.cpu.itb.misses 20 # ITB misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 601861917 # number of cpu cycles simulated
+system.cpu.num_insts 601856964 # Number of instructions executed
+system.cpu.num_refs 154866966 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:47
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Duplicating 262144 bytes
-Duplicating 524288 bytes
-Input data 1048576 bytes in length
-Compressing Input Data, level 1
-Compressed data 108074 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 3
-Compressed data 97831 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 5
-Compressed data 83382 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 7
-Compressed data 76606 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 73189 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1797646 # Simulator instruction rate (inst/s)
-host_mem_usage 201208 # Number of bytes of host memory used
-host_seconds 334.80 # Real time elapsed on the host
-host_tick_rate 2323765799 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 601856964 # Number of instructions simulated
-sim_seconds 0.778004 # Number of seconds simulated
-sim_ticks 778003833000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 153435240 # number of overall hits
-system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 530123 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 451299 # number of replacements
-system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use
-system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 325723 # number of writebacks
-system.cpu.dtb.accesses 153970296 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 153965363 # DTB hits
-system.cpu.dtb.misses 4933 # DTB misses
-system.cpu.dtb.read_accesses 114516673 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 114514042 # DTB read hits
-system.cpu.dtb.read_misses 2631 # DTB read misses
-system.cpu.dtb.write_accesses 39453623 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 39451321 # DTB write hits
-system.cpu.dtb.write_misses 2302 # DTB write misses
-system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
-system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 601861103 # number of overall hits
-system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
-system.cpu.icache.overall_misses 795 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 24 # number of replacements
-system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use
-system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 601861918 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 601861898 # ITB hits
-system.cpu.itb.misses 20 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 167236 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 288954 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 84513 # number of replacements
-system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 63194 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1556007666 # number of cpu cycles simulated
-system.cpu.num_insts 601856964 # Number of instructions executed
-system.cpu.num_refs 154866966 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1797646 # Simulator instruction rate (inst/s)
+host_mem_usage 201208 # Number of bytes of host memory used
+host_seconds 334.80 # Real time elapsed on the host
+host_tick_rate 2323765799 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 601856964 # Number of instructions simulated
+sim_seconds 0.778004 # Number of seconds simulated
+sim_ticks 778003833000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 153435240 # number of overall hits
+system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 530123 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 451299 # number of replacements
+system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use
+system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 325723 # number of writebacks
+system.cpu.dtb.accesses 153970296 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 153965363 # DTB hits
+system.cpu.dtb.misses 4933 # DTB misses
+system.cpu.dtb.read_accesses 114516673 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 114514042 # DTB read hits
+system.cpu.dtb.read_misses 2631 # DTB read misses
+system.cpu.dtb.write_accesses 39453623 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 39451321 # DTB write hits
+system.cpu.dtb.write_misses 2302 # DTB write misses
+system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
+system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 601861103 # number of overall hits
+system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
+system.cpu.icache.overall_misses 795 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 24 # number of replacements
+system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use
+system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 601861918 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 601861898 # ITB hits
+system.cpu.itb.misses 20 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 167236 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 288954 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 84513 # number of replacements
+system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 63194 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1556007666 # number of cpu cycles simulated
+system.cpu.num_insts 601856964 # Number of instructions executed
+system.cpu.num_refs 154866966 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:45
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Duplicating 262144 bytes
-Duplicating 524288 bytes
-Input data 1048576 bytes in length
-Compressing Input Data, level 1
-Compressed data 108074 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 3
-Compressed data 97831 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 5
-Compressed data 83382 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 7
-Compressed data 76606 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 73189 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 182414509 # Number of BTB hits
-global.BPredUnit.BTBLookups 203429504 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted
-global.BPredUnit.lookups 254458067 # Number of BP lookups
-global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-host_inst_rate 116972 # Simulator instruction rate (inst/s)
-host_mem_usage 204276 # Number of bytes of host memory used
-host_seconds 12016.73 # Real time elapsed on the host
-host_tick_rate 91760367 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 301399355 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1405618365 # Number of instructions simulated
-sim_seconds 1.102659 # Number of seconds simulated
-sim_ticks 1102659164000 # Number of ticks simulated
-system.cpu.commit.COM:branches 86248929 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 8096119 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 1964055138
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 1088074348 5539.94%
- 1 575643775 2930.89%
- 2 120435536 613.20%
- 3 120975808 615.95%
- 4 27955061 142.33%
- 5 8084154 41.16%
- 6 10447088 53.19%
- 7 4343249 22.11%
- 8 8096119 41.22%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 1489537508 # Number of instructions committed
-system.cpu.commit.COM:loads 402517243 # Number of loads committed
-system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
-system.cpu.commit.COM:refs 569375199 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 1390237691 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 1405618365 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated
-system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14297.934404 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.549883 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 425346266 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 13092161000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 915668 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 667355 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1685933500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses
-system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 38037.500000 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35037.500000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 1521500 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 37763.233543 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.301493 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 83930070500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 12696279000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1119.158506 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30916.502985 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 589980362 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 97022231500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 3138202 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2537980 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 14382212500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30916.502985 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 589980362 # number of overall hits
-system.cpu.dcache.overall_miss_latency 97022231500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 3138202 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2537980 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 14382212500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 523278 # number of replacements
-system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use
-system.cpu.dcache.total_refs 590215098 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 348745 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 416443424 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 3435538867 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 762668523 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 782001807 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 239759981 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 2941384 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 254458067 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 354588627 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1199300776 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 10659934 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 3732201090 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 88873600 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 354588627 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 2203815119
-system.cpu.fetch.rateDist.min_value 0
- 0 1359103013 6167.05%
- 1 256500552 1163.89%
- 2 81150170 368.23%
- 3 38425919 174.36%
- 4 85384466 387.44%
- 5 41200028 186.95%
- 6 32567288 147.78%
- 7 20688755 93.88%
- 8 288794928 1310.43%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 354588627 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 354586500 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 748 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 257319.666183 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 354588627 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency
-system.cpu.icache.demand_hits 354586500 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
-system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 748 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 47986500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 1379 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 354588627 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 354586500 # number of overall hits
-system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
-system.cpu.icache.overall_misses 2127 # number of overall misses
-system.cpu.icache.overall_mshr_hits 748 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 47986500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 222 # number of replacements
-system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1057.993155 # Cycle average of tags in use
-system.cpu.icache.total_refs 354586500 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1503210 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 128154505 # Number of branches executed
-system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate
-system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 207432555 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1490113295 # num instructions consuming a value
-system.cpu.iew.WB:count 1862924805 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1435567316 # num instructions producing a value
-system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle
-system.cpu.iew.WB:sent 1872447494 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 91815045 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 3100813 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21390970 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 17059388 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 301399355 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 2879831212 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 94512452 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 1894795224 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 9887 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 239759981 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 75706 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 47414 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 134541399 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 90333501 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 1989307676 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 0 0.00% # Type of FU issued
- IntAlu 1186637130 59.65% # Type of FU issued
- IntMult 0 0.00% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2990817 0.15% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 571681967 28.74% # Type of FU issued
- MemWrite 227997762 11.46% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 4014629 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 142220 3.54% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 232758 5.80% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 3328923 82.92% # attempts to use FU when none available
- MemWrite 310728 7.74% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 2203815119
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 1083882017 4918.21%
- 1 586425796 2660.96%
- 2 298714416 1355.44%
- 3 164995052 748.68%
- 4 47215795 214.25%
- 5 14943133 67.81%
- 6 6716024 30.47%
- 7 790185 3.59%
- 8 132701 0.60%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate
-system.cpu.iq.iqInstsAdded 2506731523 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 1989307676 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21683048 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 1079315476 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 646020 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 19439377 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 1293054260 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.559254 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.513074 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 9570274000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34106.905217 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384556 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 214675 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1194321500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.140241 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 35017 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1085610500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140241 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 35017 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 2493281000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 72896 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 348745 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 348745 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 4.234582 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34273.637440 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 214675 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 10764595500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.593998 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 314078 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 9781573500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.593998 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 314078 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34273.637440 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 214675 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 10764595500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.593998 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 314078 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 9781573500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.593998 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 314078 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 84497 # number of replacements
-system.cpu.l2cache.sampled_refs 99948 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16402.911294 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 423238 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 61945 # number of writebacks
-system.cpu.numCycles 2205318329 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 17694794 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed
-system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers
-system.cpu.rename.RENAME:IQFullEvents 27112 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 826425908 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 23298987 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 4917191839 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 3093611624 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 2420068293 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 717791899 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 239759981 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 32521117 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 1175289043 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 369621420 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 21984764 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 170791733 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21775085 # count of temporary serializing insts renamed
-system.cpu.timesIdled 43186 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:55:58
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 1102659164000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 182414509 # Number of BTB hits
+global.BPredUnit.BTBLookups 203429504 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted
+global.BPredUnit.lookups 254458067 # Number of BP lookups
+global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+host_inst_rate 116972 # Simulator instruction rate (inst/s)
+host_mem_usage 204276 # Number of bytes of host memory used
+host_seconds 12016.73 # Real time elapsed on the host
+host_tick_rate 91760367 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 301399355 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1405618365 # Number of instructions simulated
+sim_seconds 1.102659 # Number of seconds simulated
+sim_ticks 1102659164000 # Number of ticks simulated
+system.cpu.commit.COM:branches 86248929 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 8096119 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 1964055138
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 1088074348 5539.94%
+ 1 575643775 2930.89%
+ 2 120435536 613.20%
+ 3 120975808 615.95%
+ 4 27955061 142.33%
+ 5 8084154 41.16%
+ 6 10447088 53.19%
+ 7 4343249 22.11%
+ 8 8096119 41.22%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 1489537508 # Number of instructions committed
+system.cpu.commit.COM:loads 402517243 # Number of loads committed
+system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
+system.cpu.commit.COM:refs 569375199 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 1390237691 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1405618365 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated
+system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14297.934404 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.549883 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 425346266 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 13092161000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 915668 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 667355 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1685933500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_avg_miss_latency 38037.500000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35037.500000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 1521500 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 37763.233543 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.301493 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 83930070500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 12696279000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 1119.158506 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 30916.502985 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 589980362 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 97022231500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 3138202 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2537980 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 14382212500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 30916.502985 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 589980362 # number of overall hits
+system.cpu.dcache.overall_miss_latency 97022231500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 3138202 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2537980 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 14382212500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 523278 # number of replacements
+system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use
+system.cpu.dcache.total_refs 590215098 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 348745 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 416443424 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 3435538867 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 762668523 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 782001807 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 239759981 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 2941384 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 254458067 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 354588627 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1199300776 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 10659934 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 3732201090 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 88873600 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 354588627 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 2203815119
+system.cpu.fetch.rateDist.min_value 0
+ 0 1359103013 6167.05%
+ 1 256500552 1163.89%
+ 2 81150170 368.23%
+ 3 38425919 174.36%
+ 4 85384466 387.44%
+ 5 41200028 186.95%
+ 6 32567288 147.78%
+ 7 20688755 93.88%
+ 8 288794928 1310.43%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 354588627 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 354586500 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 748 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 257319.666183 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 354588627 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency
+system.cpu.icache.demand_hits 354586500 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
+system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 748 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 47986500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 1379 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 354588627 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 354586500 # number of overall hits
+system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
+system.cpu.icache.overall_misses 2127 # number of overall misses
+system.cpu.icache.overall_mshr_hits 748 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 47986500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 222 # number of replacements
+system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1057.993155 # Cycle average of tags in use
+system.cpu.icache.total_refs 354586500 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 1503210 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 128154505 # Number of branches executed
+system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate
+system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 207432555 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 1490113295 # num instructions consuming a value
+system.cpu.iew.WB:count 1862924805 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 1435567316 # num instructions producing a value
+system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle
+system.cpu.iew.WB:sent 1872447494 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 91815045 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 3100813 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 21390970 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 17059388 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 301399355 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 2879831212 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 94512452 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 1894795224 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 9887 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 239759981 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 75706 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 47414 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 134541399 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 90333501 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 1989307676 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 0 0.00% # Type of FU issued
+ IntAlu 1186637130 59.65% # Type of FU issued
+ IntMult 0 0.00% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2990817 0.15% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 571681967 28.74% # Type of FU issued
+ MemWrite 227997762 11.46% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 4014629 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 142220 3.54% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 232758 5.80% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 3328923 82.92% # attempts to use FU when none available
+ MemWrite 310728 7.74% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 2203815119
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 1083882017 4918.21%
+ 1 586425796 2660.96%
+ 2 298714416 1355.44%
+ 3 164995052 748.68%
+ 4 47215795 214.25%
+ 5 14943133 67.81%
+ 6 6716024 30.47%
+ 7 790185 3.59%
+ 8 132701 0.60%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate
+system.cpu.iq.iqInstsAdded 2506731523 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 1989307676 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 21683048 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 1079315476 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 646020 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 19439377 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 1293054260 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.559254 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.513074 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 9570274000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34106.905217 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384556 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 214675 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1194321500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.140241 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 35017 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1085610500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140241 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 35017 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 2493281000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 72896 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 348745 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 348745 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 4.234582 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34273.637440 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 214675 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 10764595500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.593998 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 314078 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 9781573500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.593998 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 314078 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34273.637440 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 214675 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 10764595500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.593998 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 314078 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 9781573500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.593998 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 314078 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 84497 # number of replacements
+system.cpu.l2cache.sampled_refs 99948 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 16402.911294 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 423238 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 61945 # number of writebacks
+system.cpu.numCycles 2205318329 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 17694794 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed
+system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers
+system.cpu.rename.RENAME:IQFullEvents 27112 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 826425908 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 23298987 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 4917191839 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 3093611624 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2420068293 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 717791899 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 239759981 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 32521117 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 1175289043 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 369621420 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 21984764 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 170791733 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 21775085 # count of temporary serializing insts renamed
+system.cpu.timesIdled 43186 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:55:58
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Duplicating 262144 bytes
-Duplicating 524288 bytes
-Input data 1048576 bytes in length
-Compressing Input Data, level 1
-Compressed data 108074 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 3
-Compressed data 97831 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 5
-Compressed data 83382 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 7
-Compressed data 76606 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 73189 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 1102659164000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 2833353 # Simulator instruction rate (inst/s)
-host_mem_usage 195884 # Number of bytes of host memory used
-host_seconds 525.71 # Real time elapsed on the host
-host_tick_rate 1416680719 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1489523295 # Number of instructions simulated
-sim_seconds 0.744764 # Number of seconds simulated
-sim_ticks 744764119000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1489528239 # number of cpu cycles simulated
-system.cpu.num_insts 1489523295 # Number of instructions executed
-system.cpu.num_refs 569365767 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:45:38
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 744764119000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2833353 # Simulator instruction rate (inst/s)
+host_mem_usage 195884 # Number of bytes of host memory used
+host_seconds 525.71 # Real time elapsed on the host
+host_tick_rate 1416680719 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1489523295 # Number of instructions simulated
+sim_seconds 0.744764 # Number of seconds simulated
+sim_ticks 744764119000 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1489528239 # number of cpu cycles simulated
+system.cpu.num_insts 1489523295 # Number of instructions executed
+system.cpu.num_refs 569365767 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:45:38
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Duplicating 262144 bytes
-Duplicating 524288 bytes
-Input data 1048576 bytes in length
-Compressing Input Data, level 1
-Compressed data 108074 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 3
-Compressed data 97831 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 5
-Compressed data 83382 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 7
-Compressed data 76606 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 73189 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 744764119000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 2121797 # Simulator instruction rate (inst/s)
-host_mem_usage 203340 # Number of bytes of host memory used
-host_seconds 702.01 # Real time elapsed on the host
-host_tick_rate 2963511011 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1489523295 # Number of instructions simulated
-sim_seconds 2.080416 # Number of seconds simulated
-sim_ticks 2080416155000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4079810000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3499352000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses
-system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 42833.642251 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 21977128000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 20437885000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 42833.642251 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 568846579 # number of overall hits
-system.cpu.dcache.overall_miss_latency 21977128000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 513081 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 20437885000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 449125 # number of replacements
-system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.205833 # Cycle average of tags in use
-system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 596368000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 316420 # number of writebacks
-system.cpu.icache.ReadReq_accesses 1489528206 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1489527099 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1345552.934959 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1489528206 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1489527099 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1489528206 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1489527099 # number of overall hits
-system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1107 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 118 # number of replacements
-system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 906.330613 # Cycle average of tags in use
-system.cpu.icache.total_refs 1489527099 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 160847 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1754792000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.173418 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 33746 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1349840000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173418 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 33746 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 316420 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 316420 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.428762 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 160847 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 15261012000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.645967 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 293481 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 11739240000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.645967 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 293481 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 160847 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 15261012000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.645967 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 293481 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 11739240000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 82905 # number of replacements
-system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16356.207611 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 61861 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 4160832310 # number of cpu cycles simulated
-system.cpu.num_insts 1489523295 # Number of instructions executed
-system.cpu.num_refs 569365767 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:41:13
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 2080416155000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2121797 # Simulator instruction rate (inst/s)
+host_mem_usage 203340 # Number of bytes of host memory used
+host_seconds 702.01 # Real time elapsed on the host
+host_tick_rate 2963511011 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1489523295 # Number of instructions simulated
+sim_seconds 2.080416 # Number of seconds simulated
+sim_ticks 2080416155000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4079810000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 3499352000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 42833.642251 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 21977128000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 20437885000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 42833.642251 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 568846579 # number of overall hits
+system.cpu.dcache.overall_miss_latency 21977128000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 513081 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 20437885000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 449125 # number of replacements
+system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4095.205833 # Cycle average of tags in use
+system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 596368000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 316420 # number of writebacks
+system.cpu.icache.ReadReq_accesses 1489528206 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1489527099 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1345552.934959 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1489528206 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1489527099 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1489528206 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1489527099 # number of overall hits
+system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1107 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 118 # number of replacements
+system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 906.330613 # Cycle average of tags in use
+system.cpu.icache.total_refs 1489527099 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 160847 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1754792000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.173418 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 33746 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1349840000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173418 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 33746 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 316420 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 316420 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 3.428762 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 160847 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 15261012000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.645967 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 293481 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 11739240000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.645967 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 293481 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 160847 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 15261012000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.645967 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 293481 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 11739240000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 82905 # number of replacements
+system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 16356.207611 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 61861 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 4160832310 # number of cpu cycles simulated
+system.cpu.num_insts 1489523295 # Number of instructions executed
+system.cpu.num_refs 569365767 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:41:13
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Duplicating 262144 bytes
-Duplicating 524288 bytes
-Input data 1048576 bytes in length
-Compressing Input Data, level 1
-Compressed data 108074 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 3
-Compressed data 97831 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 5
-Compressed data 83382 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 7
-Compressed data 76606 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 73189 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 2080416155000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1613706 # Simulator instruction rate (inst/s)
-host_mem_usage 195008 # Number of bytes of host memory used
-host_seconds 1003.53 # Real time elapsed on the host
-host_tick_rate 959566027 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1619398860 # Number of instructions simulated
-sim_seconds 0.962952 # Number of seconds simulated
-sim_ticks 962951801000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1925903603 # number of cpu cycles simulated
-system.cpu.num_insts 1619398860 # Number of instructions executed
-system.cpu.num_refs 607161871 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: instruction 'prefetch_t0' unimplemented
+warn: instruction 'prefetch_t0' unimplemented
+warn: instruction 'prefetch_t0' unimplemented
+warn: instruction 'prefetch_t0' unimplemented
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 23:03:02
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 23:03:28
+M5 executing on zizzer
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 962951801000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1613706 # Simulator instruction rate (inst/s)
+host_mem_usage 195008 # Number of bytes of host memory used
+host_seconds 1003.53 # Real time elapsed on the host
+host_tick_rate 959566027 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1619398860 # Number of instructions simulated
+sim_seconds 0.962952 # Number of seconds simulated
+sim_ticks 962951801000 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1925903603 # number of cpu cycles simulated
+system.cpu.num_insts 1619398860 # Number of instructions executed
+system.cpu.num_refs 607161871 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-warn: instruction 'prefetch_t0' unimplemented
-warn: instruction 'prefetch_t0' unimplemented
-warn: instruction 'prefetch_t0' unimplemented
-warn: instruction 'prefetch_t0' unimplemented
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 23:03:02
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 23:03:28
-M5 executing on zizzer
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Duplicating 262144 bytes
-Duplicating 524288 bytes
-Input data 1048576 bytes in length
-Compressing Input Data, level 1
-Compressed data 108074 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 3
-Compressed data 97831 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 5
-Compressed data 83382 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 7
-Compressed data 76606 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 73189 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 962951801000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1159099 # Simulator instruction rate (inst/s)
-host_mem_usage 201888 # Number of bytes of host memory used
-host_seconds 1397.12 # Real time elapsed on the host
-host_tick_rate 1828142910 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1619398860 # Number of instructions simulated
-sim_seconds 2.554133 # Number of seconds simulated
-sim_ticks 2554132875000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 418964598 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 418770218 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3505700000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000464 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 194380 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 187874337 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 17456264000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.001656 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 311719 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 16521107000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1367.063429 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 607150654 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 606644555 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 20026807000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 506099 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 607150654 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 606644555 # number of overall hits
-system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 506099 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 20026807000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 439707 # number of replacements
-system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.607929 # Cycle average of tags in use
-system.cpu.dcache.total_refs 606706851 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1594645000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 308507 # number of writebacks
-system.cpu.icache.ReadReq_accesses 1925903562 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1925902841 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 2671155.119279 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1925903562 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1925902841 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
-system.cpu.icache.demand_misses 721 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1925903562 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1925902841 # number of overall hits
-system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
-system.cpu.icache.overall_misses 721 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 4 # number of replacements
-system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 658.723848 # Cycle average of tags in use
-system.cpu.icache.total_refs 1925902841 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 249423 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 12969996000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 249423 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 9976920000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 249423 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 195101 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 161820 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1730612000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.170583 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 33281 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1331240000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170583 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 33281 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 62296 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 3239392000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 62296 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2491840000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 62296 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 308507 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 308507 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.404798 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 444524 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 161820 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 14700608000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.635970 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 282704 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 11308160000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.635970 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 282704 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 444524 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 161820 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 14700608000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.635970 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 282704 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 11308160000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.635970 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 282704 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 82097 # number of replacements
-system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16427.976695 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 61702 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 5108265750 # number of cpu cycles simulated
-system.cpu.num_insts 1619398860 # Number of instructions executed
-system.cpu.num_refs 607161871 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: instruction 'prefetch_t0' unimplemented
+warn: instruction 'prefetch_t0' unimplemented
+warn: instruction 'prefetch_t0' unimplemented
+warn: instruction 'prefetch_t0' unimplemented
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 7 2008 03:21:37
+M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5
+M5 commit date Thu Nov 06 23:13:50 2008 -0800
+M5 started Nov 8 2008 00:23:58
+M5 executing on tater
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 2554132875000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1159099 # Simulator instruction rate (inst/s)
+host_mem_usage 201888 # Number of bytes of host memory used
+host_seconds 1397.12 # Real time elapsed on the host
+host_tick_rate 1828142910 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1619398860 # Number of instructions simulated
+sim_seconds 2.554133 # Number of seconds simulated
+sim_ticks 2554132875000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 418964598 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 418770218 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 3505700000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000464 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 194380 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 187874337 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 17456264000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.001656 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 311719 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 16521107000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 1367.063429 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 607150654 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 606644555 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 20026807000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 506099 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 607150654 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 606644555 # number of overall hits
+system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 506099 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 20026807000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 439707 # number of replacements
+system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4094.607929 # Cycle average of tags in use
+system.cpu.dcache.total_refs 606706851 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 1594645000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 308507 # number of writebacks
+system.cpu.icache.ReadReq_accesses 1925903562 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1925902841 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 2671155.119279 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1925903562 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1925902841 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
+system.cpu.icache.demand_misses 721 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1925903562 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1925902841 # number of overall hits
+system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
+system.cpu.icache.overall_misses 721 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 4 # number of replacements
+system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 658.723848 # Cycle average of tags in use
+system.cpu.icache.total_refs 1925902841 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses 249423 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 12969996000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 249423 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 9976920000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 249423 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 195101 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 161820 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1730612000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.170583 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 33281 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1331240000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170583 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 33281 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 62296 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 3239392000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 62296 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2491840000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 62296 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 308507 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 308507 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 3.404798 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 444524 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 161820 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 14700608000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.635970 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 282704 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 11308160000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.635970 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 282704 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 444524 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 161820 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 14700608000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.635970 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 282704 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 11308160000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.635970 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 282704 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 82097 # number of replacements
+system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 16427.976695 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 61702 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 5108265750 # number of cpu cycles simulated
+system.cpu.num_insts 1619398860 # Number of instructions executed
+system.cpu.num_refs 607161871 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-warn: instruction 'prefetch_t0' unimplemented
-warn: instruction 'prefetch_t0' unimplemented
-warn: instruction 'prefetch_t0' unimplemented
-warn: instruction 'prefetch_t0' unimplemented
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 7 2008 03:21:37
-M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5
-M5 commit date Thu Nov 06 23:13:50 2008 -0800
-M5 started Nov 8 2008 00:23:58
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/x86/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Duplicating 262144 bytes
-Duplicating 524288 bytes
-Input data 1048576 bytes in length
-Compressing Input Data, level 1
-Compressed data 108074 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 3
-Compressed data 97831 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 5
-Compressed data 83382 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 7
-Compressed data 76606 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 73189 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 2554132875000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 4974822 # Number of BTB hits
-global.BPredUnit.BTBHits 2263931 # Number of BTB hits
-global.BPredUnit.BTBLookups 9262166 # Number of BTB lookups
-global.BPredUnit.BTBLookups 5044198 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 24314 # Number of incorrect RAS predictions.
-global.BPredUnit.RASInCorrect 16401 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 550360 # Number of conditional branches incorrect
-global.BPredUnit.condIncorrect 327538 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 8474519 # Number of conditional branches predicted
-global.BPredUnit.condPredicted 4548926 # Number of conditional branches predicted
-global.BPredUnit.lookups 10092697 # Number of BP lookups
-global.BPredUnit.lookups 5530798 # Number of BP lookups
-global.BPredUnit.usedRAS 690318 # Number of times the RAS was used to get a target.
-global.BPredUnit.usedRAS 415111 # Number of times the RAS was used to get a target.
-host_inst_rate 121094 # Simulator instruction rate (inst/s)
-host_mem_usage 292872 # Number of bytes of host memory used
-host_seconds 463.72 # Real time elapsed on the host
-host_tick_rate 4113887240 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 2050196 # Number of conflicting loads.
-memdepunit.memDep.conflictingLoads 902547 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 1831551 # Number of conflicting stores.
-memdepunit.memDep.conflictingStores 816276 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 7552776 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedLoads 4240735 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 4835977 # Number of stores inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 2555030 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 56154063 # Number of instructions simulated
-sim_seconds 1.907705 # Number of seconds simulated
-sim_ticks 1907705350500 # Number of ticks simulated
-system.cpu0.commit.COM:branches 5979955 # Number of branches committed
-system.cpu0.commit.COM:bw_lim_events 670629 # number cycles where commit BW limit reached
-system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle.samples 69429521
-system.cpu0.commit.COM:committed_per_cycle.min_value 0
- 0 52132882 7508.75%
- 1 7659816 1103.25%
- 2 4444319 640.12%
- 3 2023012 291.38%
- 4 1474688 212.40%
- 5 453462 65.31%
- 6 276660 39.85%
- 7 294053 42.35%
- 8 670629 96.59%
-system.cpu0.commit.COM:committed_per_cycle.max_value 8
-system.cpu0.commit.COM:committed_per_cycle.end_dist
-
-system.cpu0.commit.COM:count 39866915 # Number of instructions committed
-system.cpu0.commit.COM:loads 6404567 # Number of loads committed
-system.cpu0.commit.COM:membars 151031 # Number of memory barriers committed
-system.cpu0.commit.COM:refs 10831807 # Number of memory references committed
-system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.branchMispredicts 524319 # The number of times a branch was mispredicted
-system.cpu0.commit.commitCommittedInsts 39866915 # The number of committed instructions
-system.cpu0.commit.commitNonSpecStalls 458411 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.commitSquashedInsts 6215021 # The number of squashed insts skipped by commit
-system.cpu0.committedInsts 37661300 # Number of Instructions Simulated
-system.cpu0.committedInsts_total 37661300 # Number of Instructions Simulated
-system.cpu0.cpi 2.679168 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.679168 # CPI: Total CPI of All Threads
-system.cpu0.dcache.LoadLockedReq_accesses 147705 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15410.210138 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11873.163354 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits 135237 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency 192134500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate 0.084411 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses 12468 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_hits 3212 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109898000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062665 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 9256 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses 6414335 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 28975.310559 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.266435 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits 5467655 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 27430347000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate 0.147588 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 946680 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_hits 250995 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_miss_latency 19978171500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108458 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 695685 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639869500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses 156562 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency 54665.657574 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51665.657574 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits 140541 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency 875798500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate 0.102330 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses 16021 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827735500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102330 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses 16021 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses 4258124 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 48857.609779 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53932.670870 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits 2612795 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 80386842240 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.386398 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 1645329 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_hits 1362201 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_miss_latency 15269849238 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066491 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 283128 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050385997 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9304.837348 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles_no_targets 16250 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 9.224078 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked_no_mshrs 116353 # number of cycles access was blocked
-system.cpu0.dcache.blocked_no_targets 2 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles_no_mshrs 1082645740 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles_no_targets 32500 # number of cycles access was blocked
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 10672459 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 41595.993394 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 8080450 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 107817189240 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.242869 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 2592009 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 1613196 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 35248020738 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.091714 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 978813 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 10672459 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 41595.993394 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 8080450 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 107817189240 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.242869 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 2592009 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 1613196 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 35248020738 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.091714 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 978813 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 1690255497 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.dcache.replacements 922698 # number of replacements
-system.cpu0.dcache.sampled_refs 923094 # Sample count of references to valid blocks.
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 442.177178 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 8514691 # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 297324 # number of writebacks
-system.cpu0.decode.DECODE:BlockedCycles 33637373 # Number of cycles decode is blocked
-system.cpu0.decode.DECODE:BranchMispred 26509 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DECODE:BranchResolved 401334 # Number of times decode resolved a branch
-system.cpu0.decode.DECODE:DecodedInsts 50924220 # Number of instructions handled by decode
-system.cpu0.decode.DECODE:IdleCycles 25725806 # Number of cycles decode is idle
-system.cpu0.decode.DECODE:RunCycles 9142179 # Number of cycles decode is running
-system.cpu0.decode.DECODE:SquashCycles 1093475 # Number of cycles decode is squashing
-system.cpu0.decode.DECODE:SquashedInsts 84178 # Number of squashed instructions handled by decode
-system.cpu0.decode.DECODE:UnblockCycles 924162 # Number of cycles decode is unblocking
-system.cpu0.dtb.accesses 812630 # DTB accesses
-system.cpu0.dtb.acv 800 # DTB access violations
-system.cpu0.dtb.hits 11624529 # DTB hits
-system.cpu0.dtb.misses 28502 # DTB misses
-system.cpu0.dtb.read_accesses 605275 # DTB read accesses
-system.cpu0.dtb.read_acv 596 # DTB read access violations
-system.cpu0.dtb.read_hits 7062851 # DTB read hits
-system.cpu0.dtb.read_misses 24043 # DTB read misses
-system.cpu0.dtb.write_accesses 207355 # DTB write accesses
-system.cpu0.dtb.write_acv 204 # DTB write access violations
-system.cpu0.dtb.write_hits 4561678 # DTB write hits
-system.cpu0.dtb.write_misses 4459 # DTB write misses
-system.cpu0.fetch.Branches 10092697 # Number of branches that fetch encountered
-system.cpu0.fetch.CacheLines 6456334 # Number of cache lines fetched
-system.cpu0.fetch.Cycles 16708506 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.IcacheSquashes 292498 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.Insts 51999783 # Number of instructions fetch has processed
-system.cpu0.fetch.MiscStallCycles 404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.SquashCycles 660089 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.branchRate 0.100026 # Number of branch fetches per cycle
-system.cpu0.fetch.icacheStallCycles 6456334 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.predictedBranches 5665140 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.rate 0.515355 # Number of inst fetches per cycle
-system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist.samples 70522996
-system.cpu0.fetch.rateDist.min_value 0
- 0 60301622 8550.63%
- 1 760699 107.87%
- 2 1434176 203.36%
- 3 635243 90.08%
- 4 2330465 330.45%
- 5 474381 67.27%
- 6 552250 78.31%
- 7 815542 115.64%
- 8 3218618 456.39%
-system.cpu0.fetch.rateDist.max_value 8
-system.cpu0.fetch.rateDist.end_dist
-
-system.cpu0.icache.ReadReq_accesses 6456334 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 15194.690740 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.490595 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits 5806036 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 9881076999 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate 0.100722 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 650298 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_hits 29862 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_miss_latency 7526813499 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.096097 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses 620436 # number of ReadReq MSHR misses
-system.cpu0.icache.avg_blocked_cycles_no_mshrs 11557.114286 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 9.359502 # Average number of references to valid blocks.
-system.cpu0.icache.blocked_no_mshrs 35 # number of cycles access was blocked
-system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles_no_mshrs 404499 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 6456334 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 15194.690740 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency
-system.cpu0.icache.demand_hits 5806036 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 9881076999 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.100722 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 650298 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 29862 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 7526813499 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0.096097 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 620436 # number of demand (read+write) MSHR misses
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses 6456334 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 15194.690740 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 5806036 # number of overall hits
-system.cpu0.icache.overall_miss_latency 9881076999 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.100722 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 650298 # number of overall misses
-system.cpu0.icache.overall_mshr_hits 29862 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 7526813499 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0.096097 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 620436 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.icache.replacements 619824 # number of replacements
-system.cpu0.icache.sampled_refs 620336 # Sample count of references to valid blocks.
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 509.829045 # Cycle average of tags in use
-system.cpu0.icache.total_refs 5806036 # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idleCycles 30377936 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.iew.EXEC:branches 6436145 # Number of branches executed
-system.cpu0.iew.EXEC:nop 2512619 # number of nop insts executed
-system.cpu0.iew.EXEC:rate 0.402630 # Inst execution rate
-system.cpu0.iew.EXEC:refs 11739664 # number of memory reference insts executed
-system.cpu0.iew.EXEC:stores 4575851 # Number of stores executed
-system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu0.iew.WB:consumers 24160254 # num instructions consuming a value
-system.cpu0.iew.WB:count 40224289 # cumulative count of insts written-back
-system.cpu0.iew.WB:fanout 0.779043 # average fanout of values written-back
-system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.iew.WB:producers 18821888 # num instructions producing a value
-system.cpu0.iew.WB:rate 0.398651 # insts written-back per cycle
-system.cpu0.iew.WB:sent 40292052 # cumulative count of insts sent to commit
-system.cpu0.iew.branchMispredicts 568729 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewBlockCycles 7177517 # Number of cycles IEW is blocking
-system.cpu0.iew.iewDispLoadInsts 7552776 # Number of dispatched load instructions
-system.cpu0.iew.iewDispNonSpecInsts 1229726 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewDispSquashedInsts 771663 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispStoreInsts 4835977 # Number of dispatched store instructions
-system.cpu0.iew.iewDispatchedInsts 46188038 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewExecLoadInsts 7163813 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 359179 # Number of squashed instructions skipped in execute
-system.cpu0.iew.iewExecutedInsts 40625745 # Number of executed instructions
-system.cpu0.iew.iewIQFullEvents 33838 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewLSQFullEvents 4189 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.iewSquashCycles 1093475 # Number of cycles IEW is squashing
-system.cpu0.iew.iewUnblockCycles 453457 # Number of cycles IEW is unblocking
-system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread.0.cacheBlocked 242605 # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.lsq.thread.0.forwLoads 357762 # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread.0.ignoredResponses 8885 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread.0.memOrderViolation 33999 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread.0.rescheduledLoads 12233 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread.0.squashedLoads 1148209 # Number of loads squashed
-system.cpu0.iew.lsq.thread.0.squashedStores 408737 # Number of stores squashed
-system.cpu0.iew.memOrderViolationEvents 33999 # Number of memory order violations
-system.cpu0.iew.predictedNotTakenIncorrect 255829 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.predictedTakenIncorrect 312900 # Number of branches that were predicted taken incorrectly
-system.cpu0.ipc 0.373250 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.373250 # IPC: Total IPC of All Threads
-system.cpu0.iq.ISSUE:FU_type_0 40984924 # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 3324 0.01% # Type of FU issued
- IntAlu 28266314 68.97% # Type of FU issued
- IntMult 42210 0.10% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 12073 0.03% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 1656 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 7397265 18.05% # Type of FU issued
- MemWrite 4611960 11.25% # Type of FU issued
- IprAccess 650122 1.59% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0.end_dist
-system.cpu0.iq.ISSUE:fu_busy_cnt 290360 # FU busy when requested
-system.cpu0.iq.ISSUE:fu_busy_rate 0.007085 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 33477 11.53% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 185557 63.91% # attempts to use FU when none available
- MemWrite 71326 24.56% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full.end_dist
-system.cpu0.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle.samples 70522996
-system.cpu0.iq.ISSUE:issued_per_cycle.min_value 0
- 0 49763845 7056.40%
- 1 10504305 1489.49%
- 2 4625788 655.93%
- 3 2839071 402.57%
- 4 1729907 245.30%
- 5 663571 94.09%
- 6 315326 44.71%
- 7 67073 9.51%
- 8 14110 2.00%
-system.cpu0.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu0.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu0.iq.ISSUE:rate 0.406190 # Inst issue rate
-system.cpu0.iq.iqInstsAdded 42277563 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqInstsIssued 40984924 # Number of instructions issued
-system.cpu0.iq.iqNonSpecInstsAdded 1397856 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqSquashedInstsExamined 5734915 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedInstsIssued 23390 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedNonSpecRemoved 939445 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.iqSquashedOperandsExamined 3057501 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.itb.accesses 875611 # ITB accesses
-system.cpu0.itb.acv 895 # ITB acv
-system.cpu0.itb.hits 845707 # ITB hits
-system.cpu0.itb.misses 29904 # ITB misses
-system.cpu0.kern.callpal 129595 # number of callpals executed
-system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal_wripir 96 0.07% 0.07% # number of callpals executed
-system.cpu0.kern.callpal_wrmces 1 0.00% 0.08% # number of callpals executed
-system.cpu0.kern.callpal_wrfen 1 0.00% 0.08% # number of callpals executed
-system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.08% # number of callpals executed
-system.cpu0.kern.callpal_swpctx 2410 1.86% 1.94% # number of callpals executed
-system.cpu0.kern.callpal_tbi 51 0.04% 1.98% # number of callpals executed
-system.cpu0.kern.callpal_wrent 7 0.01% 1.98% # number of callpals executed
-system.cpu0.kern.callpal_swpipl 116022 89.53% 91.51% # number of callpals executed
-system.cpu0.kern.callpal_rdps 6357 4.91% 96.41% # number of callpals executed
-system.cpu0.kern.callpal_wrkgp 1 0.00% 96.41% # number of callpals executed
-system.cpu0.kern.callpal_wrusp 3 0.00% 96.42% # number of callpals executed
-system.cpu0.kern.callpal_rdusp 9 0.01% 96.42% # number of callpals executed
-system.cpu0.kern.callpal_whami 2 0.00% 96.43% # number of callpals executed
-system.cpu0.kern.callpal_rti 4116 3.18% 99.60% # number of callpals executed
-system.cpu0.kern.callpal_callsys 381 0.29% 99.90% # number of callpals executed
-system.cpu0.kern.callpal_imb 136 0.10% 100.00% # number of callpals executed
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.hwrei 144434 # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce 4855 # number of quiesce instructions executed
-system.cpu0.kern.ipl_count 122325 # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0 47769 39.05% 39.05% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_21 239 0.20% 39.25% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_22 1931 1.58% 40.82% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_30 17 0.01% 40.84% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31 72369 59.16% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_good 96409 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_0 47119 48.87% 48.87% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_21 239 0.25% 49.12% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_22 1931 2.00% 51.12% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_31 47103 48.86% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks 1907288705500 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0 1871607298000 98.13% 98.13% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_21 101503500 0.01% 98.13% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22 397998500 0.02% 98.16% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30 9331000 0.00% 98.16% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31 35172574500 1.84% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used_0 0.986393 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31 0.650873 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good_kernel 1284
-system.cpu0.kern.mode_good_user 1284
-system.cpu0.kern.mode_good_idle 0
-system.cpu0.kern.mode_switch_kernel 5894 # number of protection mode switches
-system.cpu0.kern.mode_switch_user 1284 # number of protection mode switches
-system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches
-system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel 0.217849 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks_kernel 1905144241000 99.89% 99.89% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_user 2121161500 0.11% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 2411 # number of times the context was actually changed
-system.cpu0.kern.syscall 222 # number of syscalls executed
-system.cpu0.kern.syscall_2 8 3.60% 3.60% # number of syscalls executed
-system.cpu0.kern.syscall_3 19 8.56% 12.16% # number of syscalls executed
-system.cpu0.kern.syscall_4 4 1.80% 13.96% # number of syscalls executed
-system.cpu0.kern.syscall_6 32 14.41% 28.38% # number of syscalls executed
-system.cpu0.kern.syscall_12 1 0.45% 28.83% # number of syscalls executed
-system.cpu0.kern.syscall_17 9 4.05% 32.88% # number of syscalls executed
-system.cpu0.kern.syscall_19 10 4.50% 37.39% # number of syscalls executed
-system.cpu0.kern.syscall_20 6 2.70% 40.09% # number of syscalls executed
-system.cpu0.kern.syscall_23 1 0.45% 40.54% # number of syscalls executed
-system.cpu0.kern.syscall_24 3 1.35% 41.89% # number of syscalls executed
-system.cpu0.kern.syscall_33 7 3.15% 45.05% # number of syscalls executed
-system.cpu0.kern.syscall_41 2 0.90% 45.95% # number of syscalls executed
-system.cpu0.kern.syscall_45 36 16.22% 62.16% # number of syscalls executed
-system.cpu0.kern.syscall_47 3 1.35% 63.51% # number of syscalls executed
-system.cpu0.kern.syscall_48 10 4.50% 68.02% # number of syscalls executed
-system.cpu0.kern.syscall_54 10 4.50% 72.52% # number of syscalls executed
-system.cpu0.kern.syscall_58 1 0.45% 72.97% # number of syscalls executed
-system.cpu0.kern.syscall_59 6 2.70% 75.68% # number of syscalls executed
-system.cpu0.kern.syscall_71 23 10.36% 86.04% # number of syscalls executed
-system.cpu0.kern.syscall_73 3 1.35% 87.39% # number of syscalls executed
-system.cpu0.kern.syscall_74 6 2.70% 90.09% # number of syscalls executed
-system.cpu0.kern.syscall_87 1 0.45% 90.54% # number of syscalls executed
-system.cpu0.kern.syscall_90 3 1.35% 91.89% # number of syscalls executed
-system.cpu0.kern.syscall_92 9 4.05% 95.95% # number of syscalls executed
-system.cpu0.kern.syscall_97 2 0.90% 96.85% # number of syscalls executed
-system.cpu0.kern.syscall_98 2 0.90% 97.75% # number of syscalls executed
-system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed
-system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed
-system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed
-system.cpu0.numCycles 100900932 # number of cpu cycles simulated
-system.cpu0.rename.RENAME:BlockCycles 10626974 # Number of cycles rename is blocking
-system.cpu0.rename.RENAME:CommittedMaps 27338376 # Number of HB maps that are committed
-system.cpu0.rename.RENAME:IQFullEvents 742955 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.RENAME:IdleCycles 26930007 # Number of cycles rename is idle
-system.cpu0.rename.RENAME:LSQFullEvents 1646671 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RENAME:ROBFullEvents 16625 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.RENAME:RenameLookups 58873396 # Number of register rename lookups that rename has made
-system.cpu0.rename.RENAME:RenamedInsts 48153710 # Number of instructions processed by rename
-system.cpu0.rename.RENAME:RenamedOperands 32532330 # Number of destination operands rename has renamed
-system.cpu0.rename.RENAME:RunCycles 9103233 # Number of cycles rename is running
-system.cpu0.rename.RENAME:SquashCycles 1093475 # Number of cycles rename is squashing
-system.cpu0.rename.RENAME:UnblockCycles 3612957 # Number of cycles rename is unblocking
-system.cpu0.rename.RENAME:UndoneMaps 5193954 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.RENAME:serializeStallCycles 19156348 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RENAME:serializingInsts 1163476 # count of serializing insts renamed
-system.cpu0.rename.RENAME:skidInsts 8536447 # count of insts added to the skid buffer
-system.cpu0.rename.RENAME:tempSerializingInsts 181426 # count of temporary serializing insts renamed
-system.cpu0.timesIdled 904874 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.commit.COM:branches 2941268 # Number of branches committed
-system.cpu1.commit.COM:bw_lim_events 404281 # number cycles where commit BW limit reached
-system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle.samples 37417436
-system.cpu1.commit.COM:committed_per_cycle.min_value 0
- 0 29372797 7850.03%
- 1 3570649 954.27%
- 2 1730450 462.47%
- 3 1048421 280.20%
- 4 705992 188.68%
- 5 261184 69.80%
- 6 182468 48.77%
- 7 141194 37.73%
- 8 404281 108.05%
-system.cpu1.commit.COM:committed_per_cycle.max_value 8
-system.cpu1.commit.COM:committed_per_cycle.end_dist
-
-system.cpu1.commit.COM:count 19624114 # Number of instructions committed
-system.cpu1.commit.COM:loads 3545101 # Number of loads committed
-system.cpu1.commit.COM:membars 87127 # Number of memory barriers committed
-system.cpu1.commit.COM:refs 5853378 # Number of memory references committed
-system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.branchMispredicts 311146 # The number of times a branch was mispredicted
-system.cpu1.commit.commitCommittedInsts 19624114 # The number of committed instructions
-system.cpu1.commit.commitNonSpecStalls 255253 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.commitSquashedInsts 3733069 # The number of squashed insts skipped by commit
-system.cpu1.committedInsts 18492763 # Number of Instructions Simulated
-system.cpu1.committedInsts_total 18492763 # Number of Instructions Simulated
-system.cpu1.cpi 2.312237 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 2.312237 # CPI: Total CPI of All Threads
-system.cpu1.dcache.LoadLockedReq_accesses 72124 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14446.929646 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11200.613079 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits 59829 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency 177625000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate 0.170470 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses 12295 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_hits 2019 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115097500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.142477 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses 10276 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses 3584183 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 15544.189729 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11996.806998 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits 2941941 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 9983131500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate 0.179188 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 642242 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_hits 211143 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_miss_latency 5171811500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate 0.120278 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses 431099 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 283603500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses 68163 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency 54675.738585 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51675.738585 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits 51408 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency 916092000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate 0.245808 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses 16755 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865827000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245808 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses 16755 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses 2232793 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 49361.665892 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54248.260288 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits 1538625 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 34265288889 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate 0.310897 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 694168 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_hits 551549 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_miss_latency 7736832634 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063875 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses 142619 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 511356000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.avg_blocked_cycles_no_mshrs 14029.367204 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles_no_targets 5000 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 8.864535 # Average number of references to valid blocks.
-system.cpu1.dcache.blocked_no_mshrs 31315 # number of cycles access was blocked
-system.cpu1.dcache.blocked_no_targets 1 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles_no_mshrs 439329634 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles_no_targets 5000 # number of cycles access was blocked
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 5816976 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 33109.914165 # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 4480566 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 44248420389 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.229743 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 1336410 # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits 762692 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 12908644134 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate 0.098628 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 573718 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.overall_accesses 5816976 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 33109.914165 # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 4480566 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 44248420389 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.229743 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 1336410 # number of overall misses
-system.cpu1.dcache.overall_mshr_hits 762692 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 12908644134 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate 0.098628 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses 573718 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency 794959500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.dcache.replacements 531824 # number of replacements
-system.cpu1.dcache.sampled_refs 532336 # Sample count of references to valid blocks.
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 486.799078 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 4718911 # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 39405721000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 158256 # number of writebacks
-system.cpu1.decode.DECODE:BlockedCycles 17763598 # Number of cycles decode is blocked
-system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DECODE:BranchResolved 245215 # Number of times decode resolved a branch
-system.cpu1.decode.DECODE:DecodedInsts 26209907 # Number of instructions handled by decode
-system.cpu1.decode.DECODE:IdleCycles 14707752 # Number of cycles decode is idle
-system.cpu1.decode.DECODE:RunCycles 4714008 # Number of cycles decode is running
-system.cpu1.decode.DECODE:SquashCycles 641031 # Number of cycles decode is squashing
-system.cpu1.decode.DECODE:SquashedInsts 52760 # Number of squashed instructions handled by decode
-system.cpu1.decode.DECODE:UnblockCycles 232077 # Number of cycles decode is unblocking
-system.cpu1.dtb.accesses 434054 # DTB accesses
-system.cpu1.dtb.acv 76 # DTB access violations
-system.cpu1.dtb.hits 6272530 # DTB hits
-system.cpu1.dtb.misses 17149 # DTB misses
-system.cpu1.dtb.read_accesses 314239 # DTB read accesses
-system.cpu1.dtb.read_acv 13 # DTB read access violations
-system.cpu1.dtb.read_hits 3866975 # DTB read hits
-system.cpu1.dtb.read_misses 13433 # DTB read misses
-system.cpu1.dtb.write_accesses 119815 # DTB write accesses
-system.cpu1.dtb.write_acv 63 # DTB write access violations
-system.cpu1.dtb.write_hits 2405555 # DTB write hits
-system.cpu1.dtb.write_misses 3716 # DTB write misses
-system.cpu1.fetch.Branches 5530798 # Number of branches that fetch encountered
-system.cpu1.fetch.CacheLines 3081765 # Number of cache lines fetched
-system.cpu1.fetch.Cycles 8119333 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.IcacheSquashes 192779 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.Insts 26783088 # Number of instructions fetch has processed
-system.cpu1.fetch.MiscStallCycles 1141 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.SquashCycles 373445 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.branchRate 0.129346 # Number of branch fetches per cycle
-system.cpu1.fetch.icacheStallCycles 3081765 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.predictedBranches 2679042 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.rate 0.626364 # Number of inst fetches per cycle
-system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist.samples 38058467
-system.cpu1.fetch.rateDist.min_value 0
- 0 33027824 8678.18%
- 1 336540 88.43%
- 2 683303 179.54%
- 3 398795 104.78%
- 4 792602 208.26%
- 5 252574 66.36%
- 6 340311 89.42%
- 7 403731 106.08%
- 8 1822787 478.94%
-system.cpu1.fetch.rateDist.max_value 8
-system.cpu1.fetch.rateDist.end_dist
-
-system.cpu1.icache.ReadReq_accesses 3081765 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency 14557.235908 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11605.244559 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits 2613676 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency 6814081999 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate 0.151890 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses 468089 # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_hits 20978 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_miss_latency 5188832500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate 0.145083 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses 447111 # number of ReadReq MSHR misses
-system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308 # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 5.846378 # Average number of references to valid blocks.
-system.cpu1.icache.blocked_no_mshrs 26 # number of cycles access was blocked
-system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles_no_mshrs 287500 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses 3081765 # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 14557.235908 # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency
-system.cpu1.icache.demand_hits 2613676 # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency 6814081999 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate 0.151890 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 468089 # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits 20978 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 5188832500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate 0.145083 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses 447111 # number of demand (read+write) MSHR misses
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.overall_accesses 3081765 # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 14557.235908 # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits 2613676 # number of overall hits
-system.cpu1.icache.overall_miss_latency 6814081999 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate 0.151890 # miss rate for overall accesses
-system.cpu1.icache.overall_misses 468089 # number of overall misses
-system.cpu1.icache.overall_mshr_hits 20978 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency 5188832500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate 0.145083 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses 447111 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.icache.replacements 446548 # number of replacements
-system.cpu1.icache.sampled_refs 447059 # Sample count of references to valid blocks.
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 504.476146 # Cycle average of tags in use
-system.cpu1.icache.total_refs 2613676 # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.idleCycles 4701182 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.iew.EXEC:branches 3208895 # Number of branches executed
-system.cpu1.iew.EXEC:nop 1313637 # number of nop insts executed
-system.cpu1.iew.EXEC:rate 0.474750 # Inst execution rate
-system.cpu1.iew.EXEC:refs 6445371 # number of memory reference insts executed
-system.cpu1.iew.EXEC:stores 2416978 # Number of stores executed
-system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu1.iew.WB:consumers 12350061 # num instructions consuming a value
-system.cpu1.iew.WB:count 20043548 # cumulative count of insts written-back
-system.cpu1.iew.WB:fanout 0.731488 # average fanout of values written-back
-system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.iew.WB:producers 9033918 # num instructions producing a value
-system.cpu1.iew.WB:rate 0.468749 # insts written-back per cycle
-system.cpu1.iew.WB:sent 20085855 # cumulative count of insts sent to commit
-system.cpu1.iew.branchMispredicts 338994 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewBlockCycles 2476901 # Number of cycles IEW is blocking
-system.cpu1.iew.iewDispLoadInsts 4240735 # Number of dispatched load instructions
-system.cpu1.iew.iewDispNonSpecInsts 782170 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewDispSquashedInsts 352959 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispStoreInsts 2555030 # Number of dispatched store instructions
-system.cpu1.iew.iewDispatchedInsts 23433163 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewExecLoadInsts 4028393 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 227109 # Number of squashed instructions skipped in execute
-system.cpu1.iew.iewExecutedInsts 20300122 # Number of executed instructions
-system.cpu1.iew.iewIQFullEvents 13056 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewLSQFullEvents 2312 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.iewSquashCycles 641031 # Number of cycles IEW is squashing
-system.cpu1.iew.iewUnblockCycles 92389 # Number of cycles IEW is unblocking
-system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread.0.cacheBlocked 96439 # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.lsq.thread.0.forwLoads 136590 # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread.0.ignoredResponses 5874 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread.0.memOrderViolation 18177 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread.0.rescheduledLoads 7528 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread.0.squashedLoads 695634 # Number of loads squashed
-system.cpu1.iew.lsq.thread.0.squashedStores 246753 # Number of stores squashed
-system.cpu1.iew.memOrderViolationEvents 18177 # Number of memory order violations
-system.cpu1.iew.predictedNotTakenIncorrect 160429 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.predictedTakenIncorrect 178565 # Number of branches that were predicted taken incorrectly
-system.cpu1.ipc 0.432482 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.432482 # IPC: Total IPC of All Threads
-system.cpu1.iq.ISSUE:FU_type_0 20527233 # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 3984 0.02% # Type of FU issued
- IntAlu 13446211 65.50% # Type of FU issued
- IntMult 28837 0.14% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 13702 0.07% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 1986 0.01% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 4170434 20.32% # Type of FU issued
- MemWrite 2440876 11.89% # Type of FU issued
- IprAccess 421203 2.05% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0.end_dist
-system.cpu1.iq.ISSUE:fu_busy_cnt 220615 # FU busy when requested
-system.cpu1.iq.ISSUE:fu_busy_rate 0.010747 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 16051 7.28% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 131548 59.63% # attempts to use FU when none available
- MemWrite 73016 33.10% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full.end_dist
-system.cpu1.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle.samples 38058467
-system.cpu1.iq.ISSUE:issued_per_cycle.min_value 0
- 0 28368882 7454.03%
- 1 4650018 1221.81%
- 2 1988549 522.50%
- 3 1356758 356.49%
- 4 973103 255.69%
- 5 468416 123.08%
- 6 186236 48.93%
- 7 54105 14.22%
- 8 12400 3.26%
-system.cpu1.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu1.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu1.iq.ISSUE:rate 0.480061 # Inst issue rate
-system.cpu1.iq.iqInstsAdded 21243619 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqInstsIssued 20527233 # Number of instructions issued
-system.cpu1.iq.iqNonSpecInstsAdded 875907 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqSquashedInstsExamined 3479594 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedInstsIssued 16597 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedNonSpecRemoved 620654 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.iqSquashedOperandsExamined 1771927 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.itb.accesses 525300 # ITB accesses
-system.cpu1.itb.acv 103 # ITB acv
-system.cpu1.itb.hits 518475 # ITB hits
-system.cpu1.itb.misses 6825 # ITB misses
-system.cpu1.kern.callpal 87347 # number of callpals executed
-system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal_wripir 17 0.02% 0.02% # number of callpals executed
-system.cpu1.kern.callpal_wrmces 1 0.00% 0.02% # number of callpals executed
-system.cpu1.kern.callpal_wrfen 1 0.00% 0.02% # number of callpals executed
-system.cpu1.kern.callpal_swpctx 1838 2.10% 2.13% # number of callpals executed
-system.cpu1.kern.callpal_tbi 3 0.00% 2.13% # number of callpals executed
-system.cpu1.kern.callpal_wrent 7 0.01% 2.14% # number of callpals executed
-system.cpu1.kern.callpal_swpipl 79676 91.22% 93.36% # number of callpals executed
-system.cpu1.kern.callpal_rdps 2408 2.76% 96.11% # number of callpals executed
-system.cpu1.kern.callpal_wrkgp 1 0.00% 96.11% # number of callpals executed
-system.cpu1.kern.callpal_wrusp 4 0.00% 96.12% # number of callpals executed
-system.cpu1.kern.callpal_whami 3 0.00% 96.12% # number of callpals executed
-system.cpu1.kern.callpal_rti 3206 3.67% 99.79% # number of callpals executed
-system.cpu1.kern.callpal_callsys 136 0.16% 99.95% # number of callpals executed
-system.cpu1.kern.callpal_imb 44 0.05% 100.00% # number of callpals executed
-system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.hwrei 93957 # number of hwrei instructions executed
-system.cpu1.kern.inst.quiesce 3692 # number of quiesce instructions executed
-system.cpu1.kern.ipl_count 84907 # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_0 34137 40.21% 40.21% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_22 1928 2.27% 42.48% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_30 96 0.11% 42.59% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_31 48746 57.41% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_good 68748 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_0 33410 48.60% 48.60% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_22 1928 2.80% 51.40% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_31 33314 48.46% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks 1907704497000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0 1872145700000 98.14% 98.14% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_22 351989500 0.02% 98.15% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_30 39998500 0.00% 98.16% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_31 35166809000 1.84% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used_0 0.978703 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_31 0.683420 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good_kernel 521
-system.cpu1.kern.mode_good_user 463
-system.cpu1.kern.mode_good_idle 58
-system.cpu1.kern.mode_switch_kernel 2303 # number of protection mode switches
-system.cpu1.kern.mode_switch_user 463 # number of protection mode switches
-system.cpu1.kern.mode_switch_idle 2035 # number of protection mode switches
-system.cpu1.kern.mode_switch_good 1.254728 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_kernel 0.226227 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_idle 0.028501 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel 46596073500 2.44% 2.44% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_user 1015566000 0.05% 2.50% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle 1860092849500 97.50% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 1839 # number of times the context was actually changed
-system.cpu1.kern.syscall 104 # number of syscalls executed
-system.cpu1.kern.syscall_3 11 10.58% 10.58% # number of syscalls executed
-system.cpu1.kern.syscall_6 10 9.62% 20.19% # number of syscalls executed
-system.cpu1.kern.syscall_15 1 0.96% 21.15% # number of syscalls executed
-system.cpu1.kern.syscall_17 6 5.77% 26.92% # number of syscalls executed
-system.cpu1.kern.syscall_23 3 2.88% 29.81% # number of syscalls executed
-system.cpu1.kern.syscall_24 3 2.88% 32.69% # number of syscalls executed
-system.cpu1.kern.syscall_33 4 3.85% 36.54% # number of syscalls executed
-system.cpu1.kern.syscall_45 18 17.31% 53.85% # number of syscalls executed
-system.cpu1.kern.syscall_47 3 2.88% 56.73% # number of syscalls executed
-system.cpu1.kern.syscall_59 1 0.96% 57.69% # number of syscalls executed
-system.cpu1.kern.syscall_71 31 29.81% 87.50% # number of syscalls executed
-system.cpu1.kern.syscall_74 10 9.62% 97.12% # number of syscalls executed
-system.cpu1.kern.syscall_132 3 2.88% 100.00% # number of syscalls executed
-system.cpu1.numCycles 42759649 # number of cpu cycles simulated
-system.cpu1.rename.RENAME:BlockCycles 3630480 # Number of cycles rename is blocking
-system.cpu1.rename.RENAME:CommittedMaps 13162138 # Number of HB maps that are committed
-system.cpu1.rename.RENAME:IQFullEvents 331495 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.RENAME:IdleCycles 15176071 # Number of cycles rename is idle
-system.cpu1.rename.RENAME:LSQFullEvents 648663 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RENAME:ROBFullEvents 1231 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.RENAME:RenameLookups 29369210 # Number of register rename lookups that rename has made
-system.cpu1.rename.RENAME:RenamedInsts 24481625 # Number of instructions processed by rename
-system.cpu1.rename.RENAME:RenamedOperands 16150176 # Number of destination operands rename has renamed
-system.cpu1.rename.RENAME:RunCycles 4323376 # Number of cycles rename is running
-system.cpu1.rename.RENAME:SquashCycles 641031 # Number of cycles rename is squashing
-system.cpu1.rename.RENAME:UnblockCycles 1811966 # Number of cycles rename is unblocking
-system.cpu1.rename.RENAME:UndoneMaps 2988036 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.RENAME:serializeStallCycles 12475541 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RENAME:serializingInsts 728332 # count of serializing insts renamed
-system.cpu1.rename.RENAME:skidInsts 4962004 # count of insts added to the skid buffer
-system.cpu1.rename.RENAME:tempSerializingInsts 86297 # count of temporary serializing insts renamed
-system.cpu1.timesIdled 480244 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
-system.disk0.dma_write_txs 395 # Number of DMA write transactions.
-system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency 115245.702857 # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63245.702857 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 20167998 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses 175 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 11067998 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses
-system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency 137815.912736 # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85812.468906 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 5726526806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses 41552 # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency 3565679708 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles_no_mshrs 6166.359533 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.blocked_no_mshrs 10458 # number of cycles access was blocked
-system.iocache.blocked_no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_mshrs 64487788 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses 41727 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency 137721.254919 # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency
-system.iocache.demand_hits 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 5746694804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate 1 # miss rate for demand accesses
-system.iocache.demand_misses 41727 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 3576747706 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.overall_accesses 41727 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency 137721.254919 # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.iocache.overall_hits 0 # number of overall hits
-system.iocache.overall_miss_latency 5746694804 # number of overall miss cycles
-system.iocache.overall_miss_rate 1 # miss rate for overall accesses
-system.iocache.overall_misses 41727 # number of overall misses
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 3576747706 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.iocache.replacements 41697 # number of replacements
-system.iocache.sampled_refs 41713 # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0.387818 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 1717170509000 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 41522 # number of writebacks
-system.l2c.ReadExReq_accesses 317495 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 52375.723397 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40223.099381 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 16629030300 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 317495 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 12770632938 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 317495 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 2204283 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 52067.320767 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40026.416785 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits 1893933 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 16159093000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.140794 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 310350 # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 12421518000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.140786 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 310333 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 827055500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses 141956 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 51067.196822 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.595903 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 7249294992 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 141956 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 5691526500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 141956 # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1410123998 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 455580 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 455580 # number of Writeback hits
-system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 4.836093 # Average number of references to valid blocks.
-system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2521778 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 52223.276923 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency
-system.l2c.demand_hits 1893933 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 32788123300 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.248969 # miss rate for demand accesses
-system.l2c.demand_misses 627845 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 25192150938 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.248962 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 627828 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 2521778 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 52223.276923 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 1893933 # number of overall hits
-system.l2c.overall_miss_latency 32788123300 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.248969 # miss rate for overall accesses
-system.l2c.overall_misses 627845 # number of overall misses
-system.l2c.overall_mshr_hits 17 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 25192150938 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.248962 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 627828 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 2237179498 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 402113 # number of replacements
-system.l2c.sampled_refs 433643 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 31146.703960 # Cycle average of tags in use
-system.l2c.total_refs 2097138 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 124275 # number of writebacks
-system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
-system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
-system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: kernel located at: /dist/m5/system/binaries/vmlinux
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: 125740500: Trying to launch CPU number 1!
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:35:52
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 1907705350500 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 4974822 # Number of BTB hits
+global.BPredUnit.BTBHits 2263931 # Number of BTB hits
+global.BPredUnit.BTBLookups 9262166 # Number of BTB lookups
+global.BPredUnit.BTBLookups 5044198 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 24314 # Number of incorrect RAS predictions.
+global.BPredUnit.RASInCorrect 16401 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 550360 # Number of conditional branches incorrect
+global.BPredUnit.condIncorrect 327538 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 8474519 # Number of conditional branches predicted
+global.BPredUnit.condPredicted 4548926 # Number of conditional branches predicted
+global.BPredUnit.lookups 10092697 # Number of BP lookups
+global.BPredUnit.lookups 5530798 # Number of BP lookups
+global.BPredUnit.usedRAS 690318 # Number of times the RAS was used to get a target.
+global.BPredUnit.usedRAS 415111 # Number of times the RAS was used to get a target.
+host_inst_rate 121094 # Simulator instruction rate (inst/s)
+host_mem_usage 292872 # Number of bytes of host memory used
+host_seconds 463.72 # Real time elapsed on the host
+host_tick_rate 4113887240 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 2050196 # Number of conflicting loads.
+memdepunit.memDep.conflictingLoads 902547 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 1831551 # Number of conflicting stores.
+memdepunit.memDep.conflictingStores 816276 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 7552776 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 4240735 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 4835977 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 2555030 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 56154063 # Number of instructions simulated
+sim_seconds 1.907705 # Number of seconds simulated
+sim_ticks 1907705350500 # Number of ticks simulated
+system.cpu0.commit.COM:branches 5979955 # Number of branches committed
+system.cpu0.commit.COM:bw_lim_events 670629 # number cycles where commit BW limit reached
+system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle.samples 69429521
+system.cpu0.commit.COM:committed_per_cycle.min_value 0
+ 0 52132882 7508.75%
+ 1 7659816 1103.25%
+ 2 4444319 640.12%
+ 3 2023012 291.38%
+ 4 1474688 212.40%
+ 5 453462 65.31%
+ 6 276660 39.85%
+ 7 294053 42.35%
+ 8 670629 96.59%
+system.cpu0.commit.COM:committed_per_cycle.max_value 8
+system.cpu0.commit.COM:committed_per_cycle.end_dist
+
+system.cpu0.commit.COM:count 39866915 # Number of instructions committed
+system.cpu0.commit.COM:loads 6404567 # Number of loads committed
+system.cpu0.commit.COM:membars 151031 # Number of memory barriers committed
+system.cpu0.commit.COM:refs 10831807 # Number of memory references committed
+system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu0.commit.branchMispredicts 524319 # The number of times a branch was mispredicted
+system.cpu0.commit.commitCommittedInsts 39866915 # The number of committed instructions
+system.cpu0.commit.commitNonSpecStalls 458411 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.commitSquashedInsts 6215021 # The number of squashed insts skipped by commit
+system.cpu0.committedInsts 37661300 # Number of Instructions Simulated
+system.cpu0.committedInsts_total 37661300 # Number of Instructions Simulated
+system.cpu0.cpi 2.679168 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.679168 # CPI: Total CPI of All Threads
+system.cpu0.dcache.LoadLockedReq_accesses 147705 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15410.210138 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11873.163354 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits 135237 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency 192134500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate 0.084411 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses 12468 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_hits 3212 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109898000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062665 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_misses 9256 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses 6414335 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency 28975.310559 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.266435 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_hits 5467655 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 27430347000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate 0.147588 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses 946680 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_hits 250995 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_miss_latency 19978171500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108458 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_misses 695685 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639869500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses 156562 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency 54665.657574 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51665.657574 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits 140541 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency 875798500 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate 0.102330 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses 16021 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827735500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102330 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_misses 16021 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses 4258124 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency 48857.609779 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53932.670870 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_hits 2612795 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 80386842240 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate 0.386398 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 1645329 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_hits 1362201 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_miss_latency 15269849238 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066491 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses 283128 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050385997 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9304.837348 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles_no_targets 16250 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_refs 9.224078 # Average number of references to valid blocks.
+system.cpu0.dcache.blocked_no_mshrs 116353 # number of cycles access was blocked
+system.cpu0.dcache.blocked_no_targets 2 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_mshrs 1082645740 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_targets 32500 # number of cycles access was blocked
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.demand_accesses 10672459 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 41595.993394 # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits 8080450 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 107817189240 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate 0.242869 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 2592009 # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits 1613196 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency 35248020738 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate 0.091714 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses 978813 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.overall_accesses 10672459 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 41595.993394 # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.985488 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_hits 8080450 # number of overall hits
+system.cpu0.dcache.overall_miss_latency 107817189240 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate 0.242869 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 2592009 # number of overall misses
+system.cpu0.dcache.overall_mshr_hits 1613196 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency 35248020738 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate 0.091714 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses 978813 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency 1690255497 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.dcache.replacements 922698 # number of replacements
+system.cpu0.dcache.sampled_refs 923094 # Sample count of references to valid blocks.
+system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.tagsinuse 442.177178 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 8514691 # Total number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.writebacks 297324 # number of writebacks
+system.cpu0.decode.DECODE:BlockedCycles 33637373 # Number of cycles decode is blocked
+system.cpu0.decode.DECODE:BranchMispred 26509 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DECODE:BranchResolved 401334 # Number of times decode resolved a branch
+system.cpu0.decode.DECODE:DecodedInsts 50924220 # Number of instructions handled by decode
+system.cpu0.decode.DECODE:IdleCycles 25725806 # Number of cycles decode is idle
+system.cpu0.decode.DECODE:RunCycles 9142179 # Number of cycles decode is running
+system.cpu0.decode.DECODE:SquashCycles 1093475 # Number of cycles decode is squashing
+system.cpu0.decode.DECODE:SquashedInsts 84178 # Number of squashed instructions handled by decode
+system.cpu0.decode.DECODE:UnblockCycles 924162 # Number of cycles decode is unblocking
+system.cpu0.dtb.accesses 812630 # DTB accesses
+system.cpu0.dtb.acv 800 # DTB access violations
+system.cpu0.dtb.hits 11624529 # DTB hits
+system.cpu0.dtb.misses 28502 # DTB misses
+system.cpu0.dtb.read_accesses 605275 # DTB read accesses
+system.cpu0.dtb.read_acv 596 # DTB read access violations
+system.cpu0.dtb.read_hits 7062851 # DTB read hits
+system.cpu0.dtb.read_misses 24043 # DTB read misses
+system.cpu0.dtb.write_accesses 207355 # DTB write accesses
+system.cpu0.dtb.write_acv 204 # DTB write access violations
+system.cpu0.dtb.write_hits 4561678 # DTB write hits
+system.cpu0.dtb.write_misses 4459 # DTB write misses
+system.cpu0.fetch.Branches 10092697 # Number of branches that fetch encountered
+system.cpu0.fetch.CacheLines 6456334 # Number of cache lines fetched
+system.cpu0.fetch.Cycles 16708506 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.IcacheSquashes 292498 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.Insts 51999783 # Number of instructions fetch has processed
+system.cpu0.fetch.MiscStallCycles 404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.SquashCycles 660089 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.branchRate 0.100026 # Number of branch fetches per cycle
+system.cpu0.fetch.icacheStallCycles 6456334 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.predictedBranches 5665140 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.rate 0.515355 # Number of inst fetches per cycle
+system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist.samples 70522996
+system.cpu0.fetch.rateDist.min_value 0
+ 0 60301622 8550.63%
+ 1 760699 107.87%
+ 2 1434176 203.36%
+ 3 635243 90.08%
+ 4 2330465 330.45%
+ 5 474381 67.27%
+ 6 552250 78.31%
+ 7 815542 115.64%
+ 8 3218618 456.39%
+system.cpu0.fetch.rateDist.max_value 8
+system.cpu0.fetch.rateDist.end_dist
+
+system.cpu0.icache.ReadReq_accesses 6456334 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency 15194.690740 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.490595 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits 5806036 # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency 9881076999 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate 0.100722 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses 650298 # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_hits 29862 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_miss_latency 7526813499 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate 0.096097 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_misses 620436 # number of ReadReq MSHR misses
+system.cpu0.icache.avg_blocked_cycles_no_mshrs 11557.114286 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu0.icache.avg_refs 9.359502 # Average number of references to valid blocks.
+system.cpu0.icache.blocked_no_mshrs 35 # number of cycles access was blocked
+system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles_no_mshrs 404499 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.demand_accesses 6456334 # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 15194.690740 # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency
+system.cpu0.icache.demand_hits 5806036 # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency 9881076999 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate 0.100722 # miss rate for demand accesses
+system.cpu0.icache.demand_misses 650298 # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits 29862 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency 7526813499 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate 0.096097 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses 620436 # number of demand (read+write) MSHR misses
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.icache.overall_accesses 6456334 # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 15194.690740 # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 12131.490595 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu0.icache.overall_hits 5806036 # number of overall hits
+system.cpu0.icache.overall_miss_latency 9881076999 # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate 0.100722 # miss rate for overall accesses
+system.cpu0.icache.overall_misses 650298 # number of overall misses
+system.cpu0.icache.overall_mshr_hits 29862 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency 7526813499 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate 0.096097 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses 620436 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.icache.replacements 619824 # number of replacements
+system.cpu0.icache.sampled_refs 620336 # Sample count of references to valid blocks.
+system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.tagsinuse 509.829045 # Cycle average of tags in use
+system.cpu0.icache.total_refs 5806036 # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.writebacks 0 # number of writebacks
+system.cpu0.idleCycles 30377936 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.iew.EXEC:branches 6436145 # Number of branches executed
+system.cpu0.iew.EXEC:nop 2512619 # number of nop insts executed
+system.cpu0.iew.EXEC:rate 0.402630 # Inst execution rate
+system.cpu0.iew.EXEC:refs 11739664 # number of memory reference insts executed
+system.cpu0.iew.EXEC:stores 4575851 # Number of stores executed
+system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu0.iew.WB:consumers 24160254 # num instructions consuming a value
+system.cpu0.iew.WB:count 40224289 # cumulative count of insts written-back
+system.cpu0.iew.WB:fanout 0.779043 # average fanout of values written-back
+system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu0.iew.WB:producers 18821888 # num instructions producing a value
+system.cpu0.iew.WB:rate 0.398651 # insts written-back per cycle
+system.cpu0.iew.WB:sent 40292052 # cumulative count of insts sent to commit
+system.cpu0.iew.branchMispredicts 568729 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewBlockCycles 7177517 # Number of cycles IEW is blocking
+system.cpu0.iew.iewDispLoadInsts 7552776 # Number of dispatched load instructions
+system.cpu0.iew.iewDispNonSpecInsts 1229726 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewDispSquashedInsts 771663 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispStoreInsts 4835977 # Number of dispatched store instructions
+system.cpu0.iew.iewDispatchedInsts 46188038 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewExecLoadInsts 7163813 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 359179 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewExecutedInsts 40625745 # Number of executed instructions
+system.cpu0.iew.iewIQFullEvents 33838 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu0.iew.iewLSQFullEvents 4189 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles 1093475 # Number of cycles IEW is squashing
+system.cpu0.iew.iewUnblockCycles 453457 # Number of cycles IEW is unblocking
+system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu0.iew.lsq.thread.0.cacheBlocked 242605 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread.0.forwLoads 357762 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread.0.ignoredResponses 8885 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu0.iew.lsq.thread.0.memOrderViolation 33999 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread.0.rescheduledLoads 12233 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread.0.squashedLoads 1148209 # Number of loads squashed
+system.cpu0.iew.lsq.thread.0.squashedStores 408737 # Number of stores squashed
+system.cpu0.iew.memOrderViolationEvents 33999 # Number of memory order violations
+system.cpu0.iew.predictedNotTakenIncorrect 255829 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect 312900 # Number of branches that were predicted taken incorrectly
+system.cpu0.ipc 0.373250 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.373250 # IPC: Total IPC of All Threads
+system.cpu0.iq.ISSUE:FU_type_0 40984924 # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 3324 0.01% # Type of FU issued
+ IntAlu 28266314 68.97% # Type of FU issued
+ IntMult 42210 0.10% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 12073 0.03% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 1656 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 7397265 18.05% # Type of FU issued
+ MemWrite 4611960 11.25% # Type of FU issued
+ IprAccess 650122 1.59% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0.end_dist
+system.cpu0.iq.ISSUE:fu_busy_cnt 290360 # FU busy when requested
+system.cpu0.iq.ISSUE:fu_busy_rate 0.007085 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 33477 11.53% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 185557 63.91% # attempts to use FU when none available
+ MemWrite 71326 24.56% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full.end_dist
+system.cpu0.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle.samples 70522996
+system.cpu0.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 49763845 7056.40%
+ 1 10504305 1489.49%
+ 2 4625788 655.93%
+ 3 2839071 402.57%
+ 4 1729907 245.30%
+ 5 663571 94.09%
+ 6 315326 44.71%
+ 7 67073 9.51%
+ 8 14110 2.00%
+system.cpu0.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu0.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu0.iq.ISSUE:rate 0.406190 # Inst issue rate
+system.cpu0.iq.iqInstsAdded 42277563 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqInstsIssued 40984924 # Number of instructions issued
+system.cpu0.iq.iqNonSpecInstsAdded 1397856 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqSquashedInstsExamined 5734915 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsIssued 23390 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedNonSpecRemoved 939445 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.iqSquashedOperandsExamined 3057501 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.itb.accesses 875611 # ITB accesses
+system.cpu0.itb.acv 895 # ITB acv
+system.cpu0.itb.hits 845707 # ITB hits
+system.cpu0.itb.misses 29904 # ITB misses
+system.cpu0.kern.callpal 129595 # number of callpals executed
+system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu0.kern.callpal_wripir 96 0.07% 0.07% # number of callpals executed
+system.cpu0.kern.callpal_wrmces 1 0.00% 0.08% # number of callpals executed
+system.cpu0.kern.callpal_wrfen 1 0.00% 0.08% # number of callpals executed
+system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.08% # number of callpals executed
+system.cpu0.kern.callpal_swpctx 2410 1.86% 1.94% # number of callpals executed
+system.cpu0.kern.callpal_tbi 51 0.04% 1.98% # number of callpals executed
+system.cpu0.kern.callpal_wrent 7 0.01% 1.98% # number of callpals executed
+system.cpu0.kern.callpal_swpipl 116022 89.53% 91.51% # number of callpals executed
+system.cpu0.kern.callpal_rdps 6357 4.91% 96.41% # number of callpals executed
+system.cpu0.kern.callpal_wrkgp 1 0.00% 96.41% # number of callpals executed
+system.cpu0.kern.callpal_wrusp 3 0.00% 96.42% # number of callpals executed
+system.cpu0.kern.callpal_rdusp 9 0.01% 96.42% # number of callpals executed
+system.cpu0.kern.callpal_whami 2 0.00% 96.43% # number of callpals executed
+system.cpu0.kern.callpal_rti 4116 3.18% 99.60% # number of callpals executed
+system.cpu0.kern.callpal_callsys 381 0.29% 99.90% # number of callpals executed
+system.cpu0.kern.callpal_imb 136 0.10% 100.00% # number of callpals executed
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.hwrei 144434 # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce 4855 # number of quiesce instructions executed
+system.cpu0.kern.ipl_count 122325 # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0 47769 39.05% 39.05% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21 239 0.20% 39.25% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_22 1931 1.58% 40.82% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_30 17 0.01% 40.84% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31 72369 59.16% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good 96409 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0 47119 48.87% 48.87% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_21 239 0.25% 49.12% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_22 1931 2.00% 51.12% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31 47103 48.86% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks 1907288705500 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0 1871607298000 98.13% 98.13% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21 101503500 0.01% 98.13% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22 397998500 0.02% 98.16% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30 9331000 0.00% 98.16% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31 35172574500 1.84% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used_0 0.986393 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_31 0.650873 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel 1284
+system.cpu0.kern.mode_good_user 1284
+system.cpu0.kern.mode_good_idle 0
+system.cpu0.kern.mode_switch_kernel 5894 # number of protection mode switches
+system.cpu0.kern.mode_switch_user 1284 # number of protection mode switches
+system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches
+system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel 0.217849 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks_kernel 1905144241000 99.89% 99.89% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user 2121161500 0.11% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context 2411 # number of times the context was actually changed
+system.cpu0.kern.syscall 222 # number of syscalls executed
+system.cpu0.kern.syscall_2 8 3.60% 3.60% # number of syscalls executed
+system.cpu0.kern.syscall_3 19 8.56% 12.16% # number of syscalls executed
+system.cpu0.kern.syscall_4 4 1.80% 13.96% # number of syscalls executed
+system.cpu0.kern.syscall_6 32 14.41% 28.38% # number of syscalls executed
+system.cpu0.kern.syscall_12 1 0.45% 28.83% # number of syscalls executed
+system.cpu0.kern.syscall_17 9 4.05% 32.88% # number of syscalls executed
+system.cpu0.kern.syscall_19 10 4.50% 37.39% # number of syscalls executed
+system.cpu0.kern.syscall_20 6 2.70% 40.09% # number of syscalls executed
+system.cpu0.kern.syscall_23 1 0.45% 40.54% # number of syscalls executed
+system.cpu0.kern.syscall_24 3 1.35% 41.89% # number of syscalls executed
+system.cpu0.kern.syscall_33 7 3.15% 45.05% # number of syscalls executed
+system.cpu0.kern.syscall_41 2 0.90% 45.95% # number of syscalls executed
+system.cpu0.kern.syscall_45 36 16.22% 62.16% # number of syscalls executed
+system.cpu0.kern.syscall_47 3 1.35% 63.51% # number of syscalls executed
+system.cpu0.kern.syscall_48 10 4.50% 68.02% # number of syscalls executed
+system.cpu0.kern.syscall_54 10 4.50% 72.52% # number of syscalls executed
+system.cpu0.kern.syscall_58 1 0.45% 72.97% # number of syscalls executed
+system.cpu0.kern.syscall_59 6 2.70% 75.68% # number of syscalls executed
+system.cpu0.kern.syscall_71 23 10.36% 86.04% # number of syscalls executed
+system.cpu0.kern.syscall_73 3 1.35% 87.39% # number of syscalls executed
+system.cpu0.kern.syscall_74 6 2.70% 90.09% # number of syscalls executed
+system.cpu0.kern.syscall_87 1 0.45% 90.54% # number of syscalls executed
+system.cpu0.kern.syscall_90 3 1.35% 91.89% # number of syscalls executed
+system.cpu0.kern.syscall_92 9 4.05% 95.95% # number of syscalls executed
+system.cpu0.kern.syscall_97 2 0.90% 96.85% # number of syscalls executed
+system.cpu0.kern.syscall_98 2 0.90% 97.75% # number of syscalls executed
+system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed
+system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed
+system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed
+system.cpu0.numCycles 100900932 # number of cpu cycles simulated
+system.cpu0.rename.RENAME:BlockCycles 10626974 # Number of cycles rename is blocking
+system.cpu0.rename.RENAME:CommittedMaps 27338376 # Number of HB maps that are committed
+system.cpu0.rename.RENAME:IQFullEvents 742955 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.RENAME:IdleCycles 26930007 # Number of cycles rename is idle
+system.cpu0.rename.RENAME:LSQFullEvents 1646671 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RENAME:ROBFullEvents 16625 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.RENAME:RenameLookups 58873396 # Number of register rename lookups that rename has made
+system.cpu0.rename.RENAME:RenamedInsts 48153710 # Number of instructions processed by rename
+system.cpu0.rename.RENAME:RenamedOperands 32532330 # Number of destination operands rename has renamed
+system.cpu0.rename.RENAME:RunCycles 9103233 # Number of cycles rename is running
+system.cpu0.rename.RENAME:SquashCycles 1093475 # Number of cycles rename is squashing
+system.cpu0.rename.RENAME:UnblockCycles 3612957 # Number of cycles rename is unblocking
+system.cpu0.rename.RENAME:UndoneMaps 5193954 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.RENAME:serializeStallCycles 19156348 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RENAME:serializingInsts 1163476 # count of serializing insts renamed
+system.cpu0.rename.RENAME:skidInsts 8536447 # count of insts added to the skid buffer
+system.cpu0.rename.RENAME:tempSerializingInsts 181426 # count of temporary serializing insts renamed
+system.cpu0.timesIdled 904874 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.commit.COM:branches 2941268 # Number of branches committed
+system.cpu1.commit.COM:bw_lim_events 404281 # number cycles where commit BW limit reached
+system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu1.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle.samples 37417436
+system.cpu1.commit.COM:committed_per_cycle.min_value 0
+ 0 29372797 7850.03%
+ 1 3570649 954.27%
+ 2 1730450 462.47%
+ 3 1048421 280.20%
+ 4 705992 188.68%
+ 5 261184 69.80%
+ 6 182468 48.77%
+ 7 141194 37.73%
+ 8 404281 108.05%
+system.cpu1.commit.COM:committed_per_cycle.max_value 8
+system.cpu1.commit.COM:committed_per_cycle.end_dist
+
+system.cpu1.commit.COM:count 19624114 # Number of instructions committed
+system.cpu1.commit.COM:loads 3545101 # Number of loads committed
+system.cpu1.commit.COM:membars 87127 # Number of memory barriers committed
+system.cpu1.commit.COM:refs 5853378 # Number of memory references committed
+system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu1.commit.branchMispredicts 311146 # The number of times a branch was mispredicted
+system.cpu1.commit.commitCommittedInsts 19624114 # The number of committed instructions
+system.cpu1.commit.commitNonSpecStalls 255253 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.commitSquashedInsts 3733069 # The number of squashed insts skipped by commit
+system.cpu1.committedInsts 18492763 # Number of Instructions Simulated
+system.cpu1.committedInsts_total 18492763 # Number of Instructions Simulated
+system.cpu1.cpi 2.312237 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 2.312237 # CPI: Total CPI of All Threads
+system.cpu1.dcache.LoadLockedReq_accesses 72124 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency 14446.929646 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11200.613079 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits 59829 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency 177625000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate 0.170470 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses 12295 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_hits 2019 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115097500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.142477 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_misses 10276 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses 3584183 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency 15544.189729 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11996.806998 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_hits 2941941 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency 9983131500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate 0.179188 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses 642242 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_hits 211143 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_miss_latency 5171811500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate 0.120278 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_misses 431099 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 283603500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.StoreCondReq_accesses 68163 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency 54675.738585 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51675.738585 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits 51408 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency 916092000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate 0.245808 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses 16755 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865827000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245808 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_misses 16755 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses 2232793 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency 49361.665892 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54248.260288 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_hits 1538625 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency 34265288889 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate 0.310897 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses 694168 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_hits 551549 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_miss_latency 7736832634 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063875 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_misses 142619 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 511356000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.avg_blocked_cycles_no_mshrs 14029.367204 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles_no_targets 5000 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_refs 8.864535 # Average number of references to valid blocks.
+system.cpu1.dcache.blocked_no_mshrs 31315 # number of cycles access was blocked
+system.cpu1.dcache.blocked_no_targets 1 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles_no_mshrs 439329634 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles_no_targets 5000 # number of cycles access was blocked
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.demand_accesses 5816976 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 33109.914165 # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency
+system.cpu1.dcache.demand_hits 4480566 # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency 44248420389 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate 0.229743 # miss rate for demand accesses
+system.cpu1.dcache.demand_misses 1336410 # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits 762692 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency 12908644134 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate 0.098628 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses 573718 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.overall_accesses 5816976 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 33109.914165 # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 22499.981060 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_hits 4480566 # number of overall hits
+system.cpu1.dcache.overall_miss_latency 44248420389 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate 0.229743 # miss rate for overall accesses
+system.cpu1.dcache.overall_misses 1336410 # number of overall misses
+system.cpu1.dcache.overall_mshr_hits 762692 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency 12908644134 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate 0.098628 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses 573718 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency 794959500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.dcache.replacements 531824 # number of replacements
+system.cpu1.dcache.sampled_refs 532336 # Sample count of references to valid blocks.
+system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.tagsinuse 486.799078 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 4718911 # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 39405721000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks 158256 # number of writebacks
+system.cpu1.decode.DECODE:BlockedCycles 17763598 # Number of cycles decode is blocked
+system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DECODE:BranchResolved 245215 # Number of times decode resolved a branch
+system.cpu1.decode.DECODE:DecodedInsts 26209907 # Number of instructions handled by decode
+system.cpu1.decode.DECODE:IdleCycles 14707752 # Number of cycles decode is idle
+system.cpu1.decode.DECODE:RunCycles 4714008 # Number of cycles decode is running
+system.cpu1.decode.DECODE:SquashCycles 641031 # Number of cycles decode is squashing
+system.cpu1.decode.DECODE:SquashedInsts 52760 # Number of squashed instructions handled by decode
+system.cpu1.decode.DECODE:UnblockCycles 232077 # Number of cycles decode is unblocking
+system.cpu1.dtb.accesses 434054 # DTB accesses
+system.cpu1.dtb.acv 76 # DTB access violations
+system.cpu1.dtb.hits 6272530 # DTB hits
+system.cpu1.dtb.misses 17149 # DTB misses
+system.cpu1.dtb.read_accesses 314239 # DTB read accesses
+system.cpu1.dtb.read_acv 13 # DTB read access violations
+system.cpu1.dtb.read_hits 3866975 # DTB read hits
+system.cpu1.dtb.read_misses 13433 # DTB read misses
+system.cpu1.dtb.write_accesses 119815 # DTB write accesses
+system.cpu1.dtb.write_acv 63 # DTB write access violations
+system.cpu1.dtb.write_hits 2405555 # DTB write hits
+system.cpu1.dtb.write_misses 3716 # DTB write misses
+system.cpu1.fetch.Branches 5530798 # Number of branches that fetch encountered
+system.cpu1.fetch.CacheLines 3081765 # Number of cache lines fetched
+system.cpu1.fetch.Cycles 8119333 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.IcacheSquashes 192779 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.Insts 26783088 # Number of instructions fetch has processed
+system.cpu1.fetch.MiscStallCycles 1141 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.SquashCycles 373445 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.branchRate 0.129346 # Number of branch fetches per cycle
+system.cpu1.fetch.icacheStallCycles 3081765 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.predictedBranches 2679042 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.rate 0.626364 # Number of inst fetches per cycle
+system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist.samples 38058467
+system.cpu1.fetch.rateDist.min_value 0
+ 0 33027824 8678.18%
+ 1 336540 88.43%
+ 2 683303 179.54%
+ 3 398795 104.78%
+ 4 792602 208.26%
+ 5 252574 66.36%
+ 6 340311 89.42%
+ 7 403731 106.08%
+ 8 1822787 478.94%
+system.cpu1.fetch.rateDist.max_value 8
+system.cpu1.fetch.rateDist.end_dist
+
+system.cpu1.icache.ReadReq_accesses 3081765 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency 14557.235908 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11605.244559 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits 2613676 # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency 6814081999 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate 0.151890 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses 468089 # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_hits 20978 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_miss_latency 5188832500 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate 0.145083 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_misses 447111 # number of ReadReq MSHR misses
+system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu1.icache.avg_refs 5.846378 # Average number of references to valid blocks.
+system.cpu1.icache.blocked_no_mshrs 26 # number of cycles access was blocked
+system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles_no_mshrs 287500 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.demand_accesses 3081765 # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 14557.235908 # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency
+system.cpu1.icache.demand_hits 2613676 # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency 6814081999 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate 0.151890 # miss rate for demand accesses
+system.cpu1.icache.demand_misses 468089 # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits 20978 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency 5188832500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate 0.145083 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses 447111 # number of demand (read+write) MSHR misses
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.overall_accesses 3081765 # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 14557.235908 # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11605.244559 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu1.icache.overall_hits 2613676 # number of overall hits
+system.cpu1.icache.overall_miss_latency 6814081999 # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate 0.151890 # miss rate for overall accesses
+system.cpu1.icache.overall_misses 468089 # number of overall misses
+system.cpu1.icache.overall_mshr_hits 20978 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency 5188832500 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate 0.145083 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses 447111 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.icache.replacements 446548 # number of replacements
+system.cpu1.icache.sampled_refs 447059 # Sample count of references to valid blocks.
+system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.tagsinuse 504.476146 # Cycle average of tags in use
+system.cpu1.icache.total_refs 2613676 # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.writebacks 0 # number of writebacks
+system.cpu1.idleCycles 4701182 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.iew.EXEC:branches 3208895 # Number of branches executed
+system.cpu1.iew.EXEC:nop 1313637 # number of nop insts executed
+system.cpu1.iew.EXEC:rate 0.474750 # Inst execution rate
+system.cpu1.iew.EXEC:refs 6445371 # number of memory reference insts executed
+system.cpu1.iew.EXEC:stores 2416978 # Number of stores executed
+system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu1.iew.WB:consumers 12350061 # num instructions consuming a value
+system.cpu1.iew.WB:count 20043548 # cumulative count of insts written-back
+system.cpu1.iew.WB:fanout 0.731488 # average fanout of values written-back
+system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu1.iew.WB:producers 9033918 # num instructions producing a value
+system.cpu1.iew.WB:rate 0.468749 # insts written-back per cycle
+system.cpu1.iew.WB:sent 20085855 # cumulative count of insts sent to commit
+system.cpu1.iew.branchMispredicts 338994 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewBlockCycles 2476901 # Number of cycles IEW is blocking
+system.cpu1.iew.iewDispLoadInsts 4240735 # Number of dispatched load instructions
+system.cpu1.iew.iewDispNonSpecInsts 782170 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewDispSquashedInsts 352959 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispStoreInsts 2555030 # Number of dispatched store instructions
+system.cpu1.iew.iewDispatchedInsts 23433163 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewExecLoadInsts 4028393 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 227109 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewExecutedInsts 20300122 # Number of executed instructions
+system.cpu1.iew.iewIQFullEvents 13056 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu1.iew.iewLSQFullEvents 2312 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles 641031 # Number of cycles IEW is squashing
+system.cpu1.iew.iewUnblockCycles 92389 # Number of cycles IEW is unblocking
+system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu1.iew.lsq.thread.0.cacheBlocked 96439 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread.0.forwLoads 136590 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread.0.ignoredResponses 5874 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu1.iew.lsq.thread.0.memOrderViolation 18177 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread.0.rescheduledLoads 7528 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread.0.squashedLoads 695634 # Number of loads squashed
+system.cpu1.iew.lsq.thread.0.squashedStores 246753 # Number of stores squashed
+system.cpu1.iew.memOrderViolationEvents 18177 # Number of memory order violations
+system.cpu1.iew.predictedNotTakenIncorrect 160429 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.predictedTakenIncorrect 178565 # Number of branches that were predicted taken incorrectly
+system.cpu1.ipc 0.432482 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.432482 # IPC: Total IPC of All Threads
+system.cpu1.iq.ISSUE:FU_type_0 20527233 # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 3984 0.02% # Type of FU issued
+ IntAlu 13446211 65.50% # Type of FU issued
+ IntMult 28837 0.14% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 13702 0.07% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 1986 0.01% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 4170434 20.32% # Type of FU issued
+ MemWrite 2440876 11.89% # Type of FU issued
+ IprAccess 421203 2.05% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0.end_dist
+system.cpu1.iq.ISSUE:fu_busy_cnt 220615 # FU busy when requested
+system.cpu1.iq.ISSUE:fu_busy_rate 0.010747 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 16051 7.28% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 131548 59.63% # attempts to use FU when none available
+ MemWrite 73016 33.10% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full.end_dist
+system.cpu1.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle.samples 38058467
+system.cpu1.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 28368882 7454.03%
+ 1 4650018 1221.81%
+ 2 1988549 522.50%
+ 3 1356758 356.49%
+ 4 973103 255.69%
+ 5 468416 123.08%
+ 6 186236 48.93%
+ 7 54105 14.22%
+ 8 12400 3.26%
+system.cpu1.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu1.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu1.iq.ISSUE:rate 0.480061 # Inst issue rate
+system.cpu1.iq.iqInstsAdded 21243619 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqInstsIssued 20527233 # Number of instructions issued
+system.cpu1.iq.iqNonSpecInstsAdded 875907 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqSquashedInstsExamined 3479594 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsIssued 16597 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedNonSpecRemoved 620654 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.iqSquashedOperandsExamined 1771927 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.itb.accesses 525300 # ITB accesses
+system.cpu1.itb.acv 103 # ITB acv
+system.cpu1.itb.hits 518475 # ITB hits
+system.cpu1.itb.misses 6825 # ITB misses
+system.cpu1.kern.callpal 87347 # number of callpals executed
+system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu1.kern.callpal_wripir 17 0.02% 0.02% # number of callpals executed
+system.cpu1.kern.callpal_wrmces 1 0.00% 0.02% # number of callpals executed
+system.cpu1.kern.callpal_wrfen 1 0.00% 0.02% # number of callpals executed
+system.cpu1.kern.callpal_swpctx 1838 2.10% 2.13% # number of callpals executed
+system.cpu1.kern.callpal_tbi 3 0.00% 2.13% # number of callpals executed
+system.cpu1.kern.callpal_wrent 7 0.01% 2.14% # number of callpals executed
+system.cpu1.kern.callpal_swpipl 79676 91.22% 93.36% # number of callpals executed
+system.cpu1.kern.callpal_rdps 2408 2.76% 96.11% # number of callpals executed
+system.cpu1.kern.callpal_wrkgp 1 0.00% 96.11% # number of callpals executed
+system.cpu1.kern.callpal_wrusp 4 0.00% 96.12% # number of callpals executed
+system.cpu1.kern.callpal_whami 3 0.00% 96.12% # number of callpals executed
+system.cpu1.kern.callpal_rti 3206 3.67% 99.79% # number of callpals executed
+system.cpu1.kern.callpal_callsys 136 0.16% 99.95% # number of callpals executed
+system.cpu1.kern.callpal_imb 44 0.05% 100.00% # number of callpals executed
+system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.hwrei 93957 # number of hwrei instructions executed
+system.cpu1.kern.inst.quiesce 3692 # number of quiesce instructions executed
+system.cpu1.kern.ipl_count 84907 # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0 34137 40.21% 40.21% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_22 1928 2.27% 42.48% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_30 96 0.11% 42.59% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31 48746 57.41% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good 68748 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0 33410 48.60% 48.60% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22 1928 2.80% 51.40% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31 33314 48.46% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks 1907704497000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0 1872145700000 98.14% 98.14% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22 351989500 0.02% 98.15% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30 39998500 0.00% 98.16% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31 35166809000 1.84% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used_0 0.978703 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_31 0.683420 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel 521
+system.cpu1.kern.mode_good_user 463
+system.cpu1.kern.mode_good_idle 58
+system.cpu1.kern.mode_switch_kernel 2303 # number of protection mode switches
+system.cpu1.kern.mode_switch_user 463 # number of protection mode switches
+system.cpu1.kern.mode_switch_idle 2035 # number of protection mode switches
+system.cpu1.kern.mode_switch_good 1.254728 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel 0.226227 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_idle 0.028501 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel 46596073500 2.44% 2.44% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user 1015566000 0.05% 2.50% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle 1860092849500 97.50% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 1839 # number of times the context was actually changed
+system.cpu1.kern.syscall 104 # number of syscalls executed
+system.cpu1.kern.syscall_3 11 10.58% 10.58% # number of syscalls executed
+system.cpu1.kern.syscall_6 10 9.62% 20.19% # number of syscalls executed
+system.cpu1.kern.syscall_15 1 0.96% 21.15% # number of syscalls executed
+system.cpu1.kern.syscall_17 6 5.77% 26.92% # number of syscalls executed
+system.cpu1.kern.syscall_23 3 2.88% 29.81% # number of syscalls executed
+system.cpu1.kern.syscall_24 3 2.88% 32.69% # number of syscalls executed
+system.cpu1.kern.syscall_33 4 3.85% 36.54% # number of syscalls executed
+system.cpu1.kern.syscall_45 18 17.31% 53.85% # number of syscalls executed
+system.cpu1.kern.syscall_47 3 2.88% 56.73% # number of syscalls executed
+system.cpu1.kern.syscall_59 1 0.96% 57.69% # number of syscalls executed
+system.cpu1.kern.syscall_71 31 29.81% 87.50% # number of syscalls executed
+system.cpu1.kern.syscall_74 10 9.62% 97.12% # number of syscalls executed
+system.cpu1.kern.syscall_132 3 2.88% 100.00% # number of syscalls executed
+system.cpu1.numCycles 42759649 # number of cpu cycles simulated
+system.cpu1.rename.RENAME:BlockCycles 3630480 # Number of cycles rename is blocking
+system.cpu1.rename.RENAME:CommittedMaps 13162138 # Number of HB maps that are committed
+system.cpu1.rename.RENAME:IQFullEvents 331495 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.RENAME:IdleCycles 15176071 # Number of cycles rename is idle
+system.cpu1.rename.RENAME:LSQFullEvents 648663 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RENAME:ROBFullEvents 1231 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.RENAME:RenameLookups 29369210 # Number of register rename lookups that rename has made
+system.cpu1.rename.RENAME:RenamedInsts 24481625 # Number of instructions processed by rename
+system.cpu1.rename.RENAME:RenamedOperands 16150176 # Number of destination operands rename has renamed
+system.cpu1.rename.RENAME:RunCycles 4323376 # Number of cycles rename is running
+system.cpu1.rename.RENAME:SquashCycles 641031 # Number of cycles rename is squashing
+system.cpu1.rename.RENAME:UnblockCycles 1811966 # Number of cycles rename is unblocking
+system.cpu1.rename.RENAME:UndoneMaps 2988036 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.RENAME:serializeStallCycles 12475541 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RENAME:serializingInsts 728332 # count of serializing insts renamed
+system.cpu1.rename.RENAME:skidInsts 4962004 # count of insts added to the skid buffer
+system.cpu1.rename.RENAME:tempSerializingInsts 86297 # count of temporary serializing insts renamed
+system.cpu1.timesIdled 480244 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
+system.disk0.dma_write_txs 395 # Number of DMA write transactions.
+system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_avg_miss_latency 115245.702857 # average ReadReq miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 63245.702857 # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency 20167998 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses 175 # number of ReadReq misses
+system.iocache.ReadReq_mshr_miss_latency 11067998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses
+system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_avg_miss_latency 137815.912736 # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85812.468906 # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency 5726526806 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses 41552 # number of WriteReq misses
+system.iocache.WriteReq_mshr_miss_latency 3565679708 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
+system.iocache.avg_blocked_cycles_no_mshrs 6166.359533 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.iocache.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs 10458 # number of cycles access was blocked
+system.iocache.blocked_no_targets 0 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs 64487788 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.demand_accesses 41727 # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency 137721.254919 # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency
+system.iocache.demand_hits 0 # number of demand (read+write) hits
+system.iocache.demand_miss_latency 5746694804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate 1 # miss rate for demand accesses
+system.iocache.demand_misses 41727 # number of demand (read+write) misses
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency 3576747706 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.overall_accesses 41727 # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency 137721.254919 # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 85717.825533 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.iocache.overall_hits 0 # number of overall hits
+system.iocache.overall_miss_latency 5746694804 # number of overall miss cycles
+system.iocache.overall_miss_rate 1 # miss rate for overall accesses
+system.iocache.overall_misses 41727 # number of overall misses
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency 3576747706 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements 41697 # number of replacements
+system.iocache.sampled_refs 41713 # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse 0.387818 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.warmup_cycle 1717170509000 # Cycle when the warmup percentage was hit.
+system.iocache.writebacks 41522 # number of writebacks
+system.l2c.ReadExReq_accesses 317495 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 52375.723397 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40223.099381 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 16629030300 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 317495 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 12770632938 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 317495 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 2204283 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 52067.320767 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40026.416785 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits 1893933 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 16159093000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.140794 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 310350 # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency 12421518000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.140786 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 310333 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 827055500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses 141956 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 51067.196822 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.595903 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 7249294992 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 141956 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 5691526500 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 141956 # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency 1410123998 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses 455580 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 455580 # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_refs 4.836093 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.demand_accesses 2521778 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 52223.276923 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency
+system.l2c.demand_hits 1893933 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 32788123300 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.248969 # miss rate for demand accesses
+system.l2c.demand_misses 627845 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 25192150938 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.248962 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 627828 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.overall_accesses 2521778 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 52223.276923 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40125.879919 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.overall_hits 1893933 # number of overall hits
+system.l2c.overall_miss_latency 32788123300 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.248969 # miss rate for overall accesses
+system.l2c.overall_misses 627845 # number of overall misses
+system.l2c.overall_mshr_hits 17 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 25192150938 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.248962 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 627828 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 2237179498 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements 402113 # number of replacements
+system.l2c.sampled_refs 433643 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 31146.703960 # Cycle average of tags in use
+system.l2c.total_refs 2097138 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 124275 # number of writebacks
+system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: 125740500: Trying to launch CPU number 1!
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:30:58
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:35:52
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1907705350500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 6932487 # Number of BTB hits
-global.BPredUnit.BTBLookups 13324936 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 41495 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 828381 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted
-global.BPredUnit.lookups 14559443 # Number of BP lookups
-global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target.
-host_inst_rate 123231 # Simulator instruction rate (inst/s)
-host_mem_usage 290820 # Number of bytes of host memory used
-host_seconds 430.51 # Real time elapsed on the host
-host_tick_rate 4337505567 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 7011041 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 53052618 # Number of instructions simulated
-sim_seconds 1.867359 # Number of seconds simulated
-sim_ticks 1867358550500 # Number of ticks simulated
-system.cpu.commit.COM:branches 8455188 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 973838 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 100543308
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 76317924 7590.55%
- 1 10743540 1068.55%
- 2 5987880 595.55%
- 3 2987787 297.16%
- 4 2072579 206.14%
- 5 671161 66.75%
- 6 395328 39.32%
- 7 393271 39.11%
- 8 973838 96.86%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 56244351 # Number of instructions committed
-system.cpu.commit.COM:loads 9302477 # Number of loads committed
-system.cpu.commit.COM:membars 227741 # Number of memory barriers committed
-system.cpu.commit.COM:refs 15692393 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 786910 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 56244351 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 667224 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 9485751 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 53052618 # Number of Instructions Simulated
-system.cpu.committedInsts_total 53052618 # Number of Instructions Simulated
-system.cpu.cpi 2.580282 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.580282 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 214227 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 15534.014065 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11815.523733 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits 192045 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 344575500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate 0.103544 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses 22182 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits 4654 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207102500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081820 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 17528 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses 9334533 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 23887.280277 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.210749 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits 7801638 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 36616692500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.164218 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1532895 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 448100 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 24694502000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.116213 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1084795 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 889982500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses 219741 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.938098 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.938098 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits 189758 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_latency 1689000500 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_rate 0.136447 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses 29983 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599051500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136447 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_misses 29983 # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6155139 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 49031.922002 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.269570 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits 3924727 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 109361387216 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.362366 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2230412 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1833469 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 21630324960 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.064490 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 396943 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1220847997 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.541558 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 11500 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 8.820405 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 138181 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 1383128462 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 23000 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 15489672 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 38789.840881 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 11726365 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 145978079716 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.242956 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 3763307 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2281569 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 46324826960 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.095660 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1481738 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 15489672 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 38789.840881 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 11726365 # number of overall hits
-system.cpu.dcache.overall_miss_latency 145978079716 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.242956 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 3763307 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2281569 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 46324826960 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.095660 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1481738 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 2110830497 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 1402096 # number of replacements
-system.cpu.dcache.sampled_refs 1402608 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.995429 # Cycle average of tags in use
-system.cpu.dcache.total_refs 12371571 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 430429 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 48380829 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 42524 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 612955 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 72702474 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 37949237 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 13063267 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1645972 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 134798 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 1149974 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 1229941 # DTB accesses
-system.cpu.dtb.acv 828 # DTB access violations
-system.cpu.dtb.hits 16757791 # DTB hits
-system.cpu.dtb.misses 44378 # DTB misses
-system.cpu.dtb.read_accesses 908364 # DTB read accesses
-system.cpu.dtb.read_acv 587 # DTB read access violations
-system.cpu.dtb.read_hits 10166755 # DTB read hits
-system.cpu.dtb.read_misses 36227 # DTB read misses
-system.cpu.dtb.write_accesses 321577 # DTB write accesses
-system.cpu.dtb.write_acv 241 # DTB write access violations
-system.cpu.dtb.write_hits 6591036 # DTB write hits
-system.cpu.dtb.write_misses 8151 # DTB write misses
-system.cpu.fetch.Branches 14559443 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 8996158 # Number of cache lines fetched
-system.cpu.fetch.Cycles 23473306 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 455287 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 74247726 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 2478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 968839 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.106358 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 8996158 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 7964957 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.542387 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 102189280
-system.cpu.fetch.rateDist.min_value 0
- 0 87752503 8587.25%
- 1 1049427 102.69%
- 2 2020193 197.69%
- 3 968502 94.78%
- 4 3001129 293.68%
- 5 683878 66.92%
- 6 831667 81.38%
- 7 1217349 119.13%
- 8 4664632 456.47%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 8996158 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 14905.477582 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.562270 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 7948798 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 15611401000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.116423 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1047360 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 51971 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 11852656500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.110646 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 995389 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs 11366.071429 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 7.987119 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 56 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 636500 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 8996158 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 14905.477582 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency
-system.cpu.icache.demand_hits 7948798 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 15611401000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.116423 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1047360 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 51971 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 11852656500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.110646 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 995389 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 8996158 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 14905.477582 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 7948798 # number of overall hits
-system.cpu.icache.overall_miss_latency 15611401000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.116423 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1047360 # number of overall misses
-system.cpu.icache.overall_mshr_hits 51971 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 11852656500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.110646 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 995389 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 994691 # number of replacements
-system.cpu.icache.sampled_refs 995202 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 509.772494 # Cycle average of tags in use
-system.cpu.icache.total_refs 7948797 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 34701444 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 9157080 # Number of branches executed
-system.cpu.iew.EXEC:nop 3677888 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.420385 # Inst execution rate
-system.cpu.iew.EXEC:refs 17040949 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 6614103 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 34509874 # num instructions consuming a value
-system.cpu.iew.WB:count 56954270 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.764112 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 26369407 # num instructions producing a value
-system.cpu.iew.WB:rate 0.416056 # insts written-back per cycle
-system.cpu.iew.WB:sent 57054995 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 856295 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 9703619 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 11041732 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 1799303 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 1049063 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 7011041 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 65859525 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 10426846 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 538501 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 57546755 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 50837 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 6569 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1645972 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 550293 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 311312 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 426511 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 11442 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 45279 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 15270 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1739255 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 621125 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 45279 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 380960 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 475335 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.387555 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.387555 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 58085258 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 7284 0.01% # Type of FU issued
- IntAlu 39585322 68.15% # Type of FU issued
- IntMult 61995 0.11% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 25609 0.04% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 3636 0.01% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 10781907 18.56% # Type of FU issued
- MemWrite 6666291 11.48% # Type of FU issued
- IprAccess 953214 1.64% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 433947 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.007471 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 52004 11.98% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 278726 64.23% # attempts to use FU when none available
- MemWrite 103217 23.79% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 102189280
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 73101546 7153.54%
- 1 14613738 1430.07%
- 2 6411296 627.39%
- 3 3930297 384.61%
- 4 2526857 247.27%
- 5 1033193 101.11%
- 6 443511 43.40%
- 7 107158 10.49%
- 8 21684 2.12%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 0.424318 # Inst issue rate
-system.cpu.iq.iqInstsAdded 60130813 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 58085258 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 2050824 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 8705374 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 34364 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 1383600 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 4697017 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 1300570 # ITB accesses
-system.cpu.itb.acv 941 # ITB acv
-system.cpu.itb.hits 1261136 # ITB hits
-system.cpu.itb.misses 39434 # ITB misses
-system.cpu.kern.callpal 192636 # number of callpals executed
-system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_swpctx 4177 2.17% 2.17% # number of callpals executed
-system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
-system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
-system.cpu.kern.callpal_swpipl 175664 91.19% 93.39% # number of callpals executed
-system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed
-system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed
-system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed
-system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed
-system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed
-system.cpu.kern.callpal_rti 5221 2.71% 99.64% # number of callpals executed
-system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
-system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.hwrei 211796 # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce 6269 # number of quiesce instructions executed
-system.cpu.kern.ipl_count 183013 # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0 74947 40.95% 40.95% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31 105939 57.89% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good 149287 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0 73580 49.29% 49.29% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31 73580 49.29% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks 1867357676000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0 1824918402500 97.73% 97.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_21 102745500 0.01% 97.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_22 392410500 0.02% 97.75% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31 41944117500 2.25% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used_0 0.981760 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31 0.694551 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel 1911
-system.cpu.kern.mode_good_user 1741
-system.cpu.kern.mode_good_idle 170
-system.cpu.kern.mode_switch_kernel 5975 # number of protection mode switches
-system.cpu.kern.mode_switch_user 1741 # number of protection mode switches
-system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches
-system.cpu.kern.mode_switch_good 1.400978 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel 0.319833 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel 31310273000 1.68% 1.68% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user 3185721000 0.17% 1.85% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle 1832861674000 98.15% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4178 # number of times the context was actually changed
-system.cpu.kern.syscall 326 # number of syscalls executed
-system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
-system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
-system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed
-system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed
-system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed
-system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed
-system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed
-system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed
-system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed
-system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed
-system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed
-system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed
-system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed
-system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed
-system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed
-system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed
-system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed
-system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed
-system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed
-system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed
-system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed
-system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed
-system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed
-system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed
-system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed
-system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed
-system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed
-system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
-system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
-system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
-system.cpu.numCycles 136890724 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 14253215 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 38229138 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 1097271 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 39542580 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 2236137 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 15711 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 83423826 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 68665910 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 46022424 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 12703530 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1645972 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 5219245 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 7793284 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 28824736 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 1704564 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 12805073 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 256708 # count of temporary serializing insts renamed
-system.cpu.timesIdled 1321430 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
-system.disk0.dma_write_txs 395 # Number of DMA write transactions.
-system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency 115248.543353 # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses 173 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
-system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency 137791.894638 # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85788.456248 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 5725528806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses 41552 # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency 3564681934 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles_no_mshrs 6164.090493 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.blocked_no_mshrs 10476 # number of cycles access was blocked
-system.iocache.blocked_no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_mshrs 64575012 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency 137698.425500 # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency
-system.iocache.demand_hits 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 5745466804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate 1 # miss rate for demand accesses
-system.iocache.demand_misses 41725 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 3575623932 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency 137698.425500 # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.iocache.overall_hits 0 # number of overall hits
-system.iocache.overall_miss_latency 5745466804 # number of overall miss cycles
-system.iocache.overall_miss_rate 1 # miss rate for overall accesses
-system.iocache.overall_misses 41725 # number of overall misses
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 3575623932 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.iocache.replacements 41685 # number of replacements
-system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 1.267378 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 1716179930000 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 41512 # number of writebacks
-system.l2c.ReadExReq_accesses 300595 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 52362.159484 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40213.629621 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 15739803330 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 300595 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 12088015996 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 300595 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 2097337 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 52066.027817 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40026.238880 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits 1786309 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 16193992500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.148297 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 311028 # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 12449241000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.148296 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 311027 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 797101500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses 130242 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 52272.511886 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.963790 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 6808076493 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 130242 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 5222439000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 130242 # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1102715998 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 430429 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 430429 # number of Writeback hits
-system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 4.598824 # Average number of references to valid blocks.
-system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2397932 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 52211.567959 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency
-system.l2c.demand_hits 1786309 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 31933795830 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.255063 # miss rate for demand accesses
-system.l2c.demand_misses 611623 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 24537256996 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.255062 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 611622 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 2397932 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 52211.567959 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 1786309 # number of overall hits
-system.l2c.overall_miss_latency 31933795830 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.255063 # miss rate for overall accesses
-system.l2c.overall_misses 611623 # number of overall misses
-system.l2c.overall_mshr_hits 1 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 24537256996 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.255062 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 611622 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 1899817498 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 396037 # number of replacements
-system.l2c.sampled_refs 427715 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30684.696960 # Cycle average of tags in use
-system.l2c.total_refs 1966986 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 119087 # number of writebacks
-system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
-system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
-system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: kernel located at: /dist/m5/system/binaries/vmlinux
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:31:00
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 1867358550500 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 6932487 # Number of BTB hits
+global.BPredUnit.BTBLookups 13324936 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 41495 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 828381 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted
+global.BPredUnit.lookups 14559443 # Number of BP lookups
+global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target.
+host_inst_rate 123231 # Simulator instruction rate (inst/s)
+host_mem_usage 290820 # Number of bytes of host memory used
+host_seconds 430.51 # Real time elapsed on the host
+host_tick_rate 4337505567 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 7011041 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 53052618 # Number of instructions simulated
+sim_seconds 1.867359 # Number of seconds simulated
+sim_ticks 1867358550500 # Number of ticks simulated
+system.cpu.commit.COM:branches 8455188 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 973838 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 100543308
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 76317924 7590.55%
+ 1 10743540 1068.55%
+ 2 5987880 595.55%
+ 3 2987787 297.16%
+ 4 2072579 206.14%
+ 5 671161 66.75%
+ 6 395328 39.32%
+ 7 393271 39.11%
+ 8 973838 96.86%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 56244351 # Number of instructions committed
+system.cpu.commit.COM:loads 9302477 # Number of loads committed
+system.cpu.commit.COM:membars 227741 # Number of memory barriers committed
+system.cpu.commit.COM:refs 15692393 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 786910 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 56244351 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 667224 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 9485751 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 53052618 # Number of Instructions Simulated
+system.cpu.committedInsts_total 53052618 # Number of Instructions Simulated
+system.cpu.cpi 2.580282 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.580282 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 214227 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 15534.014065 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11815.523733 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits 192045 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 344575500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate 0.103544 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses 22182 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits 4654 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207102500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081820 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_misses 17528 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 9334533 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 23887.280277 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.210749 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_hits 7801638 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 36616692500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.164218 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1532895 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 448100 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 24694502000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.116213 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1084795 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 889982500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses 219741 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.938098 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.938098 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_hits 189758 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_latency 1689000500 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_rate 0.136447 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses 29983 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599051500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136447 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_misses 29983 # number of StoreCondReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6155139 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 49031.922002 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.269570 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_hits 3924727 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 109361387216 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.362366 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2230412 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1833469 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 21630324960 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.064490 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 396943 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1220847997 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.541558 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 11500 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 8.820405 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 138181 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 1383128462 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 23000 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 15489672 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 38789.840881 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 11726365 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 145978079716 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.242956 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 3763307 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2281569 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 46324826960 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.095660 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1481738 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 15489672 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 38789.840881 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 31263.844863 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 11726365 # number of overall hits
+system.cpu.dcache.overall_miss_latency 145978079716 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.242956 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 3763307 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2281569 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 46324826960 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.095660 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1481738 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 2110830497 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 1402096 # number of replacements
+system.cpu.dcache.sampled_refs 1402608 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 511.995429 # Cycle average of tags in use
+system.cpu.dcache.total_refs 12371571 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 430429 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 48380829 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 42524 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 612955 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 72702474 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 37949237 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 13063267 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1645972 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 134798 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 1149974 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 1229941 # DTB accesses
+system.cpu.dtb.acv 828 # DTB access violations
+system.cpu.dtb.hits 16757791 # DTB hits
+system.cpu.dtb.misses 44378 # DTB misses
+system.cpu.dtb.read_accesses 908364 # DTB read accesses
+system.cpu.dtb.read_acv 587 # DTB read access violations
+system.cpu.dtb.read_hits 10166755 # DTB read hits
+system.cpu.dtb.read_misses 36227 # DTB read misses
+system.cpu.dtb.write_accesses 321577 # DTB write accesses
+system.cpu.dtb.write_acv 241 # DTB write access violations
+system.cpu.dtb.write_hits 6591036 # DTB write hits
+system.cpu.dtb.write_misses 8151 # DTB write misses
+system.cpu.fetch.Branches 14559443 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 8996158 # Number of cache lines fetched
+system.cpu.fetch.Cycles 23473306 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 455287 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 74247726 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 2478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 968839 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.106358 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 8996158 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 7964957 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.542387 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 102189280
+system.cpu.fetch.rateDist.min_value 0
+ 0 87752503 8587.25%
+ 1 1049427 102.69%
+ 2 2020193 197.69%
+ 3 968502 94.78%
+ 4 3001129 293.68%
+ 5 683878 66.92%
+ 6 831667 81.38%
+ 7 1217349 119.13%
+ 8 4664632 456.47%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 8996158 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 14905.477582 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.562270 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 7948798 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 15611401000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.116423 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1047360 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 51971 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 11852656500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.110646 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 995389 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs 11366.071429 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 7.987119 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 56 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 636500 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 8996158 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 14905.477582 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency
+system.cpu.icache.demand_hits 7948798 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 15611401000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.116423 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1047360 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 51971 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 11852656500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.110646 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 995389 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 8996158 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 14905.477582 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11907.562270 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 7948798 # number of overall hits
+system.cpu.icache.overall_miss_latency 15611401000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.116423 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1047360 # number of overall misses
+system.cpu.icache.overall_mshr_hits 51971 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 11852656500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.110646 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 995389 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 994691 # number of replacements
+system.cpu.icache.sampled_refs 995202 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 509.772494 # Cycle average of tags in use
+system.cpu.icache.total_refs 7948797 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 34701444 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 9157080 # Number of branches executed
+system.cpu.iew.EXEC:nop 3677888 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.420385 # Inst execution rate
+system.cpu.iew.EXEC:refs 17040949 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 6614103 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 34509874 # num instructions consuming a value
+system.cpu.iew.WB:count 56954270 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.764112 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 26369407 # num instructions producing a value
+system.cpu.iew.WB:rate 0.416056 # insts written-back per cycle
+system.cpu.iew.WB:sent 57054995 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 856295 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 9703619 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 11041732 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 1799303 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1049063 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 7011041 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 65859525 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 10426846 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 538501 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 57546755 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 50837 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 6569 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1645972 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 550293 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 311312 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 426511 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 11442 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 45279 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 15270 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1739255 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 621125 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 45279 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 380960 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 475335 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.387555 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.387555 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 58085258 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 7284 0.01% # Type of FU issued
+ IntAlu 39585322 68.15% # Type of FU issued
+ IntMult 61995 0.11% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 25609 0.04% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 3636 0.01% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 10781907 18.56% # Type of FU issued
+ MemWrite 6666291 11.48% # Type of FU issued
+ IprAccess 953214 1.64% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 433947 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.007471 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 52004 11.98% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 278726 64.23% # attempts to use FU when none available
+ MemWrite 103217 23.79% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 102189280
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 73101546 7153.54%
+ 1 14613738 1430.07%
+ 2 6411296 627.39%
+ 3 3930297 384.61%
+ 4 2526857 247.27%
+ 5 1033193 101.11%
+ 6 443511 43.40%
+ 7 107158 10.49%
+ 8 21684 2.12%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 0.424318 # Inst issue rate
+system.cpu.iq.iqInstsAdded 60130813 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 58085258 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 2050824 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 8705374 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 34364 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 1383600 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 4697017 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 1300570 # ITB accesses
+system.cpu.itb.acv 941 # ITB acv
+system.cpu.itb.hits 1261136 # ITB hits
+system.cpu.itb.misses 39434 # ITB misses
+system.cpu.kern.callpal 192636 # number of callpals executed
+system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_swpctx 4177 2.17% 2.17% # number of callpals executed
+system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
+system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
+system.cpu.kern.callpal_swpipl 175664 91.19% 93.39% # number of callpals executed
+system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed
+system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed
+system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed
+system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed
+system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed
+system.cpu.kern.callpal_rti 5221 2.71% 99.64% # number of callpals executed
+system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
+system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.hwrei 211796 # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce 6269 # number of quiesce instructions executed
+system.cpu.kern.ipl_count 183013 # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0 74947 40.95% 40.95% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31 105939 57.89% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good 149287 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0 73580 49.29% 49.29% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31 73580 49.29% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks 1867357676000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0 1824918402500 97.73% 97.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21 102745500 0.01% 97.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22 392410500 0.02% 97.75% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31 41944117500 2.25% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used_0 0.981760 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_31 0.694551 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel 1911
+system.cpu.kern.mode_good_user 1741
+system.cpu.kern.mode_good_idle 170
+system.cpu.kern.mode_switch_kernel 5975 # number of protection mode switches
+system.cpu.kern.mode_switch_user 1741 # number of protection mode switches
+system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches
+system.cpu.kern.mode_switch_good 1.400978 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel 0.319833 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel 31310273000 1.68% 1.68% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user 3185721000 0.17% 1.85% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle 1832861674000 98.15% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4178 # number of times the context was actually changed
+system.cpu.kern.syscall 326 # number of syscalls executed
+system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
+system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
+system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed
+system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed
+system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed
+system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed
+system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed
+system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed
+system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed
+system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed
+system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed
+system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed
+system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed
+system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed
+system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed
+system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed
+system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed
+system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed
+system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed
+system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed
+system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed
+system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed
+system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed
+system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed
+system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed
+system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed
+system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed
+system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
+system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
+system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
+system.cpu.numCycles 136890724 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 14253215 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 38229138 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 1097271 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 39542580 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 2236137 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 15711 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 83423826 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 68665910 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 46022424 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 12703530 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1645972 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 5219245 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 7793284 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 28824736 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 1704564 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 12805073 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 256708 # count of temporary serializing insts renamed
+system.cpu.timesIdled 1321430 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
+system.disk0.dma_write_txs 395 # Number of DMA write transactions.
+system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_avg_miss_latency 115248.543353 # average ReadReq miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses 173 # number of ReadReq misses
+system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
+system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_avg_miss_latency 137791.894638 # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85788.456248 # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency 5725528806 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses 41552 # number of WriteReq misses
+system.iocache.WriteReq_mshr_miss_latency 3564681934 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
+system.iocache.avg_blocked_cycles_no_mshrs 6164.090493 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.iocache.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs 10476 # number of cycles access was blocked
+system.iocache.blocked_no_targets 0 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs 64575012 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency 137698.425500 # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency
+system.iocache.demand_hits 0 # number of demand (read+write) hits
+system.iocache.demand_miss_latency 5745466804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate 1 # miss rate for demand accesses
+system.iocache.demand_misses 41725 # number of demand (read+write) misses
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency 3575623932 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency 137698.425500 # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 85695.001366 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.iocache.overall_hits 0 # number of overall hits
+system.iocache.overall_miss_latency 5745466804 # number of overall miss cycles
+system.iocache.overall_miss_rate 1 # miss rate for overall accesses
+system.iocache.overall_misses 41725 # number of overall misses
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency 3575623932 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements 41685 # number of replacements
+system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse 1.267378 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.warmup_cycle 1716179930000 # Cycle when the warmup percentage was hit.
+system.iocache.writebacks 41512 # number of writebacks
+system.l2c.ReadExReq_accesses 300595 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 52362.159484 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40213.629621 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 15739803330 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 300595 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 12088015996 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 300595 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 2097337 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 52066.027817 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40026.238880 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits 1786309 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 16193992500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.148297 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 311028 # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency 12449241000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.148296 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 311027 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 797101500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses 130242 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 52272.511886 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.963790 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 6808076493 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 130242 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 5222439000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 130242 # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency 1102715998 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses 430429 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 430429 # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_refs 4.598824 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.demand_accesses 2397932 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 52211.567959 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency
+system.l2c.demand_hits 1786309 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 31933795830 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.255063 # miss rate for demand accesses
+system.l2c.demand_misses 611623 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 24537256996 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.255062 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 611622 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.overall_accesses 2397932 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 52211.567959 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40118.336155 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.overall_hits 1786309 # number of overall hits
+system.l2c.overall_miss_latency 31933795830 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.255063 # miss rate for overall accesses
+system.l2c.overall_misses 611623 # number of overall misses
+system.l2c.overall_mshr_hits 1 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 24537256996 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.255062 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 611622 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 1899817498 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements 396037 # number of replacements
+system.l2c.sampled_refs 427715 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 30684.696960 # Cycle average of tags in use
+system.l2c.total_refs 1966986 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 119087 # number of writebacks
+system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:30:58
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:31:00
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1867358550500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 2390204 # Simulator instruction rate (inst/s)
-host_mem_usage 328072 # Number of bytes of host memory used
-host_seconds 102.01 # Real time elapsed on the host
-host_tick_rate 1198022319 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 243835278 # Number of instructions simulated
-sim_seconds 0.122216 # Number of seconds simulated
-sim_ticks 122215830000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 244431661 # number of cpu cycles simulated
-system.cpu.num_insts 243835278 # Number of instructions executed
-system.cpu.num_refs 105711442 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:56:43
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 122215830000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2390204 # Simulator instruction rate (inst/s)
+host_mem_usage 328072 # Number of bytes of host memory used
+host_seconds 102.01 # Real time elapsed on the host
+host_tick_rate 1198022319 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 243835278 # Number of instructions simulated
+sim_seconds 0.122216 # Number of seconds simulated
+sim_ticks 122215830000 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 244431661 # number of cpu cycles simulated
+system.cpu.num_insts 243835278 # Number of instructions executed
+system.cpu.num_refs 105711442 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:56:43
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-MCF SPEC version 1.6.I
-by Andreas Loebel
-Copyright (c) 1998,1999 ZIB Berlin
-All Rights Reserved.
-
-nodes : 500
-active arcs : 1905
-simplex iterations : 1502
-flow value : 4990014995
-new implicit arcs : 23867
-active arcs : 25772
-simplex iterations : 2663
-flow value : 3080014995
-checksum : 68389
-optimal
-Exiting @ tick 122215830000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1337728 # Simulator instruction rate (inst/s)
-host_mem_usage 335528 # Number of bytes of host memory used
-host_seconds 182.28 # Real time elapsed on the host
-host_tick_rate 2010386962 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 243835278 # Number of instructions simulated
-sim_seconds 0.366446 # Number of seconds simulated
-sim_ticks 366445521000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 12508650000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 9830079000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses
-system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 448000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 424000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5317928000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 104134565 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 17826578000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 987820 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 14863118000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 987820 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 104134565 # number of overall hits
-system.cpu.dcache.overall_miss_latency 17826578000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 987820 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 14863118000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 935475 # number of replacements
-system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3569.547350 # Cycle average of tags in use
-system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 134389803000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 94875 # number of writebacks
-system.cpu.icache.ReadReq_accesses 244431627 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 244430745 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 46662000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 277132.363946 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 244431627 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
-system.cpu.icache.demand_hits 244430745 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
-system.cpu.icache.demand_misses 882 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 46662000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 244431627 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 244430745 # number of overall hits
-system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
-system.cpu.icache.overall_misses 882 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 46662000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 25 # number of replacements
-system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 726.233997 # Cycle average of tags in use
-system.cpu.icache.total_refs 244430745 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2429128000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868560000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 892653 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 56472000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.001215 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1086 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 2509364000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 94875 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 2485600000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 1912000000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.050827 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 892653 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 47800 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 1912000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 891 # number of replacements
-system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 8958.603097 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 41 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 732891042 # number of cpu cycles simulated
-system.cpu.num_insts 243835278 # Number of instructions executed
-system.cpu.num_refs 105711442 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:52:55
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 366445521000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1337728 # Simulator instruction rate (inst/s)
+host_mem_usage 335528 # Number of bytes of host memory used
+host_seconds 182.28 # Real time elapsed on the host
+host_tick_rate 2010386962 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 243835278 # Number of instructions simulated
+sim_seconds 0.366446 # Number of seconds simulated
+sim_ticks 366445521000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 12508650000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 9830079000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 448000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 424000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 5317928000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 104134565 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 17826578000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 987820 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 14863118000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 987820 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 104134565 # number of overall hits
+system.cpu.dcache.overall_miss_latency 17826578000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 987820 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 14863118000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 935475 # number of replacements
+system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 3569.547350 # Cycle average of tags in use
+system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 134389803000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 94875 # number of writebacks
+system.cpu.icache.ReadReq_accesses 244431627 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 244430745 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 46662000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 277132.363946 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 244431627 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
+system.cpu.icache.demand_hits 244430745 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
+system.cpu.icache.demand_misses 882 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 46662000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 244431627 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 244430745 # number of overall hits
+system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
+system.cpu.icache.overall_misses 882 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 46662000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 25 # number of replacements
+system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 726.233997 # Cycle average of tags in use
+system.cpu.icache.total_refs 244430745 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2429128000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868560000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 892653 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 56472000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.001215 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 1086 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 2509364000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 94875 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 2485600000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 1912000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.050827 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 892653 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 47800 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 1912000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 891 # number of replacements
+system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 8958.603097 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 41 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 732891042 # number of cpu cycles simulated
+system.cpu.num_insts 243835278 # Number of instructions executed
+system.cpu.num_refs 105711442 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:52:55
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-MCF SPEC version 1.6.I
-by Andreas Loebel
-Copyright (c) 1998,1999 ZIB Berlin
-All Rights Reserved.
-
-nodes : 500
-active arcs : 1905
-simplex iterations : 1502
-flow value : 4990014995
-new implicit arcs : 23867
-active arcs : 25772
-simplex iterations : 2663
-flow value : 3080014995
-checksum : 68389
-optimal
-Exiting @ tick 366445521000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1935457 # Simulator instruction rate (inst/s)
-host_mem_usage 329540 # Number of bytes of host memory used
-host_seconds 139.35 # Real time elapsed on the host
-host_tick_rate 1189355805 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 269697303 # Number of instructions simulated
-sim_seconds 0.165732 # Number of seconds simulated
-sim_ticks 165731691000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 331463383 # number of cpu cycles simulated
-system.cpu.num_insts 269697303 # Number of instructions executed
-system.cpu.num_refs 124054655 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 23:03:02
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 23:20:12
+M5 executing on zizzer
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 165731691000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1935457 # Simulator instruction rate (inst/s)
+host_mem_usage 329540 # Number of bytes of host memory used
+host_seconds 139.35 # Real time elapsed on the host
+host_tick_rate 1189355805 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 269697303 # Number of instructions simulated
+sim_seconds 0.165732 # Number of seconds simulated
+sim_ticks 165731691000 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 331463383 # number of cpu cycles simulated
+system.cpu.num_insts 269697303 # Number of instructions executed
+system.cpu.num_refs 124054655 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 23:03:02
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 23:20:12
-M5 executing on zizzer
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-MCF SPEC version 1.6.I
-by Andreas Loebel
-Copyright (c) 1998,1999 ZIB Berlin
-All Rights Reserved.
-
-nodes : 500
-active arcs : 1905
-simplex iterations : 1502
-flow value : 4990014995
-new implicit arcs : 23867
-active arcs : 25772
-simplex iterations : 2663
-flow value : 3080014995
-checksum : 68389
-optimal
-Exiting @ tick 165731691000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1084581 # Simulator instruction rate (inst/s)
-host_mem_usage 336400 # Number of bytes of host memory used
-host_seconds 248.67 # Real time elapsed on the host
-host_tick_rate 1992187591 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 269697303 # Number of instructions simulated
-sim_seconds 0.495388 # Number of seconds simulated
-sim_ticks 495387670000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 88829255 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 31006234000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.021483 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1950188 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 25155670000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.021483 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1950188 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 31439750 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000.034908 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.034908 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 31210573 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 12833920000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.007289 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 229177 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 12146389000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.007289 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 229177 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 58.501856 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 20116.021869 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 120039828 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 43840154000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.017832 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2179365 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 37302059000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.017832 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2179365 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 20116.021869 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 120039828 # number of overall hits
-system.cpu.dcache.overall_miss_latency 43840154000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.017832 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2179365 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 37302059000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.017832 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2179365 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 2049944 # number of replacements
-system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4078.630642 # Cycle average of tags in use
-system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 165919745000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 229129 # number of writebacks
-system.cpu.icache.ReadReq_accesses 331463335 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 331462528 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 42771000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 410734.235440 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 331463335 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.demand_hits 331462528 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
-system.cpu.icache.demand_misses 807 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 42771000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 807 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 331463335 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 331462528 # number of overall hits
-system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
-system.cpu.icache.overall_misses 807 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 42771000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 807 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 24 # number of replacements
-system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 666.116249 # Cycle average of tags in use
-system.cpu.icache.total_refs 331462528 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 103852 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.298502 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 5400335000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 103852 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4154080000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 103852 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 1950995 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 1862007 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 4627376000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.045612 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 88988 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 3559520000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.045612 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 88988 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 125325 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.456812 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 6515704000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 125325 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5013000000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 125325 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 229129 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 229129 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 13.678221 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 2054847 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000.160755 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1862007 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 10027711000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.093846 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 192840 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 7713600000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.093846 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 192840 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 2054847 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000.160755 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1862007 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 10027711000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.093846 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 192840 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 7713600000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.093846 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 192840 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 108885 # number of replacements
-system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18052.553825 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 70892 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 990775340 # number of cpu cycles simulated
-system.cpu.num_insts 269697303 # Number of instructions executed
-system.cpu.num_refs 124054655 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 13 2008 21:51:42
+M5 revision 5729:f186533c0dc2d948be0523b452356918124d7f57
+M5 commit date Sun Nov 09 21:57:15 2008 -0800
+M5 started Nov 13 2008 21:51:43
+M5 executing on tater
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 495387670000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1084581 # Simulator instruction rate (inst/s)
+host_mem_usage 336400 # Number of bytes of host memory used
+host_seconds 248.67 # Real time elapsed on the host
+host_tick_rate 1992187591 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 269697303 # Number of instructions simulated
+sim_seconds 0.495388 # Number of seconds simulated
+sim_ticks 495387670000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 88829255 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 31006234000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.021483 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1950188 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 25155670000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.021483 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1950188 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 31439750 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000.034908 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.034908 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 31210573 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 12833920000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.007289 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 229177 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 12146389000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.007289 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 229177 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 58.501856 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 20116.021869 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 120039828 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 43840154000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.017832 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2179365 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 37302059000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.017832 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2179365 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 20116.021869 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 120039828 # number of overall hits
+system.cpu.dcache.overall_miss_latency 43840154000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.017832 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2179365 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 37302059000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.017832 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2179365 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 2049944 # number of replacements
+system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4078.630642 # Cycle average of tags in use
+system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 165919745000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 229129 # number of writebacks
+system.cpu.icache.ReadReq_accesses 331463335 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 331462528 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 42771000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 410734.235440 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 331463335 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.demand_hits 331462528 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
+system.cpu.icache.demand_misses 807 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 42771000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 807 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 331463335 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 331462528 # number of overall hits
+system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
+system.cpu.icache.overall_misses 807 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 42771000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 807 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 24 # number of replacements
+system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 666.116249 # Cycle average of tags in use
+system.cpu.icache.total_refs 331462528 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses 103852 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.298502 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 5400335000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 103852 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4154080000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 103852 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 1950995 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 1862007 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 4627376000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.045612 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 88988 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 3559520000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.045612 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 88988 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 125325 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51990.456812 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 6515704000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 125325 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5013000000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 125325 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 229129 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 229129 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 13.678221 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 2054847 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000.160755 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 1862007 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 10027711000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.093846 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 192840 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 7713600000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.093846 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 192840 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 2054847 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000.160755 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 1862007 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 10027711000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.093846 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 192840 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 7713600000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.093846 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 192840 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 108885 # number of replacements
+system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 18052.553825 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 70892 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 990775340 # number of cpu cycles simulated
+system.cpu.num_insts 269697303 # Number of instructions executed
+system.cpu.num_refs 124054655 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 13 2008 21:51:42
-M5 revision 5729:f186533c0dc2d948be0523b452356918124d7f57
-M5 commit date Sun Nov 09 21:57:15 2008 -0800
-M5 started Nov 13 2008 21:51:43
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-MCF SPEC version 1.6.I
-by Andreas Loebel
-Copyright (c) 1998,1999 ZIB Berlin
-All Rights Reserved.
-
-nodes : 500
-active arcs : 1905
-simplex iterations : 1502
-flow value : 4990014995
-new implicit arcs : 23867
-active arcs : 25772
-simplex iterations : 2663
-flow value : 3080014995
-checksum : 68389
-optimal
-Exiting @ tick 495387670000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1589069 # Simulator instruction rate (inst/s)
-host_mem_usage 198676 # Number of bytes of host memory used
-host_seconds 941.11 # Real time elapsed on the host
-host_tick_rate 923042875 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1495492702 # Number of instructions simulated
-sim_seconds 0.868687 # Number of seconds simulated
-sim_ticks 868687490500 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1737374982 # number of cpu cycles simulated
-system.cpu.num_insts 1495492702 # Number of instructions executed
-system.cpu.num_refs 533549000 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 23:03:02
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 23:22:32
+M5 executing on zizzer
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+ Reading the dictionary files: *************************************************
+ 58924 words stored in 3784810 bytes
+
+
+Welcome to the Link Parser -- Version 2.1
+
+ Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
+
+Processing sentences in batch mode
+
+Echoing of input sentence turned on.
+* as had expected the party to be a success , it was a success
+* do you know where John 's
+* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
+* how fast the program is it
+* I am wondering whether to invite to the party
+* I gave him for his birthday it
+* I thought terrible after our discussion
+* I wonder how much money have you earned
+* Janet who is an expert on dogs helped me choose one
+* she interviewed more programmers than was hired
+* such flowers are found chiefly particularly in Europe
+* the dogs some of which were very large ran after the man
+* the man whom I play tennis is here
+* there is going to be an important meeting January
+* to pretend that our program is usable in its current form would be happy
+* we're thinking about going to a movie this theater
+* which dog you said you chased
+- also invited to the meeting were several prominent scientists
+- he ran home so quickly that his mother could hardly believe he had called from school
+- so many people attended that they spilled over into several neighboring fields
+- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
+: Grace may not be possible to fix the problem
+ any program as good as ours should be useful
+ biochemically , I think the experiment has a lot of problems
+ Fred has had five years of experience as a programmer
+ he is looking for another job
+ how did John do it
+ how many more people do you think will come
+ how much more spilled
+ I have more money than John has time
+ I made it clear that I was angry
+ I wonder how John did it
+ I wonder how much more quickly he ran
+ invite John and whoever else you want to invite
+ it is easier to ignore the problem than it is to solve it
+ many who initially supported Thomas later changed their minds
+ neither Mary nor Louise are coming to the party
+ she interviewed more programmers than were hired
+ telling Joe that Sue was coming to the party would create a real problem
+ the man with whom I play tennis is here
+ there is a dog in the park
+ this is not the man we know and love
+ we like to eat at restaurants , usually on weekends
+ what did John say he thought you should do
+ about 2 million people attended
+ the five best costumes got prizes
+No errors!
+Exiting @ tick 868687490500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1589069 # Simulator instruction rate (inst/s)
+host_mem_usage 198676 # Number of bytes of host memory used
+host_seconds 941.11 # Real time elapsed on the host
+host_tick_rate 923042875 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1495492702 # Number of instructions simulated
+sim_seconds 0.868687 # Number of seconds simulated
+sim_ticks 868687490500 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1737374982 # number of cpu cycles simulated
+system.cpu.num_insts 1495492702 # Number of instructions executed
+system.cpu.num_refs 533549000 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 23:03:02
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 23:22:32
-M5 executing on zizzer
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
- Reading the dictionary files: *************************************************
- 58924 words stored in 3784810 bytes
-
-
-Welcome to the Link Parser -- Version 2.1
-
- Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
-
-Processing sentences in batch mode
-
-Echoing of input sentence turned on.
-* as had expected the party to be a success , it was a success
-* do you know where John 's
-* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
-* how fast the program is it
-* I am wondering whether to invite to the party
-* I gave him for his birthday it
-* I thought terrible after our discussion
-* I wonder how much money have you earned
-* Janet who is an expert on dogs helped me choose one
-* she interviewed more programmers than was hired
-* such flowers are found chiefly particularly in Europe
-* the dogs some of which were very large ran after the man
-* the man whom I play tennis is here
-* there is going to be an important meeting January
-* to pretend that our program is usable in its current form would be happy
-* we're thinking about going to a movie this theater
-* which dog you said you chased
-- also invited to the meeting were several prominent scientists
-- he ran home so quickly that his mother could hardly believe he had called from school
-- so many people attended that they spilled over into several neighboring fields
-- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
-: Grace may not be possible to fix the problem
- any program as good as ours should be useful
- biochemically , I think the experiment has a lot of problems
- Fred has had five years of experience as a programmer
- he is looking for another job
- how did John do it
- how many more people do you think will come
- how much more spilled
- I have more money than John has time
- I made it clear that I was angry
- I wonder how John did it
- I wonder how much more quickly he ran
- invite John and whoever else you want to invite
- it is easier to ignore the problem than it is to solve it
- many who initially supported Thomas later changed their minds
- neither Mary nor Louise are coming to the party
- she interviewed more programmers than were hired
- telling Joe that Sue was coming to the party would create a real problem
- the man with whom I play tennis is here
- there is a dog in the park
- this is not the man we know and love
- we like to eat at restaurants , usually on weekends
- what did John say he thought you should do
- about 2 million people attended
- the five best costumes got prizes
-No errors!
-Exiting @ tick 868687490500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 588841 # Simulator instruction rate (inst/s)
-host_mem_usage 206816 # Number of bytes of host memory used
-host_seconds 2539.72 # Real time elapsed on the host
-host_tick_rate 941590971 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1495492697 # Number of instructions simulated
-sim_seconds 2.391380 # Number of seconds simulated
-sim_ticks 2391380378000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 384102203 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 382375390 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 36518057000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.004496 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1726813 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 149160208 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 147694060 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 82104159500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.009829 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1466148 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 77705715500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 210.782586 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 533262411 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 530069450 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 114223772500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.005988 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 3192961 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 533262411 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 530069450 # number of overall hits
-system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 3192961 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 114223772500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.005988 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 2513875 # number of replacements
-system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4086.151092 # Cycle average of tags in use
-system.cpu.dcache.total_refs 530744440 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 12270587000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 1463913 # number of writebacks
-system.cpu.icache.ReadReq_accesses 1737374915 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1737372102 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 127753000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 617622.503377 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1737374915 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1737372102 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
-system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 127753000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 2813 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1737374915 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1737372102 # number of overall hits
-system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
-system.cpu.icache.overall_misses 2813 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 127753000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 1253 # number of replacements
-system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 873.848519 # Cycle average of tags in use
-system.cpu.icache.total_refs 1737372102 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 791158 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014536 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 41140227500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 791158 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 31646320000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 791158 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 1729626 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 1310104 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 21815144000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.242551 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 419522 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 16780880000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242551 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 419522 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 674990 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 35092200000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 674990 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26999600000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 674990 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 1463913 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.428071 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 2520784 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1310104 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 62955371500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.480279 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 1210680 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 48427200000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.480279 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 1210680 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 2520784 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1310104 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 62955371500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 1210680 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 48427200000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 663512 # number of replacements
-system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 17171.686632 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 1313099811000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 481430 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 4782760756 # number of cpu cycles simulated
-system.cpu.num_insts 1495492697 # Number of instructions executed
-system.cpu.num_refs 533549000 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 9 2008 18:23:31
+M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e
+M5 commit date Sat Nov 08 21:06:07 2008 -0800
+M5 started Nov 9 2008 18:34:37
+M5 executing on tater
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+ Reading the dictionary files: *************************************************
+ 58924 words stored in 3784810 bytes
+
+
+Welcome to the Link Parser -- Version 2.1
+
+ Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
+
+Processing sentences in batch mode
+
+Echoing of input sentence turned on.
+* as had expected the party to be a success , it was a success
+* do you know where John 's
+* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
+* how fast the program is it
+* I am wondering whether to invite to the party
+* I gave him for his birthday it
+* I thought terrible after our discussion
+* I wonder how much money have you earned
+* Janet who is an expert on dogs helped me choose one
+* she interviewed more programmers than was hired
+* such flowers are found chiefly particularly in Europe
+* the dogs some of which were very large ran after the man
+* the man whom I play tennis is here
+* there is going to be an important meeting January
+* to pretend that our program is usable in its current form would be happy
+* we're thinking about going to a movie this theater
+* which dog you said you chased
+- also invited to the meeting were several prominent scientists
+- he ran home so quickly that his mother could hardly believe he had called from school
+- so many people attended that they spilled over into several neighboring fields
+- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
+: Grace may not be possible to fix the problem
+ any program as good as ours should be useful
+ biochemically , I think the experiment has a lot of problems
+ Fred has had five years of experience as a programmer
+ he is looking for another job
+ how did John do it
+ how many more people do you think will come
+ how much more spilled
+ I have more money than John has time
+ I made it clear that I was angry
+ I wonder how John did it
+ I wonder how much more quickly he ran
+ invite John and whoever else you want to invite
+ it is easier to ignore the problem than it is to solve it
+ many who initially supported Thomas later changed their minds
+ neither Mary nor Louise are coming to the party
+ she interviewed more programmers than were hired
+ telling Joe that Sue was coming to the party would create a real problem
+ the man with whom I play tennis is here
+ there is a dog in the park
+ this is not the man we know and love
+ we like to eat at restaurants , usually on weekends
+ what did John say he thought you should do
+ about 2 million people attended
+ the five best costumes got prizes
+No errors!
+Exiting @ tick 2391380378000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 588841 # Simulator instruction rate (inst/s)
+host_mem_usage 206816 # Number of bytes of host memory used
+host_seconds 2539.72 # Real time elapsed on the host
+host_tick_rate 941590971 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1495492697 # Number of instructions simulated
+sim_seconds 2.391380 # Number of seconds simulated
+sim_ticks 2391380378000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 384102203 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 382375390 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 36518057000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.004496 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1726813 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 149160208 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 147694060 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 82104159500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.009829 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1466148 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 77705715500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 210.782586 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 533262411 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 530069450 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 114223772500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005988 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 3192961 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 533262411 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 530069450 # number of overall hits
+system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 3192961 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 114223772500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005988 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 2513875 # number of replacements
+system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4086.151092 # Cycle average of tags in use
+system.cpu.dcache.total_refs 530744440 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 12270587000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 1463913 # number of writebacks
+system.cpu.icache.ReadReq_accesses 1737374915 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1737372102 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 127753000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 617622.503377 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1737374915 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1737372102 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
+system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 127753000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 2813 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1737374915 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1737372102 # number of overall hits
+system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
+system.cpu.icache.overall_misses 2813 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 127753000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 1253 # number of replacements
+system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 873.848519 # Cycle average of tags in use
+system.cpu.icache.total_refs 1737372102 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses 791158 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014536 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 41140227500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 791158 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 31646320000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 791158 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 1729626 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 1310104 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 21815144000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.242551 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 419522 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 16780880000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242551 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 419522 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 674990 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 35092200000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 674990 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26999600000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 674990 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 1463913 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 3.428071 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 2520784 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 1310104 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 62955371500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.480279 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 1210680 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 48427200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.480279 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 1210680 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 2520784 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 1310104 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 62955371500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 1210680 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 48427200000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 663512 # number of replacements
+system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 17171.686632 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 1313099811000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 481430 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 4782760756 # number of cpu cycles simulated
+system.cpu.num_insts 1495492697 # Number of instructions executed
+system.cpu.num_refs 533549000 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 9 2008 18:23:31
-M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e
-M5 commit date Sat Nov 08 21:06:07 2008 -0800
-M5 started Nov 9 2008 18:34:37
-M5 executing on tater
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/20.parser/x86/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
- Reading the dictionary files: *************************************************
- 58924 words stored in 3784810 bytes
-
-
-Welcome to the Link Parser -- Version 2.1
-
- Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
-
-Processing sentences in batch mode
-
-Echoing of input sentence turned on.
-* as had expected the party to be a success , it was a success
-* do you know where John 's
-* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
-* how fast the program is it
-* I am wondering whether to invite to the party
-* I gave him for his birthday it
-* I thought terrible after our discussion
-* I wonder how much money have you earned
-* Janet who is an expert on dogs helped me choose one
-* she interviewed more programmers than was hired
-* such flowers are found chiefly particularly in Europe
-* the dogs some of which were very large ran after the man
-* the man whom I play tennis is here
-* there is going to be an important meeting January
-* to pretend that our program is usable in its current form would be happy
-* we're thinking about going to a movie this theater
-* which dog you said you chased
-- also invited to the meeting were several prominent scientists
-- he ran home so quickly that his mother could hardly believe he had called from school
-- so many people attended that they spilled over into several neighboring fields
-- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
-: Grace may not be possible to fix the problem
- any program as good as ours should be useful
- biochemically , I think the experiment has a lot of problems
- Fred has had five years of experience as a programmer
- he is looking for another job
- how did John do it
- how many more people do you think will come
- how much more spilled
- I have more money than John has time
- I made it clear that I was angry
- I wonder how John did it
- I wonder how much more quickly he ran
- invite John and whoever else you want to invite
- it is easier to ignore the problem than it is to solve it
- many who initially supported Thomas later changed their minds
- neither Mary nor Louise are coming to the party
- she interviewed more programmers than were hired
- telling Joe that Sue was coming to the party would create a real problem
- the man with whom I play tennis is here
- there is a dog in the park
- this is not the man we know and love
- we like to eat at restaurants , usually on weekends
- what did John say he thought you should do
- about 2 million people attended
- the five best costumes got prizes
-No errors!
-Exiting @ tick 2391380378000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 38296034 # Number of BTB hits
-global.BPredUnit.BTBLookups 45834466 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 1077 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 5781170 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted
-global.BPredUnit.lookups 62209737 # Number of BP lookups
-global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target.
-host_inst_rate 151728 # Simulator instruction rate (inst/s)
-host_mem_usage 209656 # Number of bytes of host memory used
-host_seconds 2475.31 # Real time elapsed on the host
-host_tick_rate 54537175 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 92324076 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 375574819 # Number of instructions simulated
-sim_seconds 0.134997 # Number of seconds simulated
-sim_ticks 134996684500 # Number of ticks simulated
-system.cpu.commit.COM:branches 44587532 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 254545672
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 123085209 4835.49%
- 1 50466868 1982.63%
- 2 18758377 736.94%
- 3 19955031 783.95%
- 4 11844121 465.30%
- 5 8478667 333.09%
- 6 5819307 228.62%
- 7 2974518 116.86%
- 8 13163574 517.14%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 398664594 # Number of instructions committed
-system.cpu.commit.COM:loads 100651995 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 174183397 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 5776994 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 94782663 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 375574819 # Number of Instructions Simulated
-system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
-system.cpu.cpi 0.718880 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.718880 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 33016.637478 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 95499596 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 56557500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1713 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 729 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 30310.747349 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.886371 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 73502716 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 545987492 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000245 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 18013 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 14704 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 119775497 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 3249.700000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40460.272684 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 32497 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30545.726047 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 169002312 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 602544992 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 19726 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 15433 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 169002312 # number of overall hits
-system.cpu.dcache.overall_miss_latency 602544992 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 19726 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 15433 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 782 # number of replacements
-system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use
-system.cpu.dcache.total_refs 169002559 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 635 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 4277 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 11323346 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 531939828 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 132443197 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 101952317 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 15306974 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 12561 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 1275127 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 185115437 # DTB accesses
-system.cpu.dtb.acv 1 # DTB access violations
-system.cpu.dtb.hits 185076670 # DTB hits
-system.cpu.dtb.misses 38767 # DTB misses
-system.cpu.dtb.read_accesses 104449499 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 104412186 # DTB read hits
-system.cpu.dtb.read_misses 37313 # DTB read misses
-system.cpu.dtb.write_accesses 80665938 # DTB write accesses
-system.cpu.dtb.write_acv 1 # DTB write access violations
-system.cpu.dtb.write_hits 80664484 # DTB write hits
-system.cpu.dtb.write_misses 1454 # DTB write misses
-system.cpu.fetch.Branches 62209737 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 63866189 # Number of cache lines fetched
-system.cpu.fetch.Cycles 169616790 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 1519057 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 544903543 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 6123543 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.230412 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 63866189 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 50640538 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.018211 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 269852647
-system.cpu.fetch.rateDist.min_value 0
- 0 164102333 6081.18%
- 1 12367121 458.29%
- 2 12410556 459.90%
- 3 6615129 245.14%
- 4 15923029 590.06%
- 5 8709903 322.77%
- 6 6580254 243.85%
- 7 4007808 148.52%
- 8 39136514 1450.29%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 63866189 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 32249.018798 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 30883.598563 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 63861348 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 156117500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 4841 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 945 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 120322500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 16391.516427 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 63866189 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 32249.018798 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency
-system.cpu.icache.demand_hits 63861348 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 156117500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
-system.cpu.icache.demand_misses 4841 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 945 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 120322500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 63861348 # number of overall hits
-system.cpu.icache.overall_miss_latency 156117500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
-system.cpu.icache.overall_misses 4841 # number of overall misses
-system.cpu.icache.overall_mshr_hits 945 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 120322500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 1975 # number of replacements
-system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1823.540410 # Cycle average of tags in use
-system.cpu.icache.total_refs 63861348 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 50976851 # Number of branches executed
-system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate
-system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 80676625 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 285463485 # num instructions consuming a value
-system.cpu.iew.WB:count 415481237 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 200770520 # num instructions producing a value
-system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle
-system.cpu.iew.WB:sent 416287464 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 6390313 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 6302760 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 10261544 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 419338652 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 15306974 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 341836 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 8734674 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 2193 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 436213 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 176181 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 24189228 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 5542509 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 429600196 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 33581 0.01% # Type of FU issued
- IntAlu 166319014 38.71% # Type of FU issued
- IntMult 2152935 0.50% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 35077566 8.17% # Type of FU issued
- FloatCmp 7830879 1.82% # Type of FU issued
- FloatCvt 2898460 0.67% # Type of FU issued
- FloatMult 16788316 3.91% # Type of FU issued
- FloatDiv 1569716 0.37% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 113503270 26.42% # Type of FU issued
- MemWrite 83426459 19.42% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 10457046 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.024341 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 40640 0.39% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 76056 0.73% # attempts to use FU when none available
- FloatCmp 13381 0.13% # attempts to use FU when none available
- FloatCvt 12891 0.12% # attempts to use FU when none available
- FloatMult 1723474 16.48% # attempts to use FU when none available
- FloatDiv 1473560 14.09% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 5907144 56.49% # attempts to use FU when none available
- MemWrite 1209900 11.57% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 269852647
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 99465935 3685.94%
- 1 57766030 2140.65%
- 2 39984554 1481.72%
- 3 29664959 1099.30%
- 4 23966120 888.12%
- 5 10452563 387.34%
- 6 5712016 211.67%
- 7 2252970 83.49%
- 8 587500 21.77%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate
-system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 68228113 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 63866476 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 63866189 # ITB hits
-system.cpu.itb.misses 287 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 3197 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 110604499 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 3197 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 100602000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 3197 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 4876 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34359.867330 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31168.325041 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 145033000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.865669 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 4221 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 131561500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865669 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 4221 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 119 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34441.176471 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31285.714286 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 4098500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 119 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 635 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs 3000 # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.130240 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 6000 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 8073 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34461.782017 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 655 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 255637499 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.918865 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 7418 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 232163500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.918865 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 7418 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 655 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 255637499 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.918865 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 7418 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 232163500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.918865 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 7418 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 14 # number of replacements
-system.cpu.l2cache.sampled_refs 4676 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3875.343408 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 609 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 269993372 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 8452992 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 1780176 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 137359458 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 7392558 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 684397837 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 518816398 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 335732022 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 97960614 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 15306974 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 10399659 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 76199681 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 372950 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 37950 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 22290547 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 251 # count of temporary serializing insts renamed
-system.cpu.timesIdled 3086 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+warn: Increasing stack size by one page.
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:46
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Eon, Version 1.1
+OO-style eon Time= 0.133333
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 38296034 # Number of BTB hits
+global.BPredUnit.BTBLookups 45834466 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 1077 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 5781170 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted
+global.BPredUnit.lookups 62209737 # Number of BP lookups
+global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target.
+host_inst_rate 151728 # Simulator instruction rate (inst/s)
+host_mem_usage 209656 # Number of bytes of host memory used
+host_seconds 2475.31 # Real time elapsed on the host
+host_tick_rate 54537175 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 92324076 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 375574819 # Number of instructions simulated
+sim_seconds 0.134997 # Number of seconds simulated
+sim_ticks 134996684500 # Number of ticks simulated
+system.cpu.commit.COM:branches 44587532 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 254545672
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 123085209 4835.49%
+ 1 50466868 1982.63%
+ 2 18758377 736.94%
+ 3 19955031 783.95%
+ 4 11844121 465.30%
+ 5 8478667 333.09%
+ 6 5819307 228.62%
+ 7 2974518 116.86%
+ 8 13163574 517.14%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 398664594 # Number of instructions committed
+system.cpu.commit.COM:loads 100651995 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 174183397 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 5776994 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 94782663 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 375574819 # Number of Instructions Simulated
+system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
+system.cpu.cpi 0.718880 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.718880 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 33016.637478 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 95499596 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 56557500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1713 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 729 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 30310.747349 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.886371 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 73502716 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 545987492 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000245 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 18013 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 14704 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 119775497 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 3249.700000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 40460.272684 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 32497 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 30545.726047 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 169002312 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 602544992 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 19726 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 15433 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 169002312 # number of overall hits
+system.cpu.dcache.overall_miss_latency 602544992 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 19726 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 15433 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 782 # number of replacements
+system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use
+system.cpu.dcache.total_refs 169002559 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 635 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 4277 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 11323346 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 531939828 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 132443197 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 101952317 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 15306974 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 12561 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 1275127 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 185115437 # DTB accesses
+system.cpu.dtb.acv 1 # DTB access violations
+system.cpu.dtb.hits 185076670 # DTB hits
+system.cpu.dtb.misses 38767 # DTB misses
+system.cpu.dtb.read_accesses 104449499 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 104412186 # DTB read hits
+system.cpu.dtb.read_misses 37313 # DTB read misses
+system.cpu.dtb.write_accesses 80665938 # DTB write accesses
+system.cpu.dtb.write_acv 1 # DTB write access violations
+system.cpu.dtb.write_hits 80664484 # DTB write hits
+system.cpu.dtb.write_misses 1454 # DTB write misses
+system.cpu.fetch.Branches 62209737 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 63866189 # Number of cache lines fetched
+system.cpu.fetch.Cycles 169616790 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1519057 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 544903543 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 6123543 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.230412 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 63866189 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 50640538 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.018211 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 269852647
+system.cpu.fetch.rateDist.min_value 0
+ 0 164102333 6081.18%
+ 1 12367121 458.29%
+ 2 12410556 459.90%
+ 3 6615129 245.14%
+ 4 15923029 590.06%
+ 5 8709903 322.77%
+ 6 6580254 243.85%
+ 7 4007808 148.52%
+ 8 39136514 1450.29%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 63866189 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 32249.018798 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 30883.598563 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 63861348 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 156117500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 4841 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 945 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 120322500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 16391.516427 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 63866189 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 32249.018798 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency
+system.cpu.icache.demand_hits 63861348 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 156117500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
+system.cpu.icache.demand_misses 4841 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 945 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 120322500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 63861348 # number of overall hits
+system.cpu.icache.overall_miss_latency 156117500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
+system.cpu.icache.overall_misses 4841 # number of overall misses
+system.cpu.icache.overall_mshr_hits 945 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 120322500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 1975 # number of replacements
+system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1823.540410 # Cycle average of tags in use
+system.cpu.icache.total_refs 63861348 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 50976851 # Number of branches executed
+system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate
+system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 80676625 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 285463485 # num instructions consuming a value
+system.cpu.iew.WB:count 415481237 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 200770520 # num instructions producing a value
+system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle
+system.cpu.iew.WB:sent 416287464 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 6390313 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 6302760 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 10261544 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 419338652 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 15306974 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 341836 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 8734674 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 2193 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 436213 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 176181 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 24189228 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 5542509 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 429600196 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 33581 0.01% # Type of FU issued
+ IntAlu 166319014 38.71% # Type of FU issued
+ IntMult 2152935 0.50% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 35077566 8.17% # Type of FU issued
+ FloatCmp 7830879 1.82% # Type of FU issued
+ FloatCvt 2898460 0.67% # Type of FU issued
+ FloatMult 16788316 3.91% # Type of FU issued
+ FloatDiv 1569716 0.37% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 113503270 26.42% # Type of FU issued
+ MemWrite 83426459 19.42% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 10457046 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.024341 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 40640 0.39% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 76056 0.73% # attempts to use FU when none available
+ FloatCmp 13381 0.13% # attempts to use FU when none available
+ FloatCvt 12891 0.12% # attempts to use FU when none available
+ FloatMult 1723474 16.48% # attempts to use FU when none available
+ FloatDiv 1473560 14.09% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 5907144 56.49% # attempts to use FU when none available
+ MemWrite 1209900 11.57% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 269852647
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 99465935 3685.94%
+ 1 57766030 2140.65%
+ 2 39984554 1481.72%
+ 3 29664959 1099.30%
+ 4 23966120 888.12%
+ 5 10452563 387.34%
+ 6 5712016 211.67%
+ 7 2252970 83.49%
+ 8 587500 21.77%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate
+system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 68228113 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 63866476 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 63866189 # ITB hits
+system.cpu.itb.misses 287 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 3197 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 110604499 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 3197 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 100602000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 3197 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 4876 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34359.867330 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31168.325041 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 145033000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.865669 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 4221 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 131561500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865669 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 4221 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 119 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34441.176471 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31285.714286 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 4098500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 119 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 635 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs 3000 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.130240 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 6000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 8073 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34461.782017 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 655 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 255637499 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.918865 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 7418 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 232163500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.918865 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 7418 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 655 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 255637499 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.918865 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 7418 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 232163500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.918865 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 7418 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 14 # number of replacements
+system.cpu.l2cache.sampled_refs 4676 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 3875.343408 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 609 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 269993372 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 8452992 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 1780176 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 137359458 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 7392558 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 684397837 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 518816398 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 335732022 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 97960614 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 15306974 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 10399659 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 76199681 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 372950 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 37950 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 22290547 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 251 # count of temporary serializing insts renamed
+system.cpu.timesIdled 3086 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-getting pixel output filename pixels_out.cook
-opening control file chair.control.cook
-opening camera file chair.camera
-opening surfaces file chair.surfaces
-reading data
-warn: Increasing stack size by one page.
-processing 8parts
-Grid measure is 6 by 3.0001 by 6
-cell dimension is 0.863065
-Creating grid for list of length 21
-Grid size = 7 by 4 by 7
-Total occupancy = 236
-reading control stream
-reading camera stream
-Writing to chair.cook.ppm
-calculating 15 by 15 image with 196 samples
-col 0. . .
-col 1. . .
-col 2. . .
-col 3. . .
-col 4. . .
-col 5. . .
-col 6. . .
-col 7. . .
-col 8. . .
-col 9. . .
-col 10. . .
-col 11. . .
-col 12. . .
-col 13. . .
-col 14. . .
-Writing to chair.cook.ppm
-0 8 14
-1 8 14
-2 8 14
-3 8 14
-4 8 14
-5 8 14
-6 8 14
-7 8 14
-8 8 14
-9 8 14
-10 8 14
-11 8 14
-12 8 14
-13 8 14
-14 8 14
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:46
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Eon, Version 1.1
-OO-style eon Time= 0.133333
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 3407773 # Simulator instruction rate (inst/s)
-host_mem_usage 201328 # Number of bytes of host memory used
-host_seconds 116.99 # Real time elapsed on the host
-host_tick_rate 1703884563 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 398664595 # Number of instructions simulated
-sim_seconds 0.199332 # Number of seconds simulated
-sim_ticks 199332411500 # Number of ticks simulated
-system.cpu.dtb.accesses 168275274 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 168275218 # DTB hits
-system.cpu.dtb.misses 56 # DTB misses
-system.cpu.dtb.read_accesses 94754510 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 94754489 # DTB read hits
-system.cpu.dtb.read_misses 21 # DTB read misses
-system.cpu.dtb.write_accesses 73520764 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 73520729 # DTB write hits
-system.cpu.dtb.write_misses 35 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 398664824 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 398664651 # ITB hits
-system.cpu.itb.misses 173 # ITB misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 398664824 # number of cpu cycles simulated
-system.cpu.num_insts 398664595 # Number of instructions executed
-system.cpu.num_refs 174183453 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+warn: Increasing stack size by one page.
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:26:02
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Eon, Version 1.1
+OO-style eon Time= 0.183333
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 3407773 # Simulator instruction rate (inst/s)
+host_mem_usage 201328 # Number of bytes of host memory used
+host_seconds 116.99 # Real time elapsed on the host
+host_tick_rate 1703884563 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 398664595 # Number of instructions simulated
+sim_seconds 0.199332 # Number of seconds simulated
+sim_ticks 199332411500 # Number of ticks simulated
+system.cpu.dtb.accesses 168275274 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 168275218 # DTB hits
+system.cpu.dtb.misses 56 # DTB misses
+system.cpu.dtb.read_accesses 94754510 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 94754489 # DTB read hits
+system.cpu.dtb.read_misses 21 # DTB read misses
+system.cpu.dtb.write_accesses 73520764 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 73520729 # DTB write hits
+system.cpu.dtb.write_misses 35 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 398664824 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 398664651 # ITB hits
+system.cpu.itb.misses 173 # ITB misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 398664824 # number of cpu cycles simulated
+system.cpu.num_insts 398664595 # Number of instructions executed
+system.cpu.num_refs 174183453 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-getting pixel output filename pixels_out.cook
-opening control file chair.control.cook
-opening camera file chair.camera
-opening surfaces file chair.surfaces
-reading data
-warn: Increasing stack size by one page.
-processing 8parts
-Grid measure is 6 by 3.0001 by 6
-cell dimension is 0.863065
-Creating grid for list of length 21
-Grid size = 7 by 4 by 7
-Total occupancy = 236
-reading control stream
-reading camera stream
-Writing to chair.cook.ppm
-calculating 15 by 15 image with 196 samples
-col 0. . .
-col 1. . .
-col 2. . .
-col 3. . .
-col 4. . .
-col 5. . .
-col 6. . .
-col 7. . .
-col 8. . .
-col 9. . .
-col 10. . .
-col 11. . .
-col 12. . .
-col 13. . .
-col 14. . .
-Writing to chair.cook.ppm
-0 8 14
-1 8 14
-2 8 14
-3 8 14
-4 8 14
-5 8 14
-6 8 14
-7 8 14
-8 8 14
-9 8 14
-10 8 14
-11 8 14
-12 8 14
-13 8 14
-14 8 14
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:26:02
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Eon, Version 1.1
-OO-style eon Time= 0.183333
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1526276 # Simulator instruction rate (inst/s)
-host_mem_usage 208780 # Number of bytes of host memory used
-host_seconds 261.20 # Real time elapsed on the host
-host_tick_rate 2172088412 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 398664609 # Number of instructions simulated
-sim_seconds 0.567352 # Number of seconds simulated
-sim_ticks 567351850000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 185584000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 175642000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54847.560976 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 233870000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 221078000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 168270956 # number of overall hits
-system.cpu.dcache.overall_miss_latency 233870000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 4264 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 221078000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 764 # number of replacements
-system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3288.899192 # Cycle average of tags in use
-system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 625 # number of writebacks
-system.cpu.dtb.accesses 168275276 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 168275220 # DTB hits
-system.cpu.dtb.misses 56 # DTB misses
-system.cpu.dtb.read_accesses 94754511 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 94754490 # DTB read hits
-system.cpu.dtb.read_misses 21 # DTB read misses
-system.cpu.dtb.write_accesses 73520765 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 73520730 # DTB write hits
-system.cpu.dtb.write_misses 35 # DTB write misses
-system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
-system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
-system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 398660993 # number of overall hits
-system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
-system.cpu.icache.overall_misses 3673 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 1769 # number of replacements
-system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1795.124700 # Cycle average of tags in use
-system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 398664839 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 398664666 # ITB hits
-system.cpu.itb.misses 173 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 166504000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 128080000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 5824000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4480000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.120240 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 376480000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 289600000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 585 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 376480000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 7240 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 289600000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 15 # number of replacements
-system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3714.176115 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1134703700 # number of cpu cycles simulated
-system.cpu.num_insts 398664609 # Number of instructions executed
-system.cpu.num_refs 174183455 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+warn: Increasing stack size by one page.
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:22:18
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Eon, Version 1.1
+OO-style eon Time= 0.566667
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1526276 # Simulator instruction rate (inst/s)
+host_mem_usage 208780 # Number of bytes of host memory used
+host_seconds 261.20 # Real time elapsed on the host
+host_tick_rate 2172088412 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 398664609 # Number of instructions simulated
+sim_seconds 0.567352 # Number of seconds simulated
+sim_ticks 567351850000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 185584000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 175642000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 54847.560976 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 233870000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 221078000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 168270956 # number of overall hits
+system.cpu.dcache.overall_miss_latency 233870000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 4264 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 221078000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 764 # number of replacements
+system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 3288.899192 # Cycle average of tags in use
+system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 625 # number of writebacks
+system.cpu.dtb.accesses 168275276 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 168275220 # DTB hits
+system.cpu.dtb.misses 56 # DTB misses
+system.cpu.dtb.read_accesses 94754511 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 94754490 # DTB read hits
+system.cpu.dtb.read_misses 21 # DTB read misses
+system.cpu.dtb.write_accesses 73520765 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 73520730 # DTB write hits
+system.cpu.dtb.write_misses 35 # DTB write misses
+system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
+system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
+system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 398660993 # number of overall hits
+system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
+system.cpu.icache.overall_misses 3673 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 1769 # number of replacements
+system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1795.124700 # Cycle average of tags in use
+system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 398664839 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 398664666 # ITB hits
+system.cpu.itb.misses 173 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 166504000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 128080000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 5824000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4480000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.120240 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 376480000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 289600000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 585 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 376480000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 7240 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 289600000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 15 # number of replacements
+system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 3714.176115 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1134703700 # number of cpu cycles simulated
+system.cpu.num_insts 398664609 # Number of instructions executed
+system.cpu.num_refs 174183455 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-getting pixel output filename pixels_out.cook
-opening control file chair.control.cook
-opening camera file chair.camera
-opening surfaces file chair.surfaces
-reading data
-warn: Increasing stack size by one page.
-processing 8parts
-Grid measure is 6 by 3.0001 by 6
-cell dimension is 0.863065
-Creating grid for list of length 21
-Grid size = 7 by 4 by 7
-Total occupancy = 236
-reading control stream
-reading camera stream
-Writing to chair.cook.ppm
-calculating 15 by 15 image with 196 samples
-col 0. . .
-col 1. . .
-col 2. . .
-col 3. . .
-col 4. . .
-col 5. . .
-col 6. . .
-col 7. . .
-col 8. . .
-col 9. . .
-col 10. . .
-col 11. . .
-col 12. . .
-col 13. . .
-col 14. . .
-Writing to chair.cook.ppm
-0 8 14
-1 8 14
-2 8 14
-3 8 14
-4 8 14
-5 8 14
-6 8 14
-7 8 14
-8 8 14
-9 8 14
-10 8 14
-11 8 14
-12 8 14
-13 8 14
-14 8 14
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:22:18
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Eon, Version 1.1
-OO-style eon Time= 0.566667
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 240462096 # Number of BTB hits
-global.BPredUnit.BTBLookups 294213603 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted
-global.BPredUnit.lookups 349424731 # Number of BP lookups
-global.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target.
-host_inst_rate 157306 # Simulator instruction rate (inst/s)
-host_mem_usage 209560 # Number of bytes of host memory used
-host_seconds 11589.17 # Real time elapsed on the host
-host_tick_rate 60846406 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 303651290 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1823043370 # Number of instructions simulated
-sim_seconds 0.705159 # Number of seconds simulated
-sim_ticks 705159454500 # Number of ticks simulated
-system.cpu.commit.COM:branches 266706457 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 68860244 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 1310002800
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 603585596 4607.51%
- 1 273587005 2088.45%
- 2 174037133 1328.52%
- 3 65399708 499.23%
- 4 48333001 368.95%
- 5 34003110 259.57%
- 6 18481318 141.08%
- 7 23715685 181.04%
- 8 68860244 525.65%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 2008987604 # Number of instructions committed
-system.cpu.commit.COM:loads 511595302 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 722390433 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 29095954 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 696013930 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
-system.cpu.cpi 0.773607 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.773607 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 6 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 6 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 465737269 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 37550.774879 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34829.991989 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 463802710 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 72644189500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.004154 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1934559 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 475266 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 50827163500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.003133 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1459293 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 38583.618605 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.752250 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 210235541 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 21581939985 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.002654 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 559355 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 484574 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2731357498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 5124.928571 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 18000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 440.284636 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 28 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 143498 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 18000 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 676532165 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 37782.429340 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 674038251 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 94226129485 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.003686 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2493914 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 959840 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 53558520998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002268 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1534074 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 674038251 # number of overall hits
-system.cpu.dcache.overall_miss_latency 94226129485 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2493914 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 959840 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 53558520998 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002268 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 1526847 # number of replacements
-system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.104513 # Cycle average of tags in use
-system.cpu.dcache.total_refs 674050682 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 274499000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 74589 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 32190527 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 12129 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 30585324 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 2936172402 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 716337474 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 561391036 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 775959987 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 775335043 # DTB hits
-system.cpu.dtb.misses 624944 # DTB misses
-system.cpu.dtb.read_accesses 516992085 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 516404963 # DTB read hits
-system.cpu.dtb.read_misses 587122 # DTB read misses
-system.cpu.dtb.write_accesses 258967902 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 258930080 # DTB write hits
-system.cpu.dtb.write_misses 37822 # DTB write misses
-system.cpu.fetch.Branches 349424731 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 348447899 # Number of cache lines fetched
-system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 3030218619 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 29544622 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 1410161885
-system.cpu.fetch.rateDist.min_value 0
- 0 830588040 5890.02%
- 1 53463106 379.13%
- 2 39766072 282.00%
- 3 63538024 450.57%
- 4 121390719 860.83%
- 5 35256321 250.02%
- 6 38761682 274.87%
- 7 6988644 49.56%
- 8 220409277 1563.01%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 348447899 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 15851.065828 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.513514 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 348437250 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 168798000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 10649 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 881 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 113685000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 9768 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 35671.299140 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 348447899 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 15851.065828 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency
-system.cpu.icache.demand_hits 348437250 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 168798000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
-system.cpu.icache.demand_misses 10649 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 881 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 113685000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 9768 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 348437250 # number of overall hits
-system.cpu.icache.overall_miss_latency 168798000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
-system.cpu.icache.overall_misses 10649 # number of overall misses
-system.cpu.icache.overall_mshr_hits 881 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 113685000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 9768 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 8097 # number of replacements
-system.cpu.icache.sampled_refs 9768 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1614.102824 # Cycle average of tags in use
-system.cpu.icache.total_refs 348437250 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 157025 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 274534145 # Number of branches executed
-system.cpu.iew.EXEC:nop 329178061 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.421117 # Inst execution rate
-system.cpu.iew.EXEC:refs 776495503 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 258968900 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1631503179 # num instructions consuming a value
-system.cpu.iew.WB:count 2002130585 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.696431 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1136229268 # num instructions producing a value
-system.cpu.iew.WB:rate 1.419630 # insts written-back per cycle
-system.cpu.iew.WB:sent 2003425032 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 31680133 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 3459468 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 655954745 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 62130 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 303651290 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 2715209778 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 517526603 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 85279852 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 2004227953 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 131519 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 3361 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 100159084 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 141229 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 50663539 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 152 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 3589 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 4102 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 144359443 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 92856159 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 3589 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 816990 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 30863143 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 2089507805 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 2752 0.00% # Type of FU issued
- IntAlu 1204412678 57.64% # Type of FU issued
- IntMult 17591 0.00% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 27851349 1.33% # Type of FU issued
- FloatCmp 8254694 0.40% # Type of FU issued
- FloatCvt 7204646 0.34% # Type of FU issued
- FloatMult 4 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 557993260 26.70% # Type of FU issued
- MemWrite 283770831 13.58% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 37093546 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 8291 0.02% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 28032977 75.57% # attempts to use FU when none available
- MemWrite 9052278 24.40% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 1410161885
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 537278436 3810.05%
- 1 285217724 2022.59%
- 2 273546804 1939.83%
- 3 154810620 1097.82%
- 4 63341841 449.18%
- 5 51438515 364.77%
- 6 32491109 230.41%
- 7 9036668 64.08%
- 8 3000168 21.28%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate
-system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 562621267 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 348448092 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 348447899 # ITB hits
-system.cpu.itb.misses 193 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.990928 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.847872 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2514269500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 71650 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297518000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 71650 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 1469061 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34325.576147 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.455515 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 28934 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 49433189000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.980304 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1440127 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 44644593000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980304 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1440127 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 3137 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34069.333758 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.659229 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 106875500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 3137 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97362000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 3137 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs 8187.500000 # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.023462 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 8 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 65500 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 1540711 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34361.852641 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 28934 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 51947458500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.981220 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 1511777 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 46942111000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981220 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 1511777 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 28934 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 51947458500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.981220 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 1511777 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 46942111000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981220 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 1511777 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 1474251 # number of replacements
-system.cpu.l2cache.sampled_refs 1506809 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 31919.645552 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 35353 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 66899 # number of writebacks
-system.cpu.numCycles 1410318910 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 20063964 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 687776 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 730652071 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 11530186 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 3303379014 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 2836019296 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 1886227369 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 545599397 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 100159084 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 13665899 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 501258299 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 21470 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 2842 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 27803045 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 61 # count of temporary serializing insts renamed
-system.cpu.timesIdled 4055 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+1375000: 2038431008
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+1372000: 1943746837
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--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 240462096 # Number of BTB hits
+global.BPredUnit.BTBLookups 294213603 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted
+global.BPredUnit.lookups 349424731 # Number of BP lookups
+global.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target.
+host_inst_rate 157306 # Simulator instruction rate (inst/s)
+host_mem_usage 209560 # Number of bytes of host memory used
+host_seconds 11589.17 # Real time elapsed on the host
+host_tick_rate 60846406 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 303651290 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1823043370 # Number of instructions simulated
+sim_seconds 0.705159 # Number of seconds simulated
+sim_ticks 705159454500 # Number of ticks simulated
+system.cpu.commit.COM:branches 266706457 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 68860244 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 1310002800
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 603585596 4607.51%
+ 1 273587005 2088.45%
+ 2 174037133 1328.52%
+ 3 65399708 499.23%
+ 4 48333001 368.95%
+ 5 34003110 259.57%
+ 6 18481318 141.08%
+ 7 23715685 181.04%
+ 8 68860244 525.65%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 2008987604 # Number of instructions committed
+system.cpu.commit.COM:loads 511595302 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 722390433 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 29095954 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 696013930 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
+system.cpu.cpi 0.773607 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.773607 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 6 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits 6 # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses 465737269 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 37550.774879 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34829.991989 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 463802710 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 72644189500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.004154 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1934559 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 475266 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 50827163500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.003133 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1459293 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 38583.618605 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.752250 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 210235541 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 21581939985 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.002654 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 559355 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 484574 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2731357498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 5124.928571 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 18000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 440.284636 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 28 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 143498 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 18000 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 676532165 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 37782.429340 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 674038251 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 94226129485 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.003686 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2493914 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 959840 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 53558520998 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002268 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1534074 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 674038251 # number of overall hits
+system.cpu.dcache.overall_miss_latency 94226129485 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2493914 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 959840 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 53558520998 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002268 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 1526847 # number of replacements
+system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4095.104513 # Cycle average of tags in use
+system.cpu.dcache.total_refs 674050682 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 274499000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 74589 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 32190527 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 12129 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 30585324 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 2936172402 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 716337474 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 561391036 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 775959987 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 775335043 # DTB hits
+system.cpu.dtb.misses 624944 # DTB misses
+system.cpu.dtb.read_accesses 516992085 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 516404963 # DTB read hits
+system.cpu.dtb.read_misses 587122 # DTB read misses
+system.cpu.dtb.write_accesses 258967902 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 258930080 # DTB write hits
+system.cpu.dtb.write_misses 37822 # DTB write misses
+system.cpu.fetch.Branches 349424731 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 348447899 # Number of cache lines fetched
+system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 3030218619 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 29544622 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 1410161885
+system.cpu.fetch.rateDist.min_value 0
+ 0 830588040 5890.02%
+ 1 53463106 379.13%
+ 2 39766072 282.00%
+ 3 63538024 450.57%
+ 4 121390719 860.83%
+ 5 35256321 250.02%
+ 6 38761682 274.87%
+ 7 6988644 49.56%
+ 8 220409277 1563.01%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 348447899 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 15851.065828 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.513514 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 348437250 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 168798000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 10649 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 881 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 113685000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 9768 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 35671.299140 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 348447899 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 15851.065828 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency
+system.cpu.icache.demand_hits 348437250 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 168798000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
+system.cpu.icache.demand_misses 10649 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 881 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 113685000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 9768 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 348437250 # number of overall hits
+system.cpu.icache.overall_miss_latency 168798000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
+system.cpu.icache.overall_misses 10649 # number of overall misses
+system.cpu.icache.overall_mshr_hits 881 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 113685000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 9768 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 8097 # number of replacements
+system.cpu.icache.sampled_refs 9768 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1614.102824 # Cycle average of tags in use
+system.cpu.icache.total_refs 348437250 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 157025 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 274534145 # Number of branches executed
+system.cpu.iew.EXEC:nop 329178061 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.421117 # Inst execution rate
+system.cpu.iew.EXEC:refs 776495503 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 258968900 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 1631503179 # num instructions consuming a value
+system.cpu.iew.WB:count 2002130585 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.696431 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 1136229268 # num instructions producing a value
+system.cpu.iew.WB:rate 1.419630 # insts written-back per cycle
+system.cpu.iew.WB:sent 2003425032 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 31680133 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 3459468 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 655954745 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 62130 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 303651290 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 2715209778 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 517526603 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 85279852 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2004227953 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 131519 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 3361 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 100159084 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 141229 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 50663539 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 152 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 3589 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 4102 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 144359443 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 92856159 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 3589 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 816990 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 30863143 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 2089507805 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 2752 0.00% # Type of FU issued
+ IntAlu 1204412678 57.64% # Type of FU issued
+ IntMult 17591 0.00% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 27851349 1.33% # Type of FU issued
+ FloatCmp 8254694 0.40% # Type of FU issued
+ FloatCvt 7204646 0.34% # Type of FU issued
+ FloatMult 4 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 557993260 26.70% # Type of FU issued
+ MemWrite 283770831 13.58% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 37093546 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 8291 0.02% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 28032977 75.57% # attempts to use FU when none available
+ MemWrite 9052278 24.40% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 1410161885
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 537278436 3810.05%
+ 1 285217724 2022.59%
+ 2 273546804 1939.83%
+ 3 154810620 1097.82%
+ 4 63341841 449.18%
+ 5 51438515 364.77%
+ 6 32491109 230.41%
+ 7 9036668 64.08%
+ 8 3000168 21.28%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate
+system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 562621267 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 348448092 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 348447899 # ITB hits
+system.cpu.itb.misses 193 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.990928 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.847872 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2514269500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 71650 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297518000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 71650 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 1469061 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34325.576147 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.455515 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 28934 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 49433189000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.980304 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 1440127 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 44644593000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980304 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 1440127 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 3137 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34069.333758 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.659229 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 106875500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 3137 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97362000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 3137 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs 8187.500000 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.023462 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 8 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 65500 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 1540711 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34361.852641 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 28934 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 51947458500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.981220 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 1511777 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 46942111000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.981220 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 1511777 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 28934 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 51947458500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.981220 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 1511777 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 46942111000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.981220 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 1511777 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 1474251 # number of replacements
+system.cpu.l2cache.sampled_refs 1506809 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 31919.645552 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 35353 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 66899 # number of writebacks
+system.cpu.numCycles 1410318910 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 20063964 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 687776 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 730652071 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 11530186 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 3303379014 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 2836019296 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 1886227369 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 545599397 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 100159084 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 13665899 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 501258299 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 21470 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 2842 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 27803045 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 61 # count of temporary serializing insts renamed
+system.cpu.timesIdled 4055 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: ignoring syscall sigprocmask(1, 0, ...)
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:45
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
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+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 3237524 # Simulator instruction rate (inst/s)
-host_mem_usage 200500 # Number of bytes of host memory used
-host_seconds 620.53 # Real time elapsed on the host
-host_tick_rate 1619110797 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2008987605 # Number of instructions simulated
-sim_seconds 1.004711 # Number of seconds simulated
-sim_ticks 1004710587000 # Number of ticks simulated
-system.cpu.dtb.accesses 722298387 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 721864922 # DTB hits
-system.cpu.dtb.misses 433465 # DTB misses
-system.cpu.dtb.read_accesses 511488910 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 511070026 # DTB read hits
-system.cpu.dtb.read_misses 418884 # DTB read misses
-system.cpu.dtb.write_accesses 210809477 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 210794896 # DTB write hits
-system.cpu.dtb.write_misses 14581 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 2009421175 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 2009421070 # ITB hits
-system.cpu.itb.misses 105 # ITB misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 2009421175 # number of cpu cycles simulated
-system.cpu.num_insts 2008987605 # Number of instructions executed
-system.cpu.num_refs 722823898 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:26:39
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
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--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 3237524 # Simulator instruction rate (inst/s)
+host_mem_usage 200500 # Number of bytes of host memory used
+host_seconds 620.53 # Real time elapsed on the host
+host_tick_rate 1619110797 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 2008987605 # Number of instructions simulated
+sim_seconds 1.004711 # Number of seconds simulated
+sim_ticks 1004710587000 # Number of ticks simulated
+system.cpu.dtb.accesses 722298387 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 721864922 # DTB hits
+system.cpu.dtb.misses 433465 # DTB misses
+system.cpu.dtb.read_accesses 511488910 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 511070026 # DTB read hits
+system.cpu.dtb.read_misses 418884 # DTB read misses
+system.cpu.dtb.write_accesses 210809477 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 210794896 # DTB write hits
+system.cpu.dtb.write_misses 14581 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 2009421175 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 2009421070 # ITB hits
+system.cpu.itb.misses 105 # ITB misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 2009421175 # number of cpu cycles simulated
+system.cpu.num_insts 2008987605 # Number of instructions executed
+system.cpu.num_refs 722823898 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: ignoring syscall sigprocmask(1, 0, ...)
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:26:39
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
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+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1407375 # Simulator instruction rate (inst/s)
-host_mem_usage 207960 # Number of bytes of host memory used
-host_seconds 1427.47 # Real time elapsed on the host
-host_tick_rate 1971983298 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2008987605 # Number of instructions simulated
-sim_seconds 2.814951 # Number of seconds simulated
-sim_ticks 2814951154000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 55392.232299 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.232299 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 80772510000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 76397934000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.692460 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.692460 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 210720109 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 4188049000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000355 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 74787 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 3963688000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 74787 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55421.867488 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 84960559000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 80361622000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55421.867488 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 720331943 # number of overall hits
-system.cpu.dcache.overall_miss_latency 84960559000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1532979 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 80361622000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 1526048 # number of replacements
-system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.198740 # Cycle average of tags in use
-system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1054514000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 74589 # number of writebacks
-system.cpu.dtb.accesses 722298387 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 721864922 # DTB hits
-system.cpu.dtb.misses 433465 # DTB misses
-system.cpu.dtb.read_accesses 511488910 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 511070026 # DTB read hits
-system.cpu.dtb.read_misses 418884 # DTB read misses
-system.cpu.dtb.write_accesses 210809477 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 210794896 # DTB write hits
-system.cpu.dtb.write_misses 14581 # DTB write misses
-system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 23421.857305 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 248178000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 216390000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
-system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 248178000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
-system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 216390000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 2009410475 # number of overall hits
-system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
-system.cpu.icache.overall_misses 10596 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 216390000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 9046 # number of replacements
-system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1478.420115 # Cycle average of tags in use
-system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 2009421176 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 2009421071 # ITB hits
-system.cpu.itb.misses 105 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 3741504000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 71952 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2878080000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 71952 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 29320 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 74852336000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.980038 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1439468 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 57578720000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980038 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1439468 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51578.130511 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 146224000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 2835 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113400000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 2835 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.023744 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 29320 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 78593840000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 1511420 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 60456800000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 1511420 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 29320 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 78593840000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 1511420 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 60456800000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 1511420 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 1473608 # number of replacements
-system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 31910.237485 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 35763 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 66899 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 5629902308 # number of cpu cycles simulated
-system.cpu.num_insts 2008987605 # Number of instructions executed
-system.cpu.num_refs 722823898 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: ignoring syscall sigprocmask(1, 0, ...)
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:44
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
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--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1407375 # Simulator instruction rate (inst/s)
+host_mem_usage 207960 # Number of bytes of host memory used
+host_seconds 1427.47 # Real time elapsed on the host
+host_tick_rate 1971983298 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 2008987605 # Number of instructions simulated
+sim_seconds 2.814951 # Number of seconds simulated
+sim_ticks 2814951154000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 55392.232299 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.232299 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 80772510000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 76397934000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.692460 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.692460 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 210720109 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4188049000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000355 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 74787 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 3963688000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 74787 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 55421.867488 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 84960559000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 80361622000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 55421.867488 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 720331943 # number of overall hits
+system.cpu.dcache.overall_miss_latency 84960559000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1532979 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 80361622000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 1526048 # number of replacements
+system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4095.198740 # Cycle average of tags in use
+system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 1054514000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 74589 # number of writebacks
+system.cpu.dtb.accesses 722298387 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 721864922 # DTB hits
+system.cpu.dtb.misses 433465 # DTB misses
+system.cpu.dtb.read_accesses 511488910 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 511070026 # DTB read hits
+system.cpu.dtb.read_misses 418884 # DTB read misses
+system.cpu.dtb.write_accesses 210809477 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 210794896 # DTB write hits
+system.cpu.dtb.write_misses 14581 # DTB write misses
+system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 23421.857305 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 248178000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 216390000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
+system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 248178000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
+system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 216390000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 2009410475 # number of overall hits
+system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
+system.cpu.icache.overall_misses 10596 # number of overall misses
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+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 9046 # number of replacements
+system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1478.420115 # Cycle average of tags in use
+system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 2009421176 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 2009421071 # ITB hits
+system.cpu.itb.misses 105 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 3741504000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 71952 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2878080000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 71952 # number of ReadExReq MSHR misses
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+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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+system.cpu.l2cache.ReadReq_mshr_misses 1439468 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51578.130511 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 146224000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113400000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 2835 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.023744 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 29320 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 78593840000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 1511420 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 60456800000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 1511420 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 29320 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 78593840000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 1511420 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 60456800000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 1511420 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 1473608 # number of replacements
+system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 31910.237485 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 35763 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 66899 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 5629902308 # number of cpu cycles simulated
+system.cpu.num_insts 2008987605 # Number of instructions executed
+system.cpu.num_refs 722823898 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: ignoring syscall sigprocmask(1, 0, ...)
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:44
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
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-15000: 1240694507
-14000: 1586030084
-13000: 1211450031
-12000: 3458253062
-11000: 1804606651
-10000: 2128587109
-9000: 1894810186
-8000: 2221431098
-7000: 113605713
-6000: 4020003580
-5000: 2988041351
-4000: 2310084217
-3000: 1475476779
-2000: 760651391
-1000: 4031656975
-0: 2206428413
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 8039250 # Number of BTB hits
-global.BPredUnit.BTBLookups 14256744 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted
-global.BPredUnit.lookups 16249463 # Number of BP lookups
-global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target.
-host_inst_rate 155507 # Simulator instruction rate (inst/s)
-host_mem_usage 212996 # Number of bytes of host memory used
-host_seconds 511.82 # Real time elapsed on the host
-host_tick_rate 53016132 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 16328872 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 79591756 # Number of instructions simulated
-sim_seconds 0.027135 # Number of seconds simulated
-sim_ticks 27134794500 # Number of ticks simulated
-system.cpu.commit.COM:branches 13754477 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 51751168
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 22506445 4348.97%
- 1 11357579 2194.65%
- 2 5114502 988.29%
- 3 3560855 688.07%
- 4 2552504 493.23%
- 5 1532717 296.17%
- 6 1008933 194.96%
- 7 796739 153.96%
- 8 3320894 641.70%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 88340672 # Number of instructions committed
-system.cpu.commit.COM:loads 20379399 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 35224018 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 79591756 # Number of Instructions Simulated
-system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
-system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 33838925 # number of overall hits
-system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1199965 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 200933 # number of replacements
-system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use
-system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147760 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 36599689 # DTB accesses
-system.cpu.dtb.acv 39 # DTB access violations
-system.cpu.dtb.hits 36425481 # DTB hits
-system.cpu.dtb.misses 174208 # DTB misses
-system.cpu.dtb.read_accesses 21541288 # DTB read accesses
-system.cpu.dtb.read_acv 37 # DTB read access violations
-system.cpu.dtb.read_hits 21383020 # DTB read hits
-system.cpu.dtb.read_misses 158268 # DTB read misses
-system.cpu.dtb.write_accesses 15058401 # DTB write accesses
-system.cpu.dtb.write_acv 2 # DTB write access violations
-system.cpu.dtb.write_hits 15042461 # DTB write hits
-system.cpu.dtb.write_misses 15940 # DTB write misses
-system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched
-system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 53041270
-system.cpu.fetch.rateDist.min_value 0
- 0 33206277 6260.46%
- 1 1871594 352.86%
- 2 1529415 288.34%
- 3 1809626 341.17%
- 4 3985239 751.35%
- 5 1867239 352.04%
- 6 695846 131.19%
- 7 1111736 209.60%
- 8 6964298 1313.00%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
-system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses
-system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 13297366 # number of overall hits
-system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses
-system.cpu.icache.overall_misses 88706 # number of overall misses
-system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 83888 # number of replacements
-system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use
-system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 14745486 # Number of branches executed
-system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate
-system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 15291392 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value
-system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 32396987 # num instructions producing a value
-system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle
-system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 0 0.00% # Type of FU issued
- IntAlu 47898565 56.12% # Type of FU issued
- IntMult 42953 0.05% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 121655 0.14% # Type of FU issued
- FloatCmp 88 0.00% # Type of FU issued
- FloatCvt 122104 0.14% # Type of FU issued
- FloatMult 53 0.00% # Type of FU issued
- FloatDiv 38535 0.05% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 21753622 25.49% # Type of FU issued
- MemWrite 15368770 18.01% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 97100 9.91% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 470602 48.04% # attempts to use FU when none available
- MemWrite 411938 42.05% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 53041270
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 17563410 3311.27%
- 1 13937999 2627.76%
- 2 8266125 1558.43%
- 3 4784809 902.09%
- 4 4627568 872.45%
- 5 2066740 389.65%
- 6 1112374 209.72%
- 7 454507 85.69%
- 8 227738 42.94%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate
-system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 13412237 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 13386072 # ITB hits
-system.cpu.itb.misses 26165 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 102894 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 188071 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 148779 # number of replacements
-system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 120647 # number of writebacks
-system.cpu.numCycles 54269590 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed
-system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:27:20
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 8039250 # Number of BTB hits
+global.BPredUnit.BTBLookups 14256744 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted
+global.BPredUnit.lookups 16249463 # Number of BP lookups
+global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target.
+host_inst_rate 155507 # Simulator instruction rate (inst/s)
+host_mem_usage 212996 # Number of bytes of host memory used
+host_seconds 511.82 # Real time elapsed on the host
+host_tick_rate 53016132 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 16328872 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 79591756 # Number of instructions simulated
+sim_seconds 0.027135 # Number of seconds simulated
+sim_ticks 27134794500 # Number of ticks simulated
+system.cpu.commit.COM:branches 13754477 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 51751168
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 22506445 4348.97%
+ 1 11357579 2194.65%
+ 2 5114502 988.29%
+ 3 3560855 688.07%
+ 4 2552504 493.23%
+ 5 1532717 296.17%
+ 6 1008933 194.96%
+ 7 796739 153.96%
+ 8 3320894 641.70%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 88340672 # Number of instructions committed
+system.cpu.commit.COM:loads 20379399 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 35224018 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 79591756 # Number of Instructions Simulated
+system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
+system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 33838925 # number of overall hits
+system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1199965 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 200933 # number of replacements
+system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use
+system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 147760 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 36599689 # DTB accesses
+system.cpu.dtb.acv 39 # DTB access violations
+system.cpu.dtb.hits 36425481 # DTB hits
+system.cpu.dtb.misses 174208 # DTB misses
+system.cpu.dtb.read_accesses 21541288 # DTB read accesses
+system.cpu.dtb.read_acv 37 # DTB read access violations
+system.cpu.dtb.read_hits 21383020 # DTB read hits
+system.cpu.dtb.read_misses 158268 # DTB read misses
+system.cpu.dtb.write_accesses 15058401 # DTB write accesses
+system.cpu.dtb.write_acv 2 # DTB write access violations
+system.cpu.dtb.write_hits 15042461 # DTB write hits
+system.cpu.dtb.write_misses 15940 # DTB write misses
+system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched
+system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 53041270
+system.cpu.fetch.rateDist.min_value 0
+ 0 33206277 6260.46%
+ 1 1871594 352.86%
+ 2 1529415 288.34%
+ 3 1809626 341.17%
+ 4 3985239 751.35%
+ 5 1867239 352.04%
+ 6 695846 131.19%
+ 7 1111736 209.60%
+ 8 6964298 1313.00%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
+system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses
+system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 13297366 # number of overall hits
+system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses
+system.cpu.icache.overall_misses 88706 # number of overall misses
+system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 83888 # number of replacements
+system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use
+system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 14745486 # Number of branches executed
+system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate
+system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 15291392 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value
+system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 32396987 # num instructions producing a value
+system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle
+system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 0 0.00% # Type of FU issued
+ IntAlu 47898565 56.12% # Type of FU issued
+ IntMult 42953 0.05% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 121655 0.14% # Type of FU issued
+ FloatCmp 88 0.00% # Type of FU issued
+ FloatCvt 122104 0.14% # Type of FU issued
+ FloatMult 53 0.00% # Type of FU issued
+ FloatDiv 38535 0.05% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 21753622 25.49% # Type of FU issued
+ MemWrite 15368770 18.01% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 97100 9.91% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 470602 48.04% # attempts to use FU when none available
+ MemWrite 411938 42.05% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 53041270
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 17563410 3311.27%
+ 1 13937999 2627.76%
+ 2 8266125 1558.43%
+ 3 4784809 902.09%
+ 4 4627568 872.45%
+ 5 2066740 389.65%
+ 6 1112374 209.72%
+ 7 454507 85.69%
+ 8 227738 42.94%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate
+system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 13412237 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 13386072 # ITB hits
+system.cpu.itb.misses 26165 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 102894 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 188071 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 148779 # number of replacements
+system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 120647 # number of writebacks
+system.cpu.numCycles 54269590 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed
+system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:27:20
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 3156054 # Simulator instruction rate (inst/s)
-host_mem_usage 203904 # Number of bytes of host memory used
-host_seconds 27.99 # Real time elapsed on the host
-host_tick_rate 1579824710 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 88340673 # Number of instructions simulated
-sim_seconds 0.044221 # Number of seconds simulated
-sim_ticks 44221003000 # Number of ticks simulated
-system.cpu.dtb.accesses 34987415 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 34890015 # DTB hits
-system.cpu.dtb.misses 97400 # DTB misses
-system.cpu.dtb.read_accesses 20366786 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 20276638 # DTB read hits
-system.cpu.dtb.read_misses 90148 # DTB read misses
-system.cpu.dtb.write_accesses 14620629 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 14613377 # DTB write hits
-system.cpu.dtb.write_misses 7252 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 88442007 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 88438073 # ITB hits
-system.cpu.itb.misses 3934 # ITB misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 88442007 # number of cpu cycles simulated
-system.cpu.num_insts 88340673 # Number of instructions executed
-system.cpu.num_refs 35321418 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:24:43
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 3156054 # Simulator instruction rate (inst/s)
+host_mem_usage 203904 # Number of bytes of host memory used
+host_seconds 27.99 # Real time elapsed on the host
+host_tick_rate 1579824710 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 88340673 # Number of instructions simulated
+sim_seconds 0.044221 # Number of seconds simulated
+sim_ticks 44221003000 # Number of ticks simulated
+system.cpu.dtb.accesses 34987415 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 34890015 # DTB hits
+system.cpu.dtb.misses 97400 # DTB misses
+system.cpu.dtb.read_accesses 20366786 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 20276638 # DTB read hits
+system.cpu.dtb.read_misses 90148 # DTB read misses
+system.cpu.dtb.write_accesses 14620629 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 14613377 # DTB write hits
+system.cpu.dtb.write_misses 7252 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 88442007 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 88438073 # ITB hits
+system.cpu.itb.misses 3934 # ITB misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 88442007 # number of cpu cycles simulated
+system.cpu.num_insts 88340673 # Number of instructions executed
+system.cpu.num_refs 35321418 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:24:43
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1655989 # Simulator instruction rate (inst/s)
-host_mem_usage 211348 # Number of bytes of host memory used
-host_seconds 53.35 # Real time elapsed on the host
-host_tick_rate 2533794438 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 88340673 # Number of instructions simulated
-sim_seconds 0.135169 # Number of seconds simulated
-sim_ticks 135168766000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 34679456 # number of overall hits
-system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 210559 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 200248 # number of replacements
-system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use
-system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147714 # number of writebacks
-system.cpu.dtb.accesses 34987415 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 34890015 # DTB hits
-system.cpu.dtb.misses 97400 # DTB misses
-system.cpu.dtb.read_accesses 20366786 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 20276638 # DTB read hits
-system.cpu.dtb.read_misses 90148 # DTB read misses
-system.cpu.dtb.write_accesses 14620629 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 14613377 # DTB write hits
-system.cpu.dtb.write_misses 7252 # DTB write misses
-system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency
-system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
-system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 88361638 # number of overall hits
-system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
-system.cpu.icache.overall_misses 76436 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 74391 # number of replacements
-system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use
-system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 88442008 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 88438074 # ITB hits
-system.cpu.itb.misses 3934 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 93905 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 186875 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 147561 # number of replacements
-system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 120634 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 270337532 # number of cpu cycles simulated
-system.cpu.num_insts 88340673 # Number of instructions executed
-system.cpu.num_refs 35321418 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:28:00
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1655989 # Simulator instruction rate (inst/s)
+host_mem_usage 211348 # Number of bytes of host memory used
+host_seconds 53.35 # Real time elapsed on the host
+host_tick_rate 2533794438 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 88340673 # Number of instructions simulated
+sim_seconds 0.135169 # Number of seconds simulated
+sim_ticks 135168766000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 34679456 # number of overall hits
+system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 210559 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 200248 # number of replacements
+system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use
+system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 147714 # number of writebacks
+system.cpu.dtb.accesses 34987415 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 34890015 # DTB hits
+system.cpu.dtb.misses 97400 # DTB misses
+system.cpu.dtb.read_accesses 20366786 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 20276638 # DTB read hits
+system.cpu.dtb.read_misses 90148 # DTB read misses
+system.cpu.dtb.write_accesses 14620629 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 14613377 # DTB write hits
+system.cpu.dtb.write_misses 7252 # DTB write misses
+system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency
+system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
+system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 88361638 # number of overall hits
+system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
+system.cpu.icache.overall_misses 76436 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 74391 # number of replacements
+system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use
+system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 88442008 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 88438074 # ITB hits
+system.cpu.itb.misses 3934 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 93905 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 186875 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 147561 # number of replacements
+system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 120634 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 270337532 # number of cpu cycles simulated
+system.cpu.num_insts 88340673 # Number of instructions executed
+system.cpu.num_refs 35321418 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:28:00
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 2431097 # Simulator instruction rate (inst/s)
-host_mem_usage 204768 # Number of bytes of host memory used
-host_seconds 56.00 # Real time elapsed on the host
-host_tick_rate 1216955986 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 136139203 # Number of instructions simulated
-sim_seconds 0.068149 # Number of seconds simulated
-sim_ticks 68148678500 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 136297358 # number of cpu cycles simulated
-system.cpu.num_insts 136139203 # Number of instructions executed
-system.cpu.num_refs 58160249 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: ignoring syscall time(4026527848, 4026528248, ...)
+warn: ignoring syscall time(4026527400, 1375098, ...)
+warn: ignoring syscall time(4026527312, 1, ...)
+warn: ignoring syscall time(4026527048, 413, ...)
+warn: ignoring syscall time(4026527048, 414, ...)
+warn: ignoring syscall time(4026527288, 4026527688, ...)
+warn: ignoring syscall time(4026526840, 1375098, ...)
+warn: Increasing stack size by one page.
+warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(4026526960, 409, ...)
+warn: ignoring syscall time(4026527040, 409, ...)
+warn: ignoring syscall time(4026527000, 409, ...)
+warn: ignoring syscall time(4026526984, 409, ...)
+warn: ignoring syscall time(4026526984, 409, ...)
+warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(4026526312, 19045, ...)
+warn: ignoring syscall time(4026526832, 409, ...)
+warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(4026526840, 409, ...)
+warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(4026526936, 409, ...)
+warn: ignoring syscall time(4026527008, 4026527408, ...)
+warn: ignoring syscall time(4026526560, 1375098, ...)
+warn: ignoring syscall time(4026527184, 18732, ...)
+warn: ignoring syscall time(4026526632, 409, ...)
+warn: ignoring syscall time(4026526736, 0, ...)
+warn: ignoring syscall time(4026527320, 0, ...)
+warn: ignoring syscall time(4026527744, 225, ...)
+warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(4026527096, 4026527496, ...)
+warn: ignoring syscall time(4026526648, 1375098, ...)
+warn: ignoring syscall time(4026526824, 0, ...)
+warn: ignoring syscall time(4026527320, 0, ...)
+warn: ignoring syscall time(4026527184, 1879089152, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
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+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
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+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall time(4026527472, 1595768, ...)
+warn: ignoring syscall time(4026526912, 17300, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026526912, 19045, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026526912, 19045, ...)
+warn: ignoring syscall time(4026526912, 17300, ...)
+warn: ignoring syscall time(4026525968, 20500, ...)
+warn: ignoring syscall time(4026525968, 4026526436, ...)
+warn: ignoring syscall time(4026526056, 7004192, ...)
+warn: ignoring syscall time(4026527512, 4, ...)
+warn: ignoring syscall time(4026525760, 0, ...)
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:55:47
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 68148678500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2431097 # Simulator instruction rate (inst/s)
+host_mem_usage 204768 # Number of bytes of host memory used
+host_seconds 56.00 # Real time elapsed on the host
+host_tick_rate 1216955986 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 136139203 # Number of instructions simulated
+sim_seconds 0.068149 # Number of seconds simulated
+sim_ticks 68148678500 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 136297358 # number of cpu cycles simulated
+system.cpu.num_insts 136139203 # Number of instructions executed
+system.cpu.num_refs 58160249 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ignoring syscall time(4026527848, 4026528248, ...)
-warn: ignoring syscall time(4026527400, 1375098, ...)
-warn: ignoring syscall time(4026527312, 1, ...)
-warn: ignoring syscall time(4026527048, 413, ...)
-warn: ignoring syscall time(4026527048, 414, ...)
-warn: ignoring syscall time(4026527288, 4026527688, ...)
-warn: ignoring syscall time(4026526840, 1375098, ...)
-warn: Increasing stack size by one page.
-warn: ignoring syscall time(4026527048, 409, ...)
-warn: ignoring syscall time(4026527048, 409, ...)
-warn: ignoring syscall time(4026526960, 409, ...)
-warn: ignoring syscall time(4026527040, 409, ...)
-warn: ignoring syscall time(4026527000, 409, ...)
-warn: ignoring syscall time(4026526984, 409, ...)
-warn: ignoring syscall time(4026526984, 409, ...)
-warn: ignoring syscall time(4026526872, 409, ...)
-warn: ignoring syscall time(4026526312, 19045, ...)
-warn: ignoring syscall time(4026526832, 409, ...)
-warn: ignoring syscall time(4026526872, 409, ...)
-warn: ignoring syscall time(4026526872, 409, ...)
-warn: ignoring syscall time(4026526848, 409, ...)
-warn: ignoring syscall time(4026526840, 409, ...)
-warn: ignoring syscall time(4026526872, 409, ...)
-warn: ignoring syscall time(4026526856, 409, ...)
-warn: ignoring syscall time(4026526848, 409, ...)
-warn: ignoring syscall time(4026526936, 409, ...)
-warn: ignoring syscall time(4026527008, 4026527408, ...)
-warn: ignoring syscall time(4026526560, 1375098, ...)
-warn: ignoring syscall time(4026527184, 18732, ...)
-warn: ignoring syscall time(4026526632, 409, ...)
-warn: ignoring syscall time(4026526736, 0, ...)
-warn: ignoring syscall time(4026527320, 0, ...)
-warn: ignoring syscall time(4026527744, 225, ...)
-warn: ignoring syscall time(4026527048, 409, ...)
-warn: ignoring syscall time(4026526856, 409, ...)
-warn: ignoring syscall time(4026526872, 409, ...)
-warn: ignoring syscall time(4026527096, 4026527496, ...)
-warn: ignoring syscall time(4026526648, 1375098, ...)
-warn: ignoring syscall time(4026526824, 0, ...)
-warn: ignoring syscall time(4026527320, 0, ...)
-warn: ignoring syscall time(4026527184, 1879089152, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall time(4026527472, 1595768, ...)
-warn: ignoring syscall time(4026526912, 17300, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026526912, 19045, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026526912, 19045, ...)
-warn: ignoring syscall time(4026526912, 17300, ...)
-warn: ignoring syscall time(4026525968, 20500, ...)
-warn: ignoring syscall time(4026525968, 4026526436, ...)
-warn: ignoring syscall time(4026526056, 7004192, ...)
-warn: ignoring syscall time(4026527512, 4, ...)
-warn: ignoring syscall time(4026525760, 0, ...)
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:55:47
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 68148678500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1344201 # Simulator instruction rate (inst/s)
-host_mem_usage 212228 # Number of bytes of host memory used
-host_seconds 101.28 # Real time elapsed on the host
-host_tick_rate 2025263348 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 136139203 # Number of instructions simulated
-sim_seconds 0.205117 # Number of seconds simulated
-sim_ticks 205116920000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses
-system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 57940701 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 154904 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 146582 # number of replacements
-system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4087.433110 # Cycle average of tags in use
-system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 821750000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 107271 # number of writebacks
-system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 727.750385 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
-system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses
-system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 136106788 # number of overall hits
-system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses
-system.cpu.icache.overall_misses 187024 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 184976 # number of replacements
-system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 2004.068304 # Cycle average of tags in use
-system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 146097762000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 5469308000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4207160000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 2066792000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1589840000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 220896000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 107271 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.433849 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 7536100000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 192777 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 144925 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 120486 # number of replacements
-system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 19311.746813 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 87413 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 410233840 # number of cpu cycles simulated
-system.cpu.num_insts 136139203 # Number of instructions executed
-system.cpu.num_refs 58160249 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: ignoring syscall time(4026527848, 4026528248, ...)
+warn: ignoring syscall time(4026527400, 1375098, ...)
+warn: ignoring syscall time(4026527312, 1, ...)
+warn: ignoring syscall time(4026527048, 413, ...)
+warn: ignoring syscall time(4026527048, 414, ...)
+warn: ignoring syscall time(4026527288, 4026527688, ...)
+warn: ignoring syscall time(4026526840, 1375098, ...)
+warn: Increasing stack size by one page.
+warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(4026526960, 409, ...)
+warn: ignoring syscall time(4026527040, 409, ...)
+warn: ignoring syscall time(4026527000, 409, ...)
+warn: ignoring syscall time(4026526984, 409, ...)
+warn: ignoring syscall time(4026526984, 409, ...)
+warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(4026526312, 19045, ...)
+warn: ignoring syscall time(4026526832, 409, ...)
+warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(4026526840, 409, ...)
+warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(4026526936, 409, ...)
+warn: ignoring syscall time(4026527008, 4026527408, ...)
+warn: ignoring syscall time(4026526560, 1375098, ...)
+warn: ignoring syscall time(4026527184, 18732, ...)
+warn: ignoring syscall time(4026526632, 409, ...)
+warn: ignoring syscall time(4026526736, 0, ...)
+warn: ignoring syscall time(4026527320, 0, ...)
+warn: ignoring syscall time(4026527744, 225, ...)
+warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(4026526872, 409, ...)
+warn: ignoring syscall time(4026527096, 4026527496, ...)
+warn: ignoring syscall time(4026526648, 1375098, ...)
+warn: ignoring syscall time(4026526824, 0, ...)
+warn: ignoring syscall time(4026527320, 0, ...)
+warn: ignoring syscall time(4026527184, 1879089152, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall times(4026527728, 246, ...)
+warn: ignoring syscall time(4026527472, 1595768, ...)
+warn: ignoring syscall time(4026526912, 17300, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026526912, 19045, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026527472, 0, ...)
+warn: ignoring syscall time(4026526912, 19045, ...)
+warn: ignoring syscall time(4026526912, 17300, ...)
+warn: ignoring syscall time(4026525968, 20500, ...)
+warn: ignoring syscall time(4026525968, 4026526436, ...)
+warn: ignoring syscall time(4026526056, 7004192, ...)
+warn: ignoring syscall time(4026527512, 4, ...)
+warn: ignoring syscall time(4026525760, 0, ...)
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:43:57
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 205116920000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1344201 # Simulator instruction rate (inst/s)
+host_mem_usage 212228 # Number of bytes of host memory used
+host_seconds 101.28 # Real time elapsed on the host
+host_tick_rate 2025263348 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 136139203 # Number of instructions simulated
+sim_seconds 0.205117 # Number of seconds simulated
+sim_ticks 205116920000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 57940701 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 154904 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 146582 # number of replacements
+system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4087.433110 # Cycle average of tags in use
+system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 821750000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 107271 # number of writebacks
+system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 727.750385 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
+system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses
+system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 136106788 # number of overall hits
+system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses
+system.cpu.icache.overall_misses 187024 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 184976 # number of replacements
+system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 2004.068304 # Cycle average of tags in use
+system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 146097762000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 5469308000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4207160000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 2066792000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1589840000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 220896000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 107271 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 1.433849 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 7536100000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 192777 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 144925 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 120486 # number of replacements
+system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 19311.746813 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 87413 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 410233840 # number of cpu cycles simulated
+system.cpu.num_insts 136139203 # Number of instructions executed
+system.cpu.num_refs 58160249 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
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-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall times(4026527728, 246, ...)
-warn: ignoring syscall time(4026527472, 1595768, ...)
-warn: ignoring syscall time(4026526912, 17300, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026526912, 19045, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026527472, 0, ...)
-warn: ignoring syscall time(4026526912, 19045, ...)
-warn: ignoring syscall time(4026526912, 17300, ...)
-warn: ignoring syscall time(4026525968, 20500, ...)
-warn: ignoring syscall time(4026525968, 4026526436, ...)
-warn: ignoring syscall time(4026526056, 7004192, ...)
-warn: ignoring syscall time(4026527512, 4, ...)
-warn: ignoring syscall time(4026525760, 0, ...)
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:43:57
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 205116920000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 312845737 # Number of BTB hits
-global.BPredUnit.BTBLookups 319575559 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 19647325 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted
-global.BPredUnit.lookups 345502589 # Number of BP lookups
-global.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target.
-host_inst_rate 178472 # Simulator instruction rate (inst/s)
-host_mem_usage 202004 # Number of bytes of host memory used
-host_seconds 9727.25 # Real time elapsed on the host
-host_tick_rate 76312348 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 67515291 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 234046222 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1736043781 # Number of instructions simulated
-sim_seconds 0.742309 # Number of seconds simulated
-sim_ticks 742309425500 # Number of ticks simulated
-system.cpu.commit.COM:branches 214632552 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 62782585 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 1379215338
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 736540830 5340.29%
- 1 260049504 1885.49%
- 2 126970462 920.60%
- 3 77723426 563.53%
- 4 51327439 372.15%
- 5 27759546 201.27%
- 6 26179568 189.81%
- 7 9881978 71.65%
- 8 62782585 455.21%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 1819780126 # Number of instructions committed
-system.cpu.commit.COM:loads 445666361 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 606571343 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 19646824 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 627314235 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
-system.cpu.cpi 0.855174 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.855174 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses 523259964 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 16887.792500 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11267.111116 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 512954316 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 174039645000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.019695 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 10305648 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 3030509 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 81969799500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.013903 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7275139 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 33917.187245 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.824123 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 155297498 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 184204379594 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.033790 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 5431004 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 3182477 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 83541376693 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 2248527 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 6337.465393 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 31613.485382 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 73.053349 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 156253 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 65330 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 990247980 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 2065309000 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 683988466 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 22764.945466 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 668251814 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 358244024594 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.023007 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 15736652 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 6212986 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 165511176193 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.013924 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9523666 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 683988466 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 22764.945466 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 668251814 # number of overall hits
-system.cpu.dcache.overall_miss_latency 358244024594 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.023007 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 15736652 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 6212986 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 165511176193 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.013924 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9523666 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 9155775 # number of replacements
-system.cpu.dcache.sampled_refs 9159871 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4079.315794 # Cycle average of tags in use
-system.cpu.dcache.total_refs 669159251 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 7089291000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2245449 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 98604488 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 553 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 54363606 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 2810650778 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 726334611 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 549143104 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 93084202 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 1641 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 5133136 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 768331639 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 752318838 # DTB hits
-system.cpu.dtb.misses 16012801 # DTB misses
-system.cpu.dtb.read_accesses 566617551 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 557381525 # DTB read hits
-system.cpu.dtb.read_misses 9236026 # DTB read misses
-system.cpu.dtb.write_accesses 201714088 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 194937313 # DTB write hits
-system.cpu.dtb.write_misses 6776775 # DTB write misses
-system.cpu.fetch.Branches 345502589 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 355180518 # Number of cache lines fetched
-system.cpu.fetch.Cycles 920206770 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 7941781 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 2863046502 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 28103166 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.232721 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 355180518 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 336596037 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.928472 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 1472299541
-system.cpu.fetch.rateDist.min_value 0
- 0 907273323 6162.29%
- 1 47886355 325.25%
- 2 34613456 235.10%
- 3 52095475 353.84%
- 4 125971058 855.61%
- 5 69335096 470.93%
- 6 50458684 342.72%
- 7 40993758 278.43%
- 8 143672336 975.84%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 355180518 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35446.920583 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35464.523282 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 355179284 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 43741500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1234 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 31989000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 393768.607539 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 355180518 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35446.920583 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency
-system.cpu.icache.demand_hits 355179284 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 43741500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1234 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 31989000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 355180518 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 355179284 # number of overall hits
-system.cpu.icache.overall_miss_latency 43741500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1234 # number of overall misses
-system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 31989000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 711.425375 # Cycle average of tags in use
-system.cpu.icache.total_refs 355179284 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 12319311 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 282186314 # Number of branches executed
-system.cpu.iew.EXEC:nop 128796557 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.535065 # Inst execution rate
-system.cpu.iew.EXEC:refs 769619324 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 201925301 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1531990762 # num instructions consuming a value
-system.cpu.iew.WB:count 2240290242 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.811831 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1243717865 # num instructions producing a value
-system.cpu.iew.WB:rate 1.509000 # insts written-back per cycle
-system.cpu.iew.WB:sent 2261678939 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 21342134 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 17373691 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 621608435 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 22154841 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 234046222 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 2621719109 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 567694023 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 36858073 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 2278986827 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 339653 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 40208 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 93084202 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 758573 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 361643 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 33889596 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 220185 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 3031505 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 175942074 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 73141240 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 3031505 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 703796 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 20638338 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 2315844900 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 0 0.00% # Type of FU issued
- IntAlu 1532920254 66.19% # Type of FU issued
- IntMult 99 0.00% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 234 0.00% # Type of FU issued
- FloatCmp 20 0.00% # Type of FU issued
- FloatCvt 143 0.00% # Type of FU issued
- FloatMult 16 0.00% # Type of FU issued
- FloatDiv 24 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 577889733 24.95% # Type of FU issued
- MemWrite 205034377 8.85% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 14393569 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.006215 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 2738956 19.03% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 9224843 64.09% # attempts to use FU when none available
- MemWrite 2429770 16.88% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 1472299541
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 577695763 3923.77%
- 1 271543756 1844.35%
- 2 242868170 1649.58%
- 3 139713874 948.95%
- 4 122021082 828.78%
- 5 69652698 473.09%
- 6 39670196 269.44%
- 7 8017828 54.46%
- 8 1116174 7.58%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate
-system.cpu.iq.iqInstsAdded 2492922509 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 2315844900 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 739697610 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 1501741 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 329349456 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 355180552 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 355180518 # ITB hits
-system.cpu.itb.misses 34 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 1884731 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.251241 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.593787 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 65231013432 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1884731 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 59294756388 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1884731 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 7276042 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34304.499446 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.330859 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5387454 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 64787066000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.259563 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1888588 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 58807478000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259563 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1888588 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 363811 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34327.098007 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31261.459167 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 12488575853 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 363811 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11373262721 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 363811 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 2245449 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2245449 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs 11899.405570 # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.417950 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 39818 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 473810531 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 9160773 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34457.219077 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 5387454 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 130018079432 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.411900 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 3773319 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 118102234388 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.411900 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 3773319 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 9160773 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 5387454 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 130018079432 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.411900 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 3773319 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 118102234388 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.411900 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 3773319 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 2759426 # number of replacements
-system.cpu.l2cache.sampled_refs 2784020 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 25902.034914 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 6731622 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 154290039500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1195718 # number of writebacks
-system.cpu.numCycles 1484618852 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 68342801 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 5307310 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 744648238 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 20682075 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 1073015 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 3556218340 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 2749142928 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 2059304862 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 535957522 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 93084202 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 30265720 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 683101899 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 1058 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 46 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 60936722 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 44 # count of temporary serializing insts renamed
-system.cpu.timesIdled 457423 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:46
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 312845737 # Number of BTB hits
+global.BPredUnit.BTBLookups 319575559 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 19647325 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted
+global.BPredUnit.lookups 345502589 # Number of BP lookups
+global.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target.
+host_inst_rate 178472 # Simulator instruction rate (inst/s)
+host_mem_usage 202004 # Number of bytes of host memory used
+host_seconds 9727.25 # Real time elapsed on the host
+host_tick_rate 76312348 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 67515291 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 234046222 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1736043781 # Number of instructions simulated
+sim_seconds 0.742309 # Number of seconds simulated
+sim_ticks 742309425500 # Number of ticks simulated
+system.cpu.commit.COM:branches 214632552 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 62782585 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 1379215338
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 736540830 5340.29%
+ 1 260049504 1885.49%
+ 2 126970462 920.60%
+ 3 77723426 563.53%
+ 4 51327439 372.15%
+ 5 27759546 201.27%
+ 6 26179568 189.81%
+ 7 9881978 71.65%
+ 8 62782585 455.21%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 1819780126 # Number of instructions committed
+system.cpu.commit.COM:loads 445666361 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 606571343 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 19646824 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 627314235 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
+system.cpu.cpi 0.855174 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.855174 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 523259964 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 16887.792500 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11267.111116 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 512954316 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 174039645000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.019695 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 10305648 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 3030509 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 81969799500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.013903 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7275139 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 33917.187245 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.824123 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 155297498 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 184204379594 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.033790 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 5431004 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 3182477 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 83541376693 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 2248527 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 6337.465393 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 31613.485382 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 73.053349 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 156253 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 65330 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 990247980 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 2065309000 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 683988466 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 22764.945466 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 668251814 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 358244024594 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.023007 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 15736652 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 6212986 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 165511176193 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.013924 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9523666 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 683988466 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 22764.945466 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 668251814 # number of overall hits
+system.cpu.dcache.overall_miss_latency 358244024594 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.023007 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 15736652 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 6212986 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 165511176193 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.013924 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9523666 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 9155775 # number of replacements
+system.cpu.dcache.sampled_refs 9159871 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4079.315794 # Cycle average of tags in use
+system.cpu.dcache.total_refs 669159251 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 7089291000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2245449 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 98604488 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 553 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 54363606 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 2810650778 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 726334611 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 549143104 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 93084202 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1641 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 5133136 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 768331639 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 752318838 # DTB hits
+system.cpu.dtb.misses 16012801 # DTB misses
+system.cpu.dtb.read_accesses 566617551 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 557381525 # DTB read hits
+system.cpu.dtb.read_misses 9236026 # DTB read misses
+system.cpu.dtb.write_accesses 201714088 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 194937313 # DTB write hits
+system.cpu.dtb.write_misses 6776775 # DTB write misses
+system.cpu.fetch.Branches 345502589 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 355180518 # Number of cache lines fetched
+system.cpu.fetch.Cycles 920206770 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 7941781 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 2863046502 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 28103166 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.232721 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 355180518 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 336596037 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.928472 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 1472299541
+system.cpu.fetch.rateDist.min_value 0
+ 0 907273323 6162.29%
+ 1 47886355 325.25%
+ 2 34613456 235.10%
+ 3 52095475 353.84%
+ 4 125971058 855.61%
+ 5 69335096 470.93%
+ 6 50458684 342.72%
+ 7 40993758 278.43%
+ 8 143672336 975.84%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 355180518 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35446.920583 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35464.523282 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 355179284 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 43741500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1234 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 31989000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 393768.607539 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 355180518 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35446.920583 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency
+system.cpu.icache.demand_hits 355179284 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 43741500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1234 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 31989000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 355180518 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 355179284 # number of overall hits
+system.cpu.icache.overall_miss_latency 43741500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1234 # number of overall misses
+system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 31989000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 711.425375 # Cycle average of tags in use
+system.cpu.icache.total_refs 355179284 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 12319311 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 282186314 # Number of branches executed
+system.cpu.iew.EXEC:nop 128796557 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.535065 # Inst execution rate
+system.cpu.iew.EXEC:refs 769619324 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 201925301 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 1531990762 # num instructions consuming a value
+system.cpu.iew.WB:count 2240290242 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.811831 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 1243717865 # num instructions producing a value
+system.cpu.iew.WB:rate 1.509000 # insts written-back per cycle
+system.cpu.iew.WB:sent 2261678939 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 21342134 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 17373691 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 621608435 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 22154841 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 234046222 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 2621719109 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 567694023 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 36858073 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2278986827 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 339653 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 40208 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 93084202 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 758573 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 361643 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 33889596 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 220185 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 3031505 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 175942074 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 73141240 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 3031505 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 703796 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 20638338 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 2315844900 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 0 0.00% # Type of FU issued
+ IntAlu 1532920254 66.19% # Type of FU issued
+ IntMult 99 0.00% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 234 0.00% # Type of FU issued
+ FloatCmp 20 0.00% # Type of FU issued
+ FloatCvt 143 0.00% # Type of FU issued
+ FloatMult 16 0.00% # Type of FU issued
+ FloatDiv 24 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 577889733 24.95% # Type of FU issued
+ MemWrite 205034377 8.85% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 14393569 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.006215 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 2738956 19.03% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 9224843 64.09% # attempts to use FU when none available
+ MemWrite 2429770 16.88% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 1472299541
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 577695763 3923.77%
+ 1 271543756 1844.35%
+ 2 242868170 1649.58%
+ 3 139713874 948.95%
+ 4 122021082 828.78%
+ 5 69652698 473.09%
+ 6 39670196 269.44%
+ 7 8017828 54.46%
+ 8 1116174 7.58%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate
+system.cpu.iq.iqInstsAdded 2492922509 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 2315844900 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 739697610 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 1501741 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 329349456 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 355180552 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 355180518 # ITB hits
+system.cpu.itb.misses 34 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 1884731 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.251241 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.593787 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 65231013432 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1884731 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 59294756388 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1884731 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 7276042 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34304.499446 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.330859 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5387454 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 64787066000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.259563 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 1888588 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 58807478000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259563 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 1888588 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 363811 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34327.098007 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31261.459167 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 12488575853 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 363811 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11373262721 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 363811 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 2245449 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 2245449 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs 11899.405570 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 2.417950 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 39818 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 473810531 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 9160773 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34457.219077 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 5387454 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 130018079432 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.411900 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 3773319 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 118102234388 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.411900 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 3773319 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 9160773 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 5387454 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 130018079432 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.411900 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 3773319 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 118102234388 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.411900 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 3773319 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 2759426 # number of replacements
+system.cpu.l2cache.sampled_refs 2784020 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 25902.034914 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 6731622 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 154290039500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1195718 # number of writebacks
+system.cpu.numCycles 1484618852 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 68342801 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 5307310 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 744648238 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 20682075 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 1073015 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 3556218340 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 2749142928 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2059304862 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 535957522 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 93084202 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 30265720 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 683101899 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 1058 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 46 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 60936722 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 44 # count of temporary serializing insts renamed
+system.cpu.timesIdled 457423 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:46
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 3337847 # Simulator instruction rate (inst/s)
-host_mem_usage 193672 # Number of bytes of host memory used
-host_seconds 545.20 # Real time elapsed on the host
-host_tick_rate 1674974438 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1819780127 # Number of instructions simulated
-sim_seconds 0.913189 # Number of seconds simulated
-sim_ticks 913189263000 # Number of ticks simulated
-system.cpu.dtb.accesses 611922547 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 605324165 # DTB hits
-system.cpu.dtb.misses 6598382 # DTB misses
-system.cpu.dtb.read_accesses 449492741 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 444595663 # DTB read hits
-system.cpu.dtb.read_misses 4897078 # DTB read misses
-system.cpu.dtb.write_accesses 162429806 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 160728502 # DTB write hits
-system.cpu.dtb.write_misses 1701304 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 1826378527 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 1826378509 # ITB hits
-system.cpu.itb.misses 18 # ITB misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1826378527 # number of cpu cycles simulated
-system.cpu.num_insts 1819780127 # Number of instructions executed
-system.cpu.num_refs 613169725 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 3337847 # Simulator instruction rate (inst/s)
+host_mem_usage 193672 # Number of bytes of host memory used
+host_seconds 545.20 # Real time elapsed on the host
+host_tick_rate 1674974438 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1819780127 # Number of instructions simulated
+sim_seconds 0.913189 # Number of seconds simulated
+sim_ticks 913189263000 # Number of ticks simulated
+system.cpu.dtb.accesses 611922547 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 605324165 # DTB hits
+system.cpu.dtb.misses 6598382 # DTB misses
+system.cpu.dtb.read_accesses 449492741 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 444595663 # DTB read hits
+system.cpu.dtb.read_misses 4897078 # DTB read misses
+system.cpu.dtb.write_accesses 162429806 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 160728502 # DTB write hits
+system.cpu.dtb.write_misses 1701304 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 1826378527 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 1826378509 # ITB hits
+system.cpu.itb.misses 18 # ITB misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1826378527 # number of cpu cycles simulated
+system.cpu.num_insts 1819780127 # Number of instructions executed
+system.cpu.num_refs 613169725 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:45
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1294592 # Simulator instruction rate (inst/s)
-host_mem_usage 201124 # Number of bytes of host memory used
-host_seconds 1405.68 # Real time elapsed on the host
-host_tick_rate 1940692275 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1819780127 # Number of instructions simulated
-sim_seconds 2.727991 # Number of seconds simulated
-sim_ticks 2727990505000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24899.898843 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21899.898843 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 179837378000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 158170136000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.842958 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.842958 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 125876559000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 305713937000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 277303289000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 595853949 # number of overall hits
-system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 9470216 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 277303289000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 9107638 # number of replacements
-system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4079.892573 # Cycle average of tags in use
-system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2244708 # number of writebacks
-system.cpu.dtb.accesses 611922547 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 605324165 # DTB hits
-system.cpu.dtb.misses 6598382 # DTB misses
-system.cpu.dtb.read_accesses 449492741 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 444595663 # DTB read hits
-system.cpu.dtb.read_misses 4897078 # DTB read misses
-system.cpu.dtb.write_accesses 162429806 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 160728502 # DTB write hits
-system.cpu.dtb.write_misses 1701304 # DTB write misses
-system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
-system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1826377708 # number of overall hits
-system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
-system.cpu.icache.overall_misses 802 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 611.737435 # Cycle average of tags in use
-system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 1826378528 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 1826378510 # ITB hits
-system.cpu.itb.misses 18 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 98244640000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 75572800000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 97508996000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 75006920000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51948.795198 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 18622708000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14339280000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 195753636000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 150579720000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 5348043 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 3764493 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 150579720000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 2751986 # number of replacements
-system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 25365.544087 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 605789077000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1194738 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 5455981010 # number of cpu cycles simulated
-system.cpu.num_insts 1819780127 # Number of instructions executed
-system.cpu.num_refs 613169725 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1294592 # Simulator instruction rate (inst/s)
+host_mem_usage 201124 # Number of bytes of host memory used
+host_seconds 1405.68 # Real time elapsed on the host
+host_tick_rate 1940692275 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1819780127 # Number of instructions simulated
+sim_seconds 2.727991 # Number of seconds simulated
+sim_ticks 2727990505000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 24899.898843 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21899.898843 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 179837378000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 158170136000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.842958 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.842958 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 125876559000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 305713937000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 277303289000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 595853949 # number of overall hits
+system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9470216 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 277303289000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 9107638 # number of replacements
+system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4079.892573 # Cycle average of tags in use
+system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2244708 # number of writebacks
+system.cpu.dtb.accesses 611922547 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 605324165 # DTB hits
+system.cpu.dtb.misses 6598382 # DTB misses
+system.cpu.dtb.read_accesses 449492741 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 444595663 # DTB read hits
+system.cpu.dtb.read_misses 4897078 # DTB read misses
+system.cpu.dtb.write_accesses 162429806 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 160728502 # DTB write hits
+system.cpu.dtb.write_misses 1701304 # DTB write misses
+system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
+system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1826377708 # number of overall hits
+system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
+system.cpu.icache.overall_misses 802 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 611.737435 # Cycle average of tags in use
+system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 1826378528 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 1826378510 # ITB hits
+system.cpu.itb.misses 18 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 98244640000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 75572800000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 97508996000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 75006920000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51948.795198 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 18622708000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14339280000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 195753636000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 150579720000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 5348043 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 3764493 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 150579720000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 2751986 # number of replacements
+system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 25365.544087 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 605789077000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1194738 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 5455981010 # number of cpu cycles simulated
+system.cpu.num_insts 1819780127 # Number of instructions executed
+system.cpu.num_refs 613169725 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:45
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 2012716 # Simulator instruction rate (inst/s)
-host_mem_usage 194900 # Number of bytes of host memory used
-host_seconds 2311.91 # Real time elapsed on the host
-host_tick_rate 1226349708 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 4653219791 # Number of instructions simulated
-sim_seconds 2.835211 # Number of seconds simulated
-sim_ticks 2835210954000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 5670421909 # number of cpu cycles simulated
-system.cpu.num_insts 4653219791 # Number of instructions executed
-system.cpu.num_refs 1686313781 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 23:03:02
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 23:38:14
+M5 executing on zizzer
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 2835210954000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2012716 # Simulator instruction rate (inst/s)
+host_mem_usage 194900 # Number of bytes of host memory used
+host_seconds 2311.91 # Real time elapsed on the host
+host_tick_rate 1226349708 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 4653219791 # Number of instructions simulated
+sim_seconds 2.835211 # Number of seconds simulated
+sim_ticks 2835210954000 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 5670421909 # number of cpu cycles simulated
+system.cpu.num_insts 4653219791 # Number of instructions executed
+system.cpu.num_refs 1686313781 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 23:03:02
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 23:38:14
-M5 executing on zizzer
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 2835210954000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1139442 # Simulator instruction rate (inst/s)
-host_mem_usage 201800 # Number of bytes of host memory used
-host_seconds 4083.77 # Real time elapsed on the host
-host_tick_rate 1872105757 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 4653219791 # Number of instructions simulated
-sim_seconds 7.645253 # Number of seconds simulated
-sim_ticks 7645253019000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1231961294 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 180714156000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 7223448 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 159043812000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7223448 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.834453 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.834453 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 436281234 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 125837340000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2247102 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1668242528 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 306551496000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 9470550 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 278139846000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9470550 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1668242528 # number of overall hits
-system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 9470550 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 278139846000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 9108982 # number of replacements
-system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4084.377273 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 78020914000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2244013 # number of writebacks
-system.cpu.icache.ReadReq_accesses 5670421871 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 5670421196 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 8400623.994074 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 5670421871 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.demand_hits 5670421196 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
-system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 5670421871 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 5670421196 # number of overall hits
-system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
-system.cpu.icache.overall_misses 675 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 10 # number of replacements
-system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 555.334497 # Cycle average of tags in use
-system.cpu.icache.total_refs 5670421196 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 1889630 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 98260760000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1889630 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 75585200000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1889630 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 7224123 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5328546 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 98570004000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.262395 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1895577 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 75823080000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262395 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1895577 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 357472 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51945.886671 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 18569200000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 357472 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14298880000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 5328546 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 196830764000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.415329 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 3785207 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 151408280000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.415329 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 3785207 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 5328546 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 3785207 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 151408280000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 2772128 # number of replacements
-system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 25740.148147 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 6038911398000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1199171 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 15290506038 # number of cpu cycles simulated
-system.cpu.num_insts 4653219791 # Number of instructions executed
-system.cpu.num_refs 1686313781 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 7 2008 03:21:37
+M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5
+M5 commit date Thu Nov 06 23:13:50 2008 -0800
+M5 started Nov 8 2008 10:43:38
+M5 executing on tater
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 7645253019000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1139442 # Simulator instruction rate (inst/s)
+host_mem_usage 201800 # Number of bytes of host memory used
+host_seconds 4083.77 # Real time elapsed on the host
+host_tick_rate 1872105757 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 4653219791 # Number of instructions simulated
+sim_seconds 7.645253 # Number of seconds simulated
+sim_ticks 7645253019000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1231961294 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 180714156000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 7223448 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 159043812000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7223448 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.834453 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.834453 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 436281234 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 125837340000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2247102 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1668242528 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 306551496000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9470550 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 278139846000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9470550 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 1668242528 # number of overall hits
+system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9470550 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 278139846000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9470550 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 9108982 # number of replacements
+system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4084.377273 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 78020914000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2244013 # number of writebacks
+system.cpu.icache.ReadReq_accesses 5670421871 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 5670421196 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 8400623.994074 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 5670421871 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.demand_hits 5670421196 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
+system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 5670421871 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 5670421196 # number of overall hits
+system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
+system.cpu.icache.overall_misses 675 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 10 # number of replacements
+system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 555.334497 # Cycle average of tags in use
+system.cpu.icache.total_refs 5670421196 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses 1889630 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 98260760000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1889630 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 75585200000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1889630 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 7224123 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5328546 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 98570004000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.262395 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 1895577 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 75823080000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262395 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 1895577 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 357472 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51945.886671 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 18569200000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 357472 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14298880000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 5328546 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 196830764000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.415329 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 3785207 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 151408280000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.415329 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 3785207 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 5328546 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 3785207 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 151408280000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.415329 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 3785207 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 2772128 # number of replacements
+system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 25740.148147 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 6038911398000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1199171 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 15290506038 # number of cpu cycles simulated
+system.cpu.num_insts 4653219791 # Number of instructions executed
+system.cpu.num_refs 1686313781 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 7 2008 03:21:37
-M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5
-M5 commit date Thu Nov 06 23:13:50 2008 -0800
-M5 started Nov 8 2008 10:43:38
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/x86/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
-Exiting @ tick 7645253019000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 13008791 # Number of BTB hits
-global.BPredUnit.BTBLookups 16964874 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted
-global.BPredUnit.lookups 19468548 # Number of BP lookups
-global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target.
-host_inst_rate 123995 # Simulator instruction rate (inst/s)
-host_mem_usage 207276 # Number of bytes of host memory used
-host_seconds 678.90 # Real time elapsed on the host
-host_tick_rate 60124800 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 10628051 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 84179709 # Number of instructions simulated
-sim_seconds 0.040819 # Number of seconds simulated
-sim_ticks 40818658500 # Number of ticks simulated
-system.cpu.commit.COM:branches 10240685 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 73457196
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 36278941 4938.79%
- 1 18156304 2471.68%
- 2 7455517 1014.95%
- 3 3880419 528.26%
- 4 2046448 278.59%
- 5 1301140 177.13%
- 6 721823 98.26%
- 7 760802 103.57%
- 8 2855802 388.77%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 91903055 # Number of instructions committed
-system.cpu.commit.COM:loads 20034413 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 26537108 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 1933797 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 56152215 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 84179709 # Number of Instructions Simulated
-system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
-system.cpu.cpi 0.969798 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.969798 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 30623.414072 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32082.015810 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 26550500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 16233500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 35738.919918 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36175.579146 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6492799 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 296775991 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.001277 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 8304 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 2649.700000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 26497 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 323326491 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 83194497 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 29894354 # number of overall hits
-system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 9171 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 83194497 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 159 # number of replacements
-system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1458.398369 # Cycle average of tags in use
-system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 105 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 3781084 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 39569074 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 31911121 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 31454022 # DTB hits
-system.cpu.dtb.misses 457099 # DTB misses
-system.cpu.dtb.read_accesses 24718123 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 24262026 # DTB read hits
-system.cpu.dtb.read_misses 456097 # DTB read misses
-system.cpu.dtb.write_accesses 7192998 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 7191996 # DTB write hits
-system.cpu.dtb.write_misses 1002 # DTB write misses
-system.cpu.fetch.Branches 19468548 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 19230003 # Number of cache lines fetched
-system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 2079597 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 81528343
-system.cpu.fetch.rateDist.min_value 0
- 0 50560378 6201.57%
- 1 3114212 381.98%
- 2 2012618 246.86%
- 3 3505366 429.96%
- 4 4590613 563.07%
- 5 1506961 184.84%
- 6 2028359 248.79%
- 7 1846743 226.52%
- 8 12363093 1516.42%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 19218965 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 174210000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 11038 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 982 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency
-system.cpu.icache.demand_hits 19218965 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 174210000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000574 # miss rate for demand accesses
-system.cpu.icache.demand_misses 11038 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 982 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 119809000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 10056 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 19218965 # number of overall hits
-system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses
-system.cpu.icache.overall_misses 11038 # number of overall misses
-system.cpu.icache.overall_mshr_hits 982 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 119809000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 8143 # number of replacements
-system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1543.991602 # Cycle average of tags in use
-system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 108975 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 12812003 # Number of branches executed
-system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate
-system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 7194632 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 90937302 # num instructions consuming a value
-system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 65837672 # num instructions producing a value
-system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle
-system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 254811 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 33976826 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 426 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 1734651 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 10628051 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 148053720 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 24767884 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2184370 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 101844271 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 121216 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 8071146 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 160195 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 849805 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 2830 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 248254 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 9784 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 13942413 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 4125356 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 248254 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 218646 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 104028641 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 7 0.00% # Type of FU issued
- IntAlu 64430040 61.93% # Type of FU issued
- IntMult 475055 0.46% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2782164 2.67% # Type of FU issued
- FloatCmp 115645 0.11% # Type of FU issued
- FloatCvt 2377276 2.29% # Type of FU issued
- FloatMult 305748 0.29% # Type of FU issued
- FloatDiv 755245 0.73% # Type of FU issued
- FloatSqrt 323 0.00% # Type of FU issued
- MemRead 25462424 24.48% # Type of FU issued
- MemWrite 7324714 7.04% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 274346 14.19% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 31 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 6547 0.34% # attempts to use FU when none available
- FloatMult 2333 0.12% # attempts to use FU when none available
- FloatDiv 832912 43.09% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 743147 38.44% # attempts to use FU when none available
- MemWrite 73812 3.82% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 81528343
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 35305774 4330.49%
- 1 18904885 2318.81%
- 2 11574997 1419.75%
- 3 6762756 829.50%
- 4 5075415 622.53%
- 5 2394533 293.71%
- 6 1208963 148.29%
- 7 250769 30.76%
- 8 50251 6.16%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate
-system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 426 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 50669408 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 19230073 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 19230003 # ITB hits
-system.cpu.itb.misses 70 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 60179000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34278.222222 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 115689000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 104895000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34390.243902 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.162602 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 4230000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3845000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs 1500 # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 3000 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 175868000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 159585500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 7186 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 5110 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 159585500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2244.769579 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 81637318 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 40833183 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 115929564 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 28833296 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 8071146 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 2024389 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 47502203 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 5305 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 457 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 4572167 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 446 # count of temporary serializing insts renamed
-system.cpu.timesIdled 2428 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:29:52
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124
\ No newline at end of file
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 13008791 # Number of BTB hits
+global.BPredUnit.BTBLookups 16964874 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted
+global.BPredUnit.lookups 19468548 # Number of BP lookups
+global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target.
+host_inst_rate 123995 # Simulator instruction rate (inst/s)
+host_mem_usage 207276 # Number of bytes of host memory used
+host_seconds 678.90 # Real time elapsed on the host
+host_tick_rate 60124800 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 10628051 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 84179709 # Number of instructions simulated
+sim_seconds 0.040819 # Number of seconds simulated
+sim_ticks 40818658500 # Number of ticks simulated
+system.cpu.commit.COM:branches 10240685 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 73457196
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 36278941 4938.79%
+ 1 18156304 2471.68%
+ 2 7455517 1014.95%
+ 3 3880419 528.26%
+ 4 2046448 278.59%
+ 5 1301140 177.13%
+ 6 721823 98.26%
+ 7 760802 103.57%
+ 8 2855802 388.77%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 91903055 # Number of instructions committed
+system.cpu.commit.COM:loads 20034413 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 26537108 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 1933797 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 56152215 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 84179709 # Number of Instructions Simulated
+system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
+system.cpu.cpi 0.969798 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.969798 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 30623.414072 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32082.015810 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 26550500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 16233500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 35738.919918 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36175.579146 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6492799 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 296775991 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.001277 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 8304 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 2649.700000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 26497 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 323326491 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 83194497 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 29894354 # number of overall hits
+system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9171 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 83194497 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 159 # number of replacements
+system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 1458.398369 # Cycle average of tags in use
+system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 105 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 3781084 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 39569074 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 31911121 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 31454022 # DTB hits
+system.cpu.dtb.misses 457099 # DTB misses
+system.cpu.dtb.read_accesses 24718123 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 24262026 # DTB read hits
+system.cpu.dtb.read_misses 456097 # DTB read misses
+system.cpu.dtb.write_accesses 7192998 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 7191996 # DTB write hits
+system.cpu.dtb.write_misses 1002 # DTB write misses
+system.cpu.fetch.Branches 19468548 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 19230003 # Number of cache lines fetched
+system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 2079597 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 81528343
+system.cpu.fetch.rateDist.min_value 0
+ 0 50560378 6201.57%
+ 1 3114212 381.98%
+ 2 2012618 246.86%
+ 3 3505366 429.96%
+ 4 4590613 563.07%
+ 5 1506961 184.84%
+ 6 2028359 248.79%
+ 7 1846743 226.52%
+ 8 12363093 1516.42%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 19218965 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 174210000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 11038 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 982 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency
+system.cpu.icache.demand_hits 19218965 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 174210000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000574 # miss rate for demand accesses
+system.cpu.icache.demand_misses 11038 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 982 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 119809000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 10056 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 19218965 # number of overall hits
+system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses
+system.cpu.icache.overall_misses 11038 # number of overall misses
+system.cpu.icache.overall_mshr_hits 982 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 119809000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 8143 # number of replacements
+system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1543.991602 # Cycle average of tags in use
+system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 108975 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 12812003 # Number of branches executed
+system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate
+system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 7194632 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 90937302 # num instructions consuming a value
+system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 65837672 # num instructions producing a value
+system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle
+system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 254811 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 33976826 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 426 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1734651 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 10628051 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 148053720 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 24767884 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2184370 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 101844271 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 121216 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 8071146 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 160195 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 849805 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 2830 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 248254 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 9784 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 13942413 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 4125356 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 248254 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 218646 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 104028641 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 7 0.00% # Type of FU issued
+ IntAlu 64430040 61.93% # Type of FU issued
+ IntMult 475055 0.46% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2782164 2.67% # Type of FU issued
+ FloatCmp 115645 0.11% # Type of FU issued
+ FloatCvt 2377276 2.29% # Type of FU issued
+ FloatMult 305748 0.29% # Type of FU issued
+ FloatDiv 755245 0.73% # Type of FU issued
+ FloatSqrt 323 0.00% # Type of FU issued
+ MemRead 25462424 24.48% # Type of FU issued
+ MemWrite 7324714 7.04% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 274346 14.19% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 31 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 6547 0.34% # attempts to use FU when none available
+ FloatMult 2333 0.12% # attempts to use FU when none available
+ FloatDiv 832912 43.09% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 743147 38.44% # attempts to use FU when none available
+ MemWrite 73812 3.82% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 81528343
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 35305774 4330.49%
+ 1 18904885 2318.81%
+ 2 11574997 1419.75%
+ 3 6762756 829.50%
+ 4 5075415 622.53%
+ 5 2394533 293.71%
+ 6 1208963 148.29%
+ 7 250769 30.76%
+ 8 50251 6.16%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate
+system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 426 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 50669408 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 19230073 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 19230003 # ITB hits
+system.cpu.itb.misses 70 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 60179000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34278.222222 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 115689000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 104895000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34390.243902 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.162602 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 4230000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3845000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs 1500 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 3000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 175868000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 159585500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 7186 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 5110 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 159585500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 2244.769579 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 81637318 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 40833183 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 115929564 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 28833296 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 8071146 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 2024389 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 47502203 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 5305 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 457 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 4572167 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 446 # count of temporary serializing insts renamed
+system.cpu.timesIdled 2428 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:29:52
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124
\ No newline at end of file
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 2797283 # Simulator instruction rate (inst/s)
-host_mem_usage 198592 # Number of bytes of host memory used
-host_seconds 32.85 # Real time elapsed on the host
-host_tick_rate 1398634763 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 91903056 # Number of instructions simulated
-sim_seconds 0.045952 # Number of seconds simulated
-sim_ticks 45951567500 # Number of ticks simulated
-system.cpu.dtb.accesses 26497334 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 26497301 # DTB hits
-system.cpu.dtb.misses 33 # DTB misses
-system.cpu.dtb.read_accesses 19996208 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 19996198 # DTB read hits
-system.cpu.dtb.read_misses 10 # DTB read misses
-system.cpu.dtb.write_accesses 6501126 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 6501103 # DTB write hits
-system.cpu.dtb.write_misses 23 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 91903136 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 91903089 # ITB hits
-system.cpu.itb.misses 47 # ITB misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 91903136 # number of cpu cycles simulated
-system.cpu.num_insts 91903056 # Number of instructions executed
-system.cpu.num_refs 26537141 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124
\ No newline at end of file
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2797283 # Simulator instruction rate (inst/s)
+host_mem_usage 198592 # Number of bytes of host memory used
+host_seconds 32.85 # Real time elapsed on the host
+host_tick_rate 1398634763 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 91903056 # Number of instructions simulated
+sim_seconds 0.045952 # Number of seconds simulated
+sim_ticks 45951567500 # Number of ticks simulated
+system.cpu.dtb.accesses 26497334 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 26497301 # DTB hits
+system.cpu.dtb.misses 33 # DTB misses
+system.cpu.dtb.read_accesses 19996208 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 19996198 # DTB read hits
+system.cpu.dtb.read_misses 10 # DTB read misses
+system.cpu.dtb.write_accesses 6501126 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 6501103 # DTB write hits
+system.cpu.dtb.write_misses 23 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 91903136 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 91903089 # ITB hits
+system.cpu.itb.misses 47 # ITB misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 91903136 # number of cpu cycles simulated
+system.cpu.num_insts 91903056 # Number of instructions executed
+system.cpu.num_refs 26537141 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:45
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124
\ No newline at end of file
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1637033 # Simulator instruction rate (inst/s)
-host_mem_usage 206044 # Number of bytes of host memory used
-host_seconds 56.14 # Real time elapsed on the host
-host_tick_rate 2115189911 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 91903056 # Number of instructions simulated
-sim_seconds 0.118747 # Number of seconds simulated
-sim_ticks 118747246000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 104104000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55046.272494 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 128478000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 121476000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 26494967 # number of overall hits
-system.cpu.dcache.overall_miss_latency 128478000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2334 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 121476000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 157 # number of replacements
-system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1442.022508 # Cycle average of tags in use
-system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 104 # number of writebacks
-system.cpu.dtb.accesses 26497334 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 26497301 # DTB hits
-system.cpu.dtb.misses 33 # DTB misses
-system.cpu.dtb.read_accesses 19996208 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 19996198 # DTB read hits
-system.cpu.dtb.read_misses 10 # DTB read misses
-system.cpu.dtb.write_accesses 6501126 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 6501103 # DTB write hits
-system.cpu.dtb.write_misses 23 # DTB write misses
-system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
-system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
-system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 91894580 # number of overall hits
-system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
-system.cpu.icache.overall_misses 8510 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 6681 # number of replacements
-system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1418.025998 # Cycle average of tags in use
-system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 91903137 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 91903090 # ITB hits
-system.cpu.itb.misses 47 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 5772000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.969435 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 249132000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.446380 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 4791 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 191640000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.446380 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 4791 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 5942 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 4791 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 191640000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 3010 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2022.059349 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 237494492 # number of cpu cycles simulated
-system.cpu.num_insts 91903056 # Number of instructions executed
-system.cpu.num_refs 26537141 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:28:54
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124
\ No newline at end of file
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1637033 # Simulator instruction rate (inst/s)
+host_mem_usage 206044 # Number of bytes of host memory used
+host_seconds 56.14 # Real time elapsed on the host
+host_tick_rate 2115189911 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 91903056 # Number of instructions simulated
+sim_seconds 0.118747 # Number of seconds simulated
+sim_ticks 118747246000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 104104000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 55046.272494 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 128478000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 121476000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 26494967 # number of overall hits
+system.cpu.dcache.overall_miss_latency 128478000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2334 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 121476000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 157 # number of replacements
+system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 1442.022508 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 104 # number of writebacks
+system.cpu.dtb.accesses 26497334 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 26497301 # DTB hits
+system.cpu.dtb.misses 33 # DTB misses
+system.cpu.dtb.read_accesses 19996208 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 19996198 # DTB read hits
+system.cpu.dtb.read_misses 10 # DTB read misses
+system.cpu.dtb.write_accesses 6501126 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 6501103 # DTB write hits
+system.cpu.dtb.write_misses 23 # DTB write misses
+system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
+system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
+system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 91894580 # number of overall hits
+system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
+system.cpu.icache.overall_misses 8510 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 6681 # number of replacements
+system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1418.025998 # Cycle average of tags in use
+system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 91903137 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 91903090 # ITB hits
+system.cpu.itb.misses 47 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 5772000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 1.969435 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 249132000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.446380 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 4791 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 191640000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.446380 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 4791 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 5942 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 4791 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 191640000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 3010 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 2022.059349 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 237494492 # number of cpu cycles simulated
+system.cpu.num_insts 91903056 # Number of instructions executed
+system.cpu.num_refs 26537141 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:28:54
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124
\ No newline at end of file
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 2346541 # Simulator instruction rate (inst/s)
-host_mem_usage 200408 # Number of bytes of host memory used
-host_seconds 82.44 # Real time elapsed on the host
-host_tick_rate 1173274177 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 193444769 # Number of instructions simulated
-sim_seconds 0.096723 # Number of seconds simulated
-sim_ticks 96722951500 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 193445904 # number of cpu cycles simulated
-system.cpu.num_insts 193444769 # Number of instructions executed
-system.cpu.num_refs 76733959 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 401 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:54:24
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 96722951500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2346541 # Simulator instruction rate (inst/s)
+host_mem_usage 200408 # Number of bytes of host memory used
+host_seconds 82.44 # Real time elapsed on the host
+host_tick_rate 1173274177 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 193444769 # Number of instructions simulated
+sim_seconds 0.096723 # Number of seconds simulated
+sim_ticks 96722951500 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 193445904 # number of cpu cycles simulated
+system.cpu.num_insts 193444769 # Number of instructions executed
+system.cpu.num_refs 76733959 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 401 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:54:24
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-atomic
-Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
-Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 96722951500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1229412 # Simulator instruction rate (inst/s)
-host_mem_usage 207888 # Number of bytes of host memory used
-host_seconds 157.35 # Real time elapsed on the host
-host_tick_rate 1719613407 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 193444769 # Number of instructions simulated
-sim_seconds 0.270579 # Number of seconds simulated
-sim_ticks 270578573000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
-system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 112000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 106000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 18975338 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 76709909 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 89544000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1599 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 84747000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1599 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 76709909 # number of overall hits
-system.cpu.dcache.overall_miss_latency 89544000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1599 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 84747000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1599 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 2 # number of replacements
-system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1237.193452 # Cycle average of tags in use
-system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2 # number of writebacks
-system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 193433499 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 15741.658447 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 193445787 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
-system.cpu.icache.demand_hits 193433499 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses
-system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 193445787 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 193433499 # number of overall hits
-system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses
-system.cpu.icache.overall_misses 12288 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 10362 # number of replacements
-system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1591.566927 # Cycle average of tags in use
-system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 1300000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.134332 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 8691 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 5173 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2657.329033 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 541157146 # number of cpu cycles simulated
-system.cpu.num_insts 193444769 # Number of instructions executed
-system.cpu.num_refs 76733959 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 401 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 17 2008 13:45:49
+M5 revision 5749:7015e400bd1deffa6e51e839baf2ed6d9bd3e31f
+M5 commit date Sat Nov 15 23:42:11 2008 -0500
+M5 started Nov 17 2008 13:46:11
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 270578573000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1229412 # Simulator instruction rate (inst/s)
+host_mem_usage 207888 # Number of bytes of host memory used
+host_seconds 157.35 # Real time elapsed on the host
+host_tick_rate 1719613407 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 193444769 # Number of instructions simulated
+sim_seconds 0.270579 # Number of seconds simulated
+sim_ticks 270578573000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 112000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 106000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 18975338 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 76709909 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 89544000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1599 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 84747000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1599 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 76709909 # number of overall hits
+system.cpu.dcache.overall_miss_latency 89544000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1599 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 84747000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1599 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 2 # number of replacements
+system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 1237.193452 # Cycle average of tags in use
+system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2 # number of writebacks
+system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 193433499 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 15741.658447 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 193445787 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
+system.cpu.icache.demand_hits 193433499 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses
+system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 193445787 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 193433499 # number of overall hits
+system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses
+system.cpu.icache.overall_misses 12288 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 10362 # number of replacements
+system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1591.566927 # Cycle average of tags in use
+system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses 1078 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 56056000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1078 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 1300000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 2.134332 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 268996000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.373125 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 5173 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 8691 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 5173 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 2657.329033 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 541157146 # number of cpu cycles simulated
+system.cpu.num_insts 193444769 # Number of instructions executed
+system.cpu.num_refs 76733959 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 401 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 17 2008 13:45:49
-M5 revision 5749:7015e400bd1deffa6e51e839baf2ed6d9bd3e31f
-M5 commit date Sat Nov 15 23:42:11 2008 -0500
-M5 started Nov 17 2008 13:46:11
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 270578573000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 2311586 # Simulator instruction rate (inst/s)
-host_mem_usage 202280 # Number of bytes of host memory used
-host_seconds 94.57 # Real time elapsed on the host
-host_tick_rate 1374811015 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 218595322 # Number of instructions simulated
-sim_seconds 0.130009 # Number of seconds simulated
-sim_ticks 130009373500 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 260018748 # number of cpu cycles simulated
-system.cpu.num_insts 218595322 # Number of instructions executed
-system.cpu.num_refs 77165364 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 23:03:02
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 6 2008 00:16:46
+M5 executing on zizzer
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-atomic
+Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 130009373500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2311586 # Simulator instruction rate (inst/s)
+host_mem_usage 202280 # Number of bytes of host memory used
+host_seconds 94.57 # Real time elapsed on the host
+host_tick_rate 1374811015 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 218595322 # Number of instructions simulated
+sim_seconds 0.130009 # Number of seconds simulated
+sim_ticks 130009373500 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 260018748 # number of cpu cycles simulated
+system.cpu.num_insts 218595322 # Number of instructions executed
+system.cpu.num_refs 77165364 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 23:03:02
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 6 2008 00:16:46
-M5 executing on zizzer
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-atomic
-Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
-Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 130009373500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 937563 # Simulator instruction rate (inst/s)
-host_mem_usage 210412 # Number of bytes of host memory used
-host_seconds 233.15 # Real time elapsed on the host
-host_tick_rate 1447418160 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 218595322 # Number of instructions simulated
-sim_seconds 0.337470 # Number of seconds simulated
-sim_ticks 337469714000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 56649281 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 17823500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 319 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 16866500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 20515729 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 20514128 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 89656000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1601 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 84853000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1601 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40740.989968 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 77165329 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55978.906250 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 77163409 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 107479500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1920 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 101719500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1920 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 77165329 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55978.906250 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 77163409 # number of overall hits
-system.cpu.dcache.overall_miss_latency 107479500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1920 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 101719500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1920 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 27 # number of replacements
-system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1362.540978 # Cycle average of tags in use
-system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2 # number of writebacks
-system.cpu.icache.ReadReq_accesses 260018596 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 260013903 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 170866000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 55404.624547 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 260018596 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency
-system.cpu.icache.demand_hits 260013903 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
-system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 170866000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000018 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 4693 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 260018596 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 260013903 # number of overall hits
-system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
-system.cpu.icache.overall_misses 4693 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 170866000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000018 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 2835 # number of replacements
-system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1453.991072 # Cycle average of tags in use
-system.cpu.icache.total_refs 260013903 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 5012 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52002.058917 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 1855 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 164170500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.629888 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 3157 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 126280000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629888 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 3157 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 1352000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 26 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1040000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 26 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.592084 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 6587 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52001.373626 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1855 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 246070500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.718385 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 4732 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 189280000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.718385 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 4732 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 6587 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52001.373626 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1855 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 246070500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.718385 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 4732 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 189280000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.718385 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 4732 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2031.720395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 674939428 # number of cpu cycles simulated
-system.cpu.num_insts 218595322 # Number of instructions executed
-system.cpu.num_refs 77165364 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 9 2008 18:23:31
+M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e
+M5 commit date Sat Nov 08 21:06:07 2008 -0800
+M5 started Nov 9 2008 18:29:22
+M5 executing on tater
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-timing
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 337469714000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 937563 # Simulator instruction rate (inst/s)
+host_mem_usage 210412 # Number of bytes of host memory used
+host_seconds 233.15 # Real time elapsed on the host
+host_tick_rate 1447418160 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 218595322 # Number of instructions simulated
+sim_seconds 0.337470 # Number of seconds simulated
+sim_ticks 337469714000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 56649281 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 17823500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 319 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 16866500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 20515729 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 20514128 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 89656000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1601 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 84853000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1601 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 40740.989968 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 77165329 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 55978.906250 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 77163409 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 107479500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1920 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 101719500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1920 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 77165329 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 55978.906250 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 77163409 # number of overall hits
+system.cpu.dcache.overall_miss_latency 107479500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1920 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 101719500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1920 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 27 # number of replacements
+system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 1362.540978 # Cycle average of tags in use
+system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2 # number of writebacks
+system.cpu.icache.ReadReq_accesses 260018596 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 260013903 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 170866000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 55404.624547 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 260018596 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency
+system.cpu.icache.demand_hits 260013903 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
+system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 170866000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000018 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 4693 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 260018596 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 260013903 # number of overall hits
+system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
+system.cpu.icache.overall_misses 4693 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 170866000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000018 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 2835 # number of replacements
+system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1453.991072 # Cycle average of tags in use
+system.cpu.icache.total_refs 260013903 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 5012 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52002.058917 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 1855 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 164170500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.629888 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 3157 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 126280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629888 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 3157 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 1352000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 26 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1040000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 26 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.592084 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 6587 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52001.373626 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 1855 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 246070500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.718385 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 4732 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 189280000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.718385 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 4732 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 6587 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52001.373626 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 1855 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 246070500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.718385 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 4732 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 189280000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.718385 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 4732 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 2031.720395 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 674939428 # number of cpu cycles simulated
+system.cpu.num_insts 218595322 # Number of instructions executed
+system.cpu.num_refs 77165364 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 9 2008 18:23:31
-M5 revision 5729:dc856beee70a0af5562dc3d83a94fb177bcd292e
-M5 commit date Sat Nov 08 21:06:07 2008 -0800
-M5 started Nov 9 2008 18:29:22
-M5 executing on tater
-command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/x86/linux/simple-timing
-Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
-Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 337469714000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 2656730 # Simulator instruction rate (inst/s)
-host_mem_usage 499828 # Number of bytes of host memory used
-host_seconds 839.06 # Real time elapsed on the host
-host_tick_rate 2662232 # Simulator tick rate (ticks/s)
-sim_freq 2000000000 # Frequency of simulated ticks
-sim_insts 2229160714 # Number of instructions simulated
-sim_seconds 1.116889 # Number of seconds simulated
-sim_ticks 2233777512 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 2233777513 # number of cpu cycles simulated
-system.cpu.num_insts 2229160714 # Number of instructions executed
-system.cpu.num_refs 547951940 # Number of memory references
-
----------- End Simulation Statistics ----------
--- /dev/null
+Warning: rounding error > tolerance
+ 0.002000 rounded to 0
+Warning: rounding error > tolerance
+ 0.002000 rounded to 0
+warn: No kernel set for full system simulation. Assuming you know what you're doing...
+Warning: rounding error > tolerance
+ 0.002000 rounded to 0
+warn: Sockets disabled, not accepting terminal connections
+Warning: rounding error > tolerance
+ 0.002000 rounded to 0
+warn: Sockets disabled, not accepting gdb connections
+warn: Ignoring write to SPARC ERROR regsiter
+warn: Ignoring write to SPARC ERROR regsiter
+warn: Don't know what interrupt to clear for console.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 15:59:58
+M5 revision 5718:323cfbfec1a4ee56f71bd7e4cfad02af7e11c17e
+M5 commit date Wed Nov 05 15:30:49 2008 -0500
+M5 started Nov 5 2008 16:00:22
+M5 executing on zizzer
+command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
+Global frequency set at 2000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 2233777512 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2656730 # Simulator instruction rate (inst/s)
+host_mem_usage 499828 # Number of bytes of host memory used
+host_seconds 839.06 # Real time elapsed on the host
+host_tick_rate 2662232 # Simulator tick rate (ticks/s)
+sim_freq 2000000000 # Frequency of simulated ticks
+sim_insts 2229160714 # Number of instructions simulated
+sim_seconds 1.116889 # Number of seconds simulated
+sim_ticks 2233777512 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 2233777513 # number of cpu cycles simulated
+system.cpu.num_insts 2229160714 # Number of instructions executed
+system.cpu.num_refs 547951940 # Number of memory references
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-Warning: rounding error > tolerance
- 0.002000 rounded to 0
-Warning: rounding error > tolerance
- 0.002000 rounded to 0
-warn: No kernel set for full system simulation. Assuming you know what you're doing...
-Warning: rounding error > tolerance
- 0.002000 rounded to 0
-warn: Sockets disabled, not accepting terminal connections
-Warning: rounding error > tolerance
- 0.002000 rounded to 0
-warn: Sockets disabled, not accepting gdb connections
-warn: Ignoring write to SPARC ERROR regsiter
-warn: Ignoring write to SPARC ERROR regsiter
-warn: Don't know what interrupt to clear for console.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 15:59:58
-M5 revision 5718:323cfbfec1a4ee56f71bd7e4cfad02af7e11c17e
-M5 commit date Wed Nov 05 15:30:49 2008 -0500
-M5 started Nov 5 2008 16:00:22
-M5 executing on zizzer
-command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
-Global frequency set at 2000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2233777512 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 806 # Number of BTB hits
-global.BPredUnit.BTBLookups 1937 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1370 # Number of conditional branches predicted
-global.BPredUnit.lookups 2263 # Number of BP lookups
-global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target.
-host_inst_rate 7058 # Simulator instruction rate (inst/s)
-host_mem_usage 199016 # Number of bytes of host memory used
-host_seconds 0.90 # Real time elapsed on the host
-host_tick_rate 13784618 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 29 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2287 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1266 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 6386 # Number of instructions simulated
-sim_seconds 0.000012 # Number of seconds simulated
-sim_ticks 12474500 # Number of ticks simulated
-system.cpu.commit.COM:branches 1051 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 12416
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 9513 7661.89%
- 1 1627 1310.41%
- 2 488 393.04%
- 3 267 215.05%
- 4 153 123.23%
- 5 104 83.76%
- 6 96 77.32%
- 7 53 42.69%
- 8 115 92.62%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 6403 # Number of instructions committed
-system.cpu.commit.COM:loads 1185 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 2050 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 6386 # Number of Instructions Simulated
-system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
-system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2104 # number of overall hits
-system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 554 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 2951 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 2890 # DTB hits
-system.cpu.dtb.misses 61 # DTB misses
-system.cpu.dtb.read_accesses 1876 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 1840 # DTB read hits
-system.cpu.dtb.read_misses 36 # DTB read misses
-system.cpu.dtb.write_accesses 1075 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 1050 # DTB write hits
-system.cpu.dtb.write_misses 25 # DTB write misses
-system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched
-system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 13314
-system.cpu.fetch.rateDist.min_value 0
- 0 10844 8144.81%
- 1 252 189.27%
- 2 238 178.76%
- 3 230 172.75%
- 4 272 204.30%
- 5 162 121.68%
- 6 232 174.25%
- 7 129 96.89%
- 8 955 717.29%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses
-system.cpu.icache.demand_misses 424 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1378 # number of overall hits
-system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses
-system.cpu.icache.overall_misses 424 # number of overall misses
-system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use
-system.cpu.icache.total_refs 1378 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 1450 # Number of branches executed
-system.cpu.iew.EXEC:nop 82 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate
-system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 1077 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 6020 # num instructions consuming a value
-system.cpu.iew.WB:count 8734 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4491 # num instructions producing a value
-system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle
-system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 9345 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 2 0.02% # Type of FU issued
- IntAlu 6254 66.92% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1986 21.25% # Type of FU issued
- MemWrite 1100 11.77% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 14 13.33% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 56 53.33% # attempts to use FU when none available
- MemWrite 35 33.33% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 13314
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 9113 6844.67%
- 1 1716 1288.87%
- 2 1071 804.42%
- 3 725 544.54%
- 4 355 266.64%
- 5 172 129.19%
- 6 115 86.38%
- 7 34 25.54%
- 8 13 9.76%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate
-system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 1838 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 1802 # ITB hits
-system.cpu.itb.misses 36 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 480 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 24950 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
-system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:44
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 12474500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 806 # Number of BTB hits
+global.BPredUnit.BTBLookups 1937 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 1370 # Number of conditional branches predicted
+global.BPredUnit.lookups 2263 # Number of BP lookups
+global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target.
+host_inst_rate 7058 # Simulator instruction rate (inst/s)
+host_mem_usage 199016 # Number of bytes of host memory used
+host_seconds 0.90 # Real time elapsed on the host
+host_tick_rate 13784618 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 29 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 2287 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1266 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 6386 # Number of instructions simulated
+sim_seconds 0.000012 # Number of seconds simulated
+sim_ticks 12474500 # Number of ticks simulated
+system.cpu.commit.COM:branches 1051 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 12416
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 9513 7661.89%
+ 1 1627 1310.41%
+ 2 488 393.04%
+ 3 267 215.05%
+ 4 153 123.23%
+ 5 104 83.76%
+ 6 96 77.32%
+ 7 53 42.69%
+ 8 115 92.62%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 6403 # Number of instructions committed
+system.cpu.commit.COM:loads 1185 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 2050 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 6386 # Number of Instructions Simulated
+system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
+system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 2104 # number of overall hits
+system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 554 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 2951 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 2890 # DTB hits
+system.cpu.dtb.misses 61 # DTB misses
+system.cpu.dtb.read_accesses 1876 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 1840 # DTB read hits
+system.cpu.dtb.read_misses 36 # DTB read misses
+system.cpu.dtb.write_accesses 1075 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 1050 # DTB write hits
+system.cpu.dtb.write_misses 25 # DTB write misses
+system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched
+system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 13314
+system.cpu.fetch.rateDist.min_value 0
+ 0 10844 8144.81%
+ 1 252 189.27%
+ 2 238 178.76%
+ 3 230 172.75%
+ 4 272 204.30%
+ 5 162 121.68%
+ 6 232 174.25%
+ 7 129 96.89%
+ 8 955 717.29%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses
+system.cpu.icache.demand_misses 424 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1378 # number of overall hits
+system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses
+system.cpu.icache.overall_misses 424 # number of overall misses
+system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use
+system.cpu.icache.total_refs 1378 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 1450 # Number of branches executed
+system.cpu.iew.EXEC:nop 82 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate
+system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 1077 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 6020 # num instructions consuming a value
+system.cpu.iew.WB:count 8734 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 4491 # num instructions producing a value
+system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle
+system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 9345 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 2 0.02% # Type of FU issued
+ IntAlu 6254 66.92% # Type of FU issued
+ IntMult 1 0.01% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2 0.02% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 1986 21.25% # Type of FU issued
+ MemWrite 1100 11.77% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 14 13.33% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 56 53.33% # attempts to use FU when none available
+ MemWrite 35 33.33% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 13314
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 9113 6844.67%
+ 1 1716 1288.87%
+ 2 1071 804.42%
+ 3 725 544.54%
+ 4 355 266.64%
+ 5 172 129.19%
+ 6 115 86.38%
+ 7 34 25.54%
+ 8 13 9.76%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate
+system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 1838 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 1802 # ITB hits
+system.cpu.itb.misses 36 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 1 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 480 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 24950 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
+system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:44
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Exiting @ tick 12474500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 6758 # Simulator instruction rate (inst/s)
-host_mem_usage 190848 # Number of bytes of host memory used
-host_seconds 0.95 # Real time elapsed on the host
-host_tick_rate 3391912 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 6404 # Number of instructions simulated
-sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 3215000 # Number of ticks simulated
-system.cpu.dtb.accesses 2060 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 2050 # DTB hits
-system.cpu.dtb.misses 10 # DTB misses
-system.cpu.dtb.read_accesses 1192 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 1185 # DTB read hits
-system.cpu.dtb.read_misses 7 # DTB read misses
-system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 865 # DTB write hits
-system.cpu.dtb.write_misses 3 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 6431 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 6414 # ITB hits
-system.cpu.itb.misses 17 # ITB misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 6431 # number of cpu cycles simulated
-system.cpu.num_insts 6404 # Number of instructions executed
-system.cpu.num_refs 2060 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:44
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 3215000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 6758 # Simulator instruction rate (inst/s)
+host_mem_usage 190848 # Number of bytes of host memory used
+host_seconds 0.95 # Real time elapsed on the host
+host_tick_rate 3391912 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 6404 # Number of instructions simulated
+sim_seconds 0.000003 # Number of seconds simulated
+sim_ticks 3215000 # Number of ticks simulated
+system.cpu.dtb.accesses 2060 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 2050 # DTB hits
+system.cpu.dtb.misses 10 # DTB misses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 1185 # DTB read hits
+system.cpu.dtb.read_misses 7 # DTB read misses
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 865 # DTB write hits
+system.cpu.dtb.write_misses 3 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 6431 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 6414 # ITB hits
+system.cpu.itb.misses 17 # ITB misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 6431 # number of cpu cycles simulated
+system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.num_refs 2060 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:44
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Exiting @ tick 3215000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 68165 # Simulator instruction rate (inst/s)
-host_mem_usage 198212 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
-host_tick_rate 358563073 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 6404 # Number of instructions simulated
-sim_seconds 0.000034 # Number of seconds simulated
-sim_ticks 33777000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10192000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 9646000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1868 # number of overall hits
-system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 182 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 9646000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 104.111261 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dtb.accesses 2060 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 2050 # DTB hits
-system.cpu.dtb.misses 10 # DTB misses
-system.cpu.dtb.read_accesses 1192 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 1185 # DTB read hits
-system.cpu.dtb.read_misses 7 # DTB read misses
-system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 865 # DTB write hits
-system.cpu.dtb.write_misses 3 # DTB write misses
-system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
-system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses
-system.cpu.icache.demand_misses 279 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 6136 # number of overall hits
-system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses
-system.cpu.icache.overall_misses 279 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 128.649737 # Cycle average of tags in use
-system.cpu.icache.total_refs 6136 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 6432 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 6415 # ITB hits
-system.cpu.itb.misses 17 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 446 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 179.928092 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 67554 # number of cpu cycles simulated
-system.cpu.num_insts 6404 # Number of instructions executed
-system.cpu.num_refs 2060 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:46
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 33777000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 68165 # Simulator instruction rate (inst/s)
+host_mem_usage 198212 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 358563073 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 6404 # Number of instructions simulated
+sim_seconds 0.000034 # Number of seconds simulated
+sim_ticks 33777000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 10192000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 9646000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 1868 # number of overall hits
+system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 182 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 9646000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 104.111261 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.dtb.accesses 2060 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 2050 # DTB hits
+system.cpu.dtb.misses 10 # DTB misses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 1185 # DTB read hits
+system.cpu.dtb.read_misses 7 # DTB read misses
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 865 # DTB write hits
+system.cpu.dtb.write_misses 3 # DTB write misses
+system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
+system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses
+system.cpu.icache.demand_misses 279 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 6136 # number of overall hits
+system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses
+system.cpu.icache.overall_misses 279 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 128.649737 # Cycle average of tags in use
+system.cpu.icache.total_refs 6136 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 6432 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 6415 # ITB hits
+system.cpu.itb.misses 17 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 1 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 446 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 179.928092 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 67554 # number of cpu cycles simulated
+system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.num_refs 2060 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:46
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Exiting @ tick 33777000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 198 # Number of BTB hits
-global.BPredUnit.BTBLookups 684 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 447 # Number of conditional branches predicted
-global.BPredUnit.lookups 859 # Number of BP lookups
-global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target.
-host_inst_rate 31288 # Simulator instruction rate (inst/s)
-host_mem_usage 198012 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-host_tick_rate 93885607 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 411 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2387 # Number of instructions simulated
-sim_seconds 0.000007 # Number of seconds simulated
-sim_ticks 7183000 # Number of ticks simulated
-system.cpu.commit.COM:branches 396 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6196
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 5239 8455.46%
- 1 263 424.47%
- 2 334 539.06%
- 3 134 216.27%
- 4 73 117.82%
- 5 63 101.68%
- 6 32 51.65%
- 7 20 32.28%
- 8 38 61.33%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 2576 # Number of instructions committed
-system.cpu.commit.COM:loads 415 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 709 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 2387 # Number of Instructions Simulated
-system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
-system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 674 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 193 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use
-system.cpu.dcache.total_refs 715 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 971 # DTB accesses
-system.cpu.dtb.acv 1 # DTB access violations
-system.cpu.dtb.hits 946 # DTB hits
-system.cpu.dtb.misses 25 # DTB misses
-system.cpu.dtb.read_accesses 611 # DTB read accesses
-system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_hits 600 # DTB read hits
-system.cpu.dtb.read_misses 11 # DTB read misses
-system.cpu.dtb.write_accesses 360 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 346 # DTB write hits
-system.cpu.dtb.write_misses 14 # DTB write misses
-system.cpu.fetch.Branches 859 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 747 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 240 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6528
-system.cpu.fetch.rateDist.min_value 0
- 0 5595 8570.77%
- 1 36 55.15%
- 2 100 153.19%
- 3 69 105.70%
- 4 130 199.14%
- 5 72 110.29%
- 6 45 68.93%
- 7 48 73.53%
- 8 433 663.30%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency
-system.cpu.icache.demand_hits 512 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses
-system.cpu.icache.demand_misses 235 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 512 # number of overall hits
-system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses
-system.cpu.icache.overall_misses 235 # number of overall misses
-system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use
-system.cpu.icache.total_refs 512 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 584 # Number of branches executed
-system.cpu.iew.EXEC:nop 286 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate
-system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 360 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1896 # num instructions consuming a value
-system.cpu.iew.WB:count 3311 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1509 # num instructions producing a value
-system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle
-system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 3514 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 0 0.00% # Type of FU issued
- IntAlu 2506 71.31% # Type of FU issued
- IntMult 1 0.03% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 0 0.00% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 639 18.18% # Type of FU issued
- MemWrite 368 10.47% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 1 2.94% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 11 32.35% # attempts to use FU when none available
- MemWrite 22 64.71% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6528
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 5051 7737.44%
- 1 569 871.63%
- 2 331 507.05%
- 3 253 387.56%
- 4 172 263.48%
- 5 97 148.59%
- 6 39 59.74%
- 7 11 16.85%
- 8 5 7.66%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate
-system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 776 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 747 # ITB hits
-system.cpu.itb.misses 29 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 266 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 14367 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
-system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:29:52
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 7183000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 198 # Number of BTB hits
+global.BPredUnit.BTBLookups 684 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 447 # Number of conditional branches predicted
+global.BPredUnit.lookups 859 # Number of BP lookups
+global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target.
+host_inst_rate 31288 # Simulator instruction rate (inst/s)
+host_mem_usage 198012 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
+host_tick_rate 93885607 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 411 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 2387 # Number of instructions simulated
+sim_seconds 0.000007 # Number of seconds simulated
+sim_ticks 7183000 # Number of ticks simulated
+system.cpu.commit.COM:branches 396 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 6196
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 5239 8455.46%
+ 1 263 424.47%
+ 2 334 539.06%
+ 3 134 216.27%
+ 4 73 117.82%
+ 5 63 101.68%
+ 6 32 51.65%
+ 7 20 32.28%
+ 8 38 61.33%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 2576 # Number of instructions committed
+system.cpu.commit.COM:loads 415 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 709 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 2387 # Number of Instructions Simulated
+system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
+system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 674 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 193 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use
+system.cpu.dcache.total_refs 715 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 971 # DTB accesses
+system.cpu.dtb.acv 1 # DTB access violations
+system.cpu.dtb.hits 946 # DTB hits
+system.cpu.dtb.misses 25 # DTB misses
+system.cpu.dtb.read_accesses 611 # DTB read accesses
+system.cpu.dtb.read_acv 1 # DTB read access violations
+system.cpu.dtb.read_hits 600 # DTB read hits
+system.cpu.dtb.read_misses 11 # DTB read misses
+system.cpu.dtb.write_accesses 360 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 346 # DTB write hits
+system.cpu.dtb.write_misses 14 # DTB write misses
+system.cpu.fetch.Branches 859 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 747 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 240 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 6528
+system.cpu.fetch.rateDist.min_value 0
+ 0 5595 8570.77%
+ 1 36 55.15%
+ 2 100 153.19%
+ 3 69 105.70%
+ 4 130 199.14%
+ 5 72 110.29%
+ 6 45 68.93%
+ 7 48 73.53%
+ 8 433 663.30%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency
+system.cpu.icache.demand_hits 512 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses
+system.cpu.icache.demand_misses 235 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 512 # number of overall hits
+system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses
+system.cpu.icache.overall_misses 235 # number of overall misses
+system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use
+system.cpu.icache.total_refs 512 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 584 # Number of branches executed
+system.cpu.iew.EXEC:nop 286 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate
+system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 360 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 1896 # num instructions consuming a value
+system.cpu.iew.WB:count 3311 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 1509 # num instructions producing a value
+system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle
+system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 3514 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 0 0.00% # Type of FU issued
+ IntAlu 2506 71.31% # Type of FU issued
+ IntMult 1 0.03% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 0 0.00% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 639 18.18% # Type of FU issued
+ MemWrite 368 10.47% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 1 2.94% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 11 32.35% # attempts to use FU when none available
+ MemWrite 22 64.71% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 6528
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 5051 7737.44%
+ 1 569 871.63%
+ 2 331 507.05%
+ 3 253 387.56%
+ 4 172 263.48%
+ 5 97 148.59%
+ 6 39 59.74%
+ 7 11 16.85%
+ 8 5 7.66%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate
+system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 776 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 747 # ITB hits
+system.cpu.itb.misses 29 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 0 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 266 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 14367 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
+system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:29:52
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Exiting @ tick 7183000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 334328 # Simulator instruction rate (inst/s)
-host_mem_usage 189900 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 162370166 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2577 # Number of instructions simulated
-sim_seconds 0.000001 # Number of seconds simulated
-sim_ticks 1297500 # Number of ticks simulated
-system.cpu.dtb.accesses 717 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 709 # DTB hits
-system.cpu.dtb.misses 8 # DTB misses
-system.cpu.dtb.read_accesses 419 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 415 # DTB read hits
-system.cpu.dtb.read_misses 4 # DTB read misses
-system.cpu.dtb.write_accesses 298 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 294 # DTB write hits
-system.cpu.dtb.write_misses 4 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 2596 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 2585 # ITB hits
-system.cpu.itb.misses 11 # ITB misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 2596 # number of cpu cycles simulated
-system.cpu.num_insts 2577 # Number of instructions executed
-system.cpu.num_refs 717 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:24:43
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 1297500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 334328 # Simulator instruction rate (inst/s)
+host_mem_usage 189900 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 162370166 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 2577 # Number of instructions simulated
+sim_seconds 0.000001 # Number of seconds simulated
+sim_ticks 1297500 # Number of ticks simulated
+system.cpu.dtb.accesses 717 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 709 # DTB hits
+system.cpu.dtb.misses 8 # DTB misses
+system.cpu.dtb.read_accesses 419 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 415 # DTB read hits
+system.cpu.dtb.read_misses 4 # DTB read misses
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 294 # DTB write hits
+system.cpu.dtb.write_misses 4 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 2596 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 2585 # ITB hits
+system.cpu.itb.misses 11 # ITB misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 2596 # number of cpu cycles simulated
+system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.num_refs 717 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:24:43
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Exiting @ tick 1297500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 59950 # Simulator instruction rate (inst/s)
-host_mem_usage 197352 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-host_tick_rate 402241104 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2577 # Number of instructions simulated
-sim_seconds 0.000017 # Number of seconds simulated
-sim_ticks 17374000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 616 # number of overall hits
-system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 93 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use
-system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dtb.accesses 717 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 709 # DTB hits
-system.cpu.dtb.misses 8 # DTB misses
-system.cpu.dtb.read_accesses 419 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 415 # DTB read hits
-system.cpu.dtb.read_misses 4 # DTB read misses
-system.cpu.dtb.write_accesses 298 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 294 # DTB write hits
-system.cpu.dtb.write_misses 4 # DTB write misses
-system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses
-system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 2423 # number of overall hits
-system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses
-system.cpu.icache.overall_misses 163 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use
-system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 2597 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 2586 # ITB hits
-system.cpu.itb.misses 11 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 245 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 34748 # number of cpu cycles simulated
-system.cpu.num_insts 2577 # Number of instructions executed
-system.cpu.num_refs 717 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:46
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 17374000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 59950 # Simulator instruction rate (inst/s)
+host_mem_usage 197352 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 402241104 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 2577 # Number of instructions simulated
+sim_seconds 0.000017 # Number of seconds simulated
+sim_ticks 17374000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 616 # number of overall hits
+system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 93 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use
+system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.dtb.accesses 717 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 709 # DTB hits
+system.cpu.dtb.misses 8 # DTB misses
+system.cpu.dtb.read_accesses 419 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 415 # DTB read hits
+system.cpu.dtb.read_misses 4 # DTB read misses
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 294 # DTB write hits
+system.cpu.dtb.write_misses 4 # DTB write misses
+system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses
+system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 2423 # number of overall hits
+system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses
+system.cpu.icache.overall_misses 163 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use
+system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 2597 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 2586 # ITB hits
+system.cpu.itb.misses 11 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 0 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 245 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 34748 # number of cpu cycles simulated
+system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.num_refs 717 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:46
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Exiting @ tick 17374000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 10079 # Simulator instruction rate (inst/s)
-host_mem_usage 192068 # Number of bytes of host memory used
-host_seconds 0.56 # Real time elapsed on the host
-host_tick_rate 5037819 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5656 # Number of instructions simulated
-sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 2828000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 5657 # number of cpu cycles simulated
-system.cpu.num_insts 5656 # Number of instructions executed
-system.cpu.num_refs 2055 # Number of memory references
-system.cpu.tlb.accesses 0 # DTB accesses
-system.cpu.tlb.accesses 0 # DTB accesses
-system.cpu.tlb.hits 0 # DTB hits
-system.cpu.tlb.hits 0 # DTB hits
-system.cpu.tlb.misses 0 # DTB misses
-system.cpu.tlb.misses 0 # DTB misses
-system.cpu.tlb.read_accesses 0 # DTB read accesses
-system.cpu.tlb.read_accesses 0 # DTB read accesses
-system.cpu.tlb.read_hits 0 # DTB read hits
-system.cpu.tlb.read_hits 0 # DTB read hits
-system.cpu.tlb.read_misses 0 # DTB read misses
-system.cpu.tlb.read_misses 0 # DTB read misses
-system.cpu.tlb.write_accesses 0 # DTB write accesses
-system.cpu.tlb.write_accesses 0 # DTB write accesses
-system.cpu.tlb.write_hits 0 # DTB write hits
-system.cpu.tlb.write_hits 0 # DTB write hits
-system.cpu.tlb.write_misses 0 # DTB write misses
-system.cpu.tlb.write_misses 0 # DTB write misses
-system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:37:22
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:37:50
+M5 executing on zizzer
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello World!
+Exiting @ tick 2828000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 10079 # Simulator instruction rate (inst/s)
+host_mem_usage 192068 # Number of bytes of host memory used
+host_seconds 0.56 # Real time elapsed on the host
+host_tick_rate 5037819 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5656 # Number of instructions simulated
+sim_seconds 0.000003 # Number of seconds simulated
+sim_ticks 2828000 # Number of ticks simulated
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 5657 # number of cpu cycles simulated
+system.cpu.num_insts 5656 # Number of instructions executed
+system.cpu.num_refs 2055 # Number of memory references
+system.cpu.tlb.accesses 0 # DTB accesses
+system.cpu.tlb.accesses 0 # DTB accesses
+system.cpu.tlb.hits 0 # DTB hits
+system.cpu.tlb.hits 0 # DTB hits
+system.cpu.tlb.misses 0 # DTB misses
+system.cpu.tlb.misses 0 # DTB misses
+system.cpu.tlb.read_accesses 0 # DTB read accesses
+system.cpu.tlb.read_accesses 0 # DTB read accesses
+system.cpu.tlb.read_hits 0 # DTB read hits
+system.cpu.tlb.read_hits 0 # DTB read hits
+system.cpu.tlb.read_misses 0 # DTB read misses
+system.cpu.tlb.read_misses 0 # DTB read misses
+system.cpu.tlb.write_accesses 0 # DTB write accesses
+system.cpu.tlb.write_accesses 0 # DTB write accesses
+system.cpu.tlb.write_hits 0 # DTB write hits
+system.cpu.tlb.write_hits 0 # DTB write hits
+system.cpu.tlb.write_misses 0 # DTB write misses
+system.cpu.tlb.write_misses 0 # DTB write misses
+system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:37:22
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:37:50
-M5 executing on zizzer
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello World!
-Exiting @ tick 2828000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 334992 # Simulator instruction rate (inst/s)
-host_mem_usage 199532 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 1887416058 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5656 # Number of instructions simulated
-sim_seconds 0.000032 # Number of seconds simulated
-sim_ticks 32322000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1908 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 146 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 83.826869 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
-system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses
-system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 5355 # number of overall hits
-system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses
-system.cpu.icache.overall_misses 303 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 13 # number of replacements
-system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 134.976151 # Cycle average of tags in use
-system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2600000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 19916000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 15320000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 22516000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 17320000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 22516000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 433 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 17320000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 181.998644 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 64644 # number of cpu cycles simulated
-system.cpu.num_insts 5656 # Number of instructions executed
-system.cpu.num_refs 2055 # Number of memory references
-system.cpu.tlb.accesses 0 # DTB accesses
-system.cpu.tlb.accesses 0 # DTB accesses
-system.cpu.tlb.hits 0 # DTB hits
-system.cpu.tlb.hits 0 # DTB hits
-system.cpu.tlb.misses 0 # DTB misses
-system.cpu.tlb.misses 0 # DTB misses
-system.cpu.tlb.read_accesses 0 # DTB read accesses
-system.cpu.tlb.read_accesses 0 # DTB read accesses
-system.cpu.tlb.read_hits 0 # DTB read hits
-system.cpu.tlb.read_hits 0 # DTB read hits
-system.cpu.tlb.read_misses 0 # DTB read misses
-system.cpu.tlb.read_misses 0 # DTB read misses
-system.cpu.tlb.write_accesses 0 # DTB write accesses
-system.cpu.tlb.write_accesses 0 # DTB write accesses
-system.cpu.tlb.write_hits 0 # DTB write hits
-system.cpu.tlb.write_hits 0 # DTB write hits
-system.cpu.tlb.write_misses 0 # DTB write misses
-system.cpu.tlb.write_misses 0 # DTB write misses
-system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:37:22
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:37:51
+M5 executing on zizzer
+command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello World!
+Exiting @ tick 32322000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 334992 # Simulator instruction rate (inst/s)
+host_mem_usage 199532 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 1887416058 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5656 # Number of instructions simulated
+sim_seconds 0.000032 # Number of seconds simulated
+sim_ticks 32322000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 1908 # number of overall hits
+system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 146 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 83.826869 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
+system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses
+system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 5355 # number of overall hits
+system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses
+system.cpu.icache.overall_misses 303 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 13 # number of replacements
+system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 134.976151 # Cycle average of tags in use
+system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2600000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 19916000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 15320000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 22516000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 17320000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 22516000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 433 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 17320000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 181.998644 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 64644 # number of cpu cycles simulated
+system.cpu.num_insts 5656 # Number of instructions executed
+system.cpu.num_refs 2055 # Number of memory references
+system.cpu.tlb.accesses 0 # DTB accesses
+system.cpu.tlb.accesses 0 # DTB accesses
+system.cpu.tlb.hits 0 # DTB hits
+system.cpu.tlb.hits 0 # DTB hits
+system.cpu.tlb.misses 0 # DTB misses
+system.cpu.tlb.misses 0 # DTB misses
+system.cpu.tlb.read_accesses 0 # DTB read accesses
+system.cpu.tlb.read_accesses 0 # DTB read accesses
+system.cpu.tlb.read_hits 0 # DTB read hits
+system.cpu.tlb.read_hits 0 # DTB read hits
+system.cpu.tlb.read_misses 0 # DTB read misses
+system.cpu.tlb.read_misses 0 # DTB read misses
+system.cpu.tlb.write_accesses 0 # DTB write accesses
+system.cpu.tlb.write_accesses 0 # DTB write accesses
+system.cpu.tlb.write_hits 0 # DTB write hits
+system.cpu.tlb.write_hits 0 # DTB write hits
+system.cpu.tlb.write_misses 0 # DTB write misses
+system.cpu.tlb.write_misses 0 # DTB write misses
+system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:37:22
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:37:51
-M5 executing on zizzer
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/mips/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello World!
-Exiting @ tick 32322000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 371297 # Simulator instruction rate (inst/s)
-host_mem_usage 191740 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 185101425 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5340 # Number of instructions simulated
-sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 2701000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 5403 # number of cpu cycles simulated
-system.cpu.num_insts 5340 # Number of instructions executed
-system.cpu.num_refs 1402 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:55:47
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello World!Exiting @ tick 2701000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 371297 # Simulator instruction rate (inst/s)
+host_mem_usage 191740 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 185101425 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5340 # Number of instructions simulated
+sim_seconds 0.000003 # Number of seconds simulated
+sim_ticks 2701000 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 5403 # number of cpu cycles simulated
+system.cpu.num_insts 5340 # Number of instructions executed
+system.cpu.num_refs 1402 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:55:47
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 2701000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 419811 # Simulator instruction rate (inst/s)
-host_mem_usage 199192 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2213741040 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5340 # Number of instructions simulated
-sim_seconds 0.000029 # Number of seconds simulated
-sim_ticks 29031000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1239 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 150 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency
-system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses
-system.cpu.icache.demand_misses 257 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 5127 # number of overall hits
-system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses
-system.cpu.icache.overall_misses 257 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use
-system.cpu.icache.total_refs 5127 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 3 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 389 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 58062 # number of cpu cycles simulated
-system.cpu.num_insts 5340 # Number of instructions executed
-system.cpu.num_refs 1402 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:41:19
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello World!Exiting @ tick 29031000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 419811 # Simulator instruction rate (inst/s)
+host_mem_usage 199192 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+host_tick_rate 2213741040 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5340 # Number of instructions simulated
+sim_seconds 0.000029 # Number of seconds simulated
+sim_ticks 29031000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 1239 # number of overall hits
+system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 150 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency
+system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses
+system.cpu.icache.demand_misses 257 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 5127 # number of overall hits
+system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses
+system.cpu.icache.overall_misses 257 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use
+system.cpu.icache.total_refs 5127 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 3 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 389 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 58062 # number of cpu cycles simulated
+system.cpu.num_insts 5340 # Number of instructions executed
+system.cpu.num_refs 1402 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:41:19
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 29031000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 557395 # Simulator instruction rate (inst/s)
-host_mem_usage 190704 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 320851262 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 9493 # Number of instructions simulated
-sim_seconds 0.000006 # Number of seconds simulated
-sim_ticks 5518000 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 11037 # number of cpu cycles simulated
-system.cpu.num_insts 9493 # Number of instructions executed
-system.cpu.num_refs 2003 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 23:03:02
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 6 2008 00:18:22
+M5 executing on zizzer
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 5518000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 557395 # Simulator instruction rate (inst/s)
+host_mem_usage 190704 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 320851262 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 9493 # Number of instructions simulated
+sim_seconds 0.000006 # Number of seconds simulated
+sim_ticks 5518000 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 11037 # number of cpu cycles simulated
+system.cpu.num_insts 9493 # Number of instructions executed
+system.cpu.num_refs 2003 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 23:03:02
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 6 2008 00:18:22
-M5 executing on zizzer
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Exiting @ tick 5518000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 106773 # Simulator instruction rate (inst/s)
-host_mem_usage 197592 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
-host_tick_rate 379942758 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 9493 # Number of instructions simulated
-sim_seconds 0.000034 # Number of seconds simulated
-sim_ticks 33851000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 999 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3024000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.051282 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2862000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.051282 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13.939850 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 1987 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1835 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8512000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.076497 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 152 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.076497 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1835 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8512000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.076497 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 152 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.076497 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 81.582554 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_accesses 11007 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 10779 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.020714 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.020714 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 47.276316 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 11007 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
-system.cpu.icache.demand_hits 10779 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.020714 # miss rate for demand accesses
-system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.020714 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 11007 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 10779 # number of overall hits
-system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.020714 # miss rate for overall accesses
-system.cpu.icache.overall_misses 228 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.020714 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 107.509501 # Cycle average of tags in use
-system.cpu.icache.total_refs 10779 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 282 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 14612000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.996454 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 281 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 11240000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996454 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 281 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.003817 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 361 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 18720000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.997230 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 360 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 14400000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.997230 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 360 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 18720000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.997230 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 360 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 14400000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.997230 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 360 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 129.102217 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 67702 # number of cpu cycles simulated
-system.cpu.num_insts 9493 # Number of instructions executed
-system.cpu.num_refs 2003 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 7 2008 03:21:37
+M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5
+M5 commit date Thu Nov 06 23:13:50 2008 -0800
+M5 started Nov 8 2008 00:19:20
+M5 executing on tater
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 33851000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 106773 # Simulator instruction rate (inst/s)
+host_mem_usage 197592 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 379942758 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 9493 # Number of instructions simulated
+sim_seconds 0.000034 # Number of seconds simulated
+sim_ticks 33851000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 999 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3024000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.051282 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2862000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.051282 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 13.939850 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 1987 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1835 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 8512000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.076497 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 152 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.076497 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 1835 # number of overall hits
+system.cpu.dcache.overall_miss_latency 8512000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.076497 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 152 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.076497 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 81.582554 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_accesses 11007 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 10779 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.020714 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.020714 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 47.276316 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 11007 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
+system.cpu.icache.demand_hits 10779 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.020714 # miss rate for demand accesses
+system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.020714 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 11007 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 10779 # number of overall hits
+system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.020714 # miss rate for overall accesses
+system.cpu.icache.overall_misses 228 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.020714 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 107.509501 # Cycle average of tags in use
+system.cpu.icache.total_refs 10779 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 282 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 14612000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.996454 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 281 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 11240000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996454 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 281 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.003817 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 361 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 18720000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.997230 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 360 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 14400000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.997230 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 360 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 1 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 18720000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.997230 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 360 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 14400000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.997230 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 360 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 129.102217 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 67702 # number of cpu cycles simulated
+system.cpu.num_insts 9493 # Number of instructions executed
+system.cpu.num_refs 2003 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
-warn: instruction 'fldcw_Mw' unimplemented
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 7 2008 03:21:37
-M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5
-M5 commit date Thu Nov 06 23:13:50 2008 -0800
-M5 started Nov 8 2008 00:19:20
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Exiting @ tick 33851000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 916 # Number of BTB hits
-global.BPredUnit.BTBLookups 4733 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 3153 # Number of conditional branches predicted
-global.BPredUnit.lookups 5548 # Number of BP lookups
-global.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target.
-host_inst_rate 85524 # Simulator instruction rate (inst/s)
-host_mem_usage 199540 # Number of bytes of host memory used
-host_seconds 0.15 # Real time elapsed on the host
-host_tick_rate 95322021 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads.
-memdepunit.memDep.conflictingLoads 58 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 4 # Number of conflicting stores.
-memdepunit.memDep.conflictingStores 32 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2431 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedLoads 2520 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1282 # Number of stores inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1303 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 12773 # Number of instructions simulated
-sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 14251500 # Number of ticks simulated
-system.cpu.commit.COM:branches 2102 # Number of branches committed
-system.cpu.commit.COM:branches_0 1051 # Number of branches committed
-system.cpu.commit.COM:branches_1 1051 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 22837
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 16880 7391.51%
- 1 3016 1320.66%
- 2 1386 606.91%
- 3 576 252.22%
- 4 326 142.75%
- 5 268 117.35%
- 6 170 74.44%
- 7 93 40.72%
- 8 122 53.42%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 12807 # Number of instructions committed
-system.cpu.commit.COM:count_0 6403 # Number of instructions committed
-system.cpu.commit.COM:count_1 6404 # Number of instructions committed
-system.cpu.commit.COM:loads 2370 # Number of loads committed
-system.cpu.commit.COM:loads_0 1185 # Number of loads committed
-system.cpu.commit.COM:loads_1 1185 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed
-system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 4100 # Number of memory references committed
-system.cpu.commit.COM:refs_0 2050 # Number of memory references committed
-system.cpu.commit.COM:refs_1 2050 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed
-system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit
-system.cpu.committedInsts_0 6386 # Number of Instructions Simulated
-system.cpu.committedInsts_1 6387 # Number of Instructions Simulated
-system.cpu.committedInsts_total 12773 # Number of Instructions Simulated
-system.cpu.cpi_0 4.463514 # CPI: Cycles Per Instruction
-system.cpu.cpi_1 4.462815 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses_0 3925 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency_0 35473.913043 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36849.514563 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 3580 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits_0 3580 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 12238500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency_0 12238500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate_0 0.087898 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 345 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses_0 345 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 139 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits_0 139 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency_0 7591000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052484 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 206 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses_0 206 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses_0 1730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency_0 33703.947368 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36103.448276 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits_0 970 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 25615000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency_0 25615000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate_0 0.439306 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses_0 760 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 586 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits_0 586 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 6282000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency_0 6282000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100578 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses_0 5655 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency_0 34256.561086 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_hits 4550 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits_0 4550 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 37853500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency_0 37853500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate_0 0.195402 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1105 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses_0 1105 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 725 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits_0 725 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 13873000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency_0 13873000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate_0 0.067197 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 380 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses_0 380 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated
-system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 5655 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses_0 5655 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency_0 34256.561086 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 4550 # number of overall hits
-system.cpu.dcache.overall_hits_0 4550 # number of overall hits
-system.cpu.dcache.overall_hits_1 0 # number of overall hits
-system.cpu.dcache.overall_miss_latency 37853500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency_0 37853500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate_0 0.195402 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1105 # number of overall misses
-system.cpu.dcache.overall_misses_0 1105 # number of overall misses
-system.cpu.dcache.overall_misses_1 0 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 725 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits_0 725 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 13873000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency_0 13873000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate_0 0.067197 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 380 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses_0 380 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.replacements_0 0 # number of replacements
-system.cpu.dcache.replacements_1 0 # number of replacements
-system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use
-system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dcache.writebacks_0 0 # number of writebacks
-system.cpu.dcache.writebacks_1 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 33392 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 4878 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 2128 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 668 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 186 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 6300 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 6155 # DTB hits
-system.cpu.dtb.misses 145 # DTB misses
-system.cpu.dtb.read_accesses 4144 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 4056 # DTB read hits
-system.cpu.dtb.read_misses 88 # DTB read misses
-system.cpu.dtb.write_accesses 2156 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 2099 # DTB write hits
-system.cpu.dtb.write_misses 57 # DTB write misses
-system.cpu.fetch.Branches 5548 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 4113 # Number of cache lines fetched
-system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 1714 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 22904
-system.cpu.fetch.rateDist.min_value 0
- 0 17622 7693.85%
- 1 416 181.63%
- 2 353 154.12%
- 3 477 208.26%
- 4 425 185.56%
- 5 349 152.38%
- 6 442 192.98%
- 7 261 113.95%
- 8 2559 1117.27%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses_0 4113 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency_0 35793.697979 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35516.155089 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 3272 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits_0 3272 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 30102500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency_0 30102500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate_0 0.204474 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 841 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses_0 841 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits_0 222 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 21984500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency_0 21984500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate_0 0.150498 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 4113 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses_0 4113 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency_0 35793.697979 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits
-system.cpu.icache.demand_hits_0 3272 # number of demand (read+write) hits
-system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 30102500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency_0 30102500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate_0 0.204474 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.icache.demand_misses 841 # number of demand (read+write) misses
-system.cpu.icache.demand_misses_0 841 # number of demand (read+write) misses
-system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits_0 222 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 21984500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency_0 21984500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate_0 0.150498 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated
-system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses_0 4113 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency_0 35793.697979 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 3272 # number of overall hits
-system.cpu.icache.overall_hits_0 3272 # number of overall hits
-system.cpu.icache.overall_hits_1 0 # number of overall hits
-system.cpu.icache.overall_miss_latency 30102500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency_0 30102500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate_0 0.204474 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.icache.overall_misses 841 # number of overall misses
-system.cpu.icache.overall_misses_0 841 # number of overall misses
-system.cpu.icache.overall_misses_1 0 # number of overall misses
-system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits_0 222 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 21984500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency_0 21984500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate_0 0.150498 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 6 # number of replacements
-system.cpu.icache.replacements_0 6 # number of replacements
-system.cpu.icache.replacements_1 0 # number of replacements
-system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use
-system.cpu.icache.total_refs 3272 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.writebacks_0 0 # number of writebacks
-system.cpu.icache.writebacks_1 0 # number of writebacks
-system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 3160 # Number of branches executed
-system.cpu.iew.EXEC:branches_0 1573 # Number of branches executed
-system.cpu.iew.EXEC:branches_1 1587 # Number of branches executed
-system.cpu.iew.EXEC:nop 135 # number of nop insts executed
-system.cpu.iew.EXEC:nop_0 70 # number of nop insts executed
-system.cpu.iew.EXEC:nop_1 65 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate
-system.cpu.iew.EXEC:refs 6321 # number of memory reference insts executed
-system.cpu.iew.EXEC:refs_0 3132 # number of memory reference insts executed
-system.cpu.iew.EXEC:refs_1 3189 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 2175 # Number of stores executed
-system.cpu.iew.EXEC:stores_0 1090 # Number of stores executed
-system.cpu.iew.EXEC:stores_1 1085 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed
-system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 11901 # num instructions consuming a value
-system.cpu.iew.WB:consumers_0 5984 # num instructions consuming a value
-system.cpu.iew.WB:consumers_1 5917 # num instructions consuming a value
-system.cpu.iew.WB:count 18426 # cumulative count of insts written-back
-system.cpu.iew.WB:count_0 9221 # cumulative count of insts written-back
-system.cpu.iew.WB:count_1 9205 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 1.552811 # average fanout of values written-back
-system.cpu.iew.WB:fanout_0 0.776404 # average fanout of values written-back
-system.cpu.iew.WB:fanout_1 0.776407 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 9240 # num instructions producing a value
-system.cpu.iew.WB:producers_0 4646 # num instructions producing a value
-system.cpu.iew.WB:producers_1 4594 # num instructions producing a value
-system.cpu.iew.WB:rate 0.646436 # insts written-back per cycle
-system.cpu.iew.WB:rate_0 0.323498 # insts written-back per cycle
-system.cpu.iew.WB:rate_1 0.322937 # insts written-back per cycle
-system.cpu.iew.WB:sent 18664 # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent_0 9324 # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent_1 9340 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 4146 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts_0 2042 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts_1 2104 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 2128 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1246 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 417 # Number of stores squashed
-system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.1.forwLoads 72 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.1.squashedLoads 1335 # Number of loads squashed
-system.cpu.iew.lsq.thread.1.squashedStores 438 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc_0 0.224039 # IPC: Instructions Per Cycle
-system.cpu.ipc_1 0.224074 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 10179 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 2 0.02% # Type of FU issued
- IntAlu 6830 67.10% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 2173 21.35% # Type of FU issued
- MemWrite 1171 11.50% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:FU_type_1 10211 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1.start_dist
- No_OpClass 2 0.02% # Type of FU issued
- IntAlu 6842 67.01% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 2230 21.84% # Type of FU issued
- MemWrite 1134 11.11% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1.end_dist
-system.cpu.iq.ISSUE:FU_type 20390 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type.start_dist
- No_OpClass 4 0.02% # Type of FU issued
- IntAlu 13672 67.05% # Type of FU issued
- IntMult 2 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 4 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 4403 21.59% # Type of FU issued
- MemWrite 2305 11.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 172 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt_0 87 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt_1 85 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.008436 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate_0 0.004267 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate_1 0.004169 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 13 7.56% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 96 55.81% # attempts to use FU when none available
- MemWrite 63 36.63% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 22904
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 14156 6180.58%
- 1 3289 1435.99%
- 2 2351 1026.46%
- 3 1373 599.46%
- 4 854 372.86%
- 5 535 233.58%
- 6 261 113.95%
- 7 57 24.89%
- 8 28 12.22%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate
-system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 9662 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 5422 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 4162 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 4113 # ITB hits
-system.cpu.itb.misses 49 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34643.835616 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31589.041096 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 5058000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency_0 5058000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4612000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4612000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses_0 825 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency_0 34555.285541 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31414.337789 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 28439000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency_0 28439000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate_0 0.997576 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses_0 823 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 25854000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25854000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997576 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 823 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses_0 823 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34482.142857 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31357.142857 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 965500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency_0 965500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 878000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 878000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6750 # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 4 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 27000 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses_0 971 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency_0 34568.627451 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 33497000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency_0 33497000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate_0 0.997940 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses_0 969 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 30466000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency_0 30466000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate_0 0.997940 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 969 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses_0 969 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated
-system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses_0 971 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency_0 34568.627451 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_hits_0 2 # number of overall hits
-system.cpu.l2cache.overall_hits_1 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 33497000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency_0 33497000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate_0 0.997940 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 969 # number of overall misses
-system.cpu.l2cache.overall_misses_0 969 # number of overall misses
-system.cpu.l2cache.overall_misses_1 0 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 30466000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency_0 30466000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate_0 0.997940 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 969 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses_0 969 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.replacements_0 0 # number of replacements
-system.cpu.l2cache.replacements_1 0 # number of replacements
-system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.writebacks_0 0 # number of writebacks
-system.cpu.l2cache.writebacks_1 0 # number of writebacks
-system.cpu.numCycles 28504 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 33866 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 1399 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 32685 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 26128 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 19538 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 4546 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed
-system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
-system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:28:54
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Hello world!
+Exiting @ tick 14251500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 916 # Number of BTB hits
+global.BPredUnit.BTBLookups 4733 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 3153 # Number of conditional branches predicted
+global.BPredUnit.lookups 5548 # Number of BP lookups
+global.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target.
+host_inst_rate 85524 # Simulator instruction rate (inst/s)
+host_mem_usage 199540 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
+host_tick_rate 95322021 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads.
+memdepunit.memDep.conflictingLoads 58 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 4 # Number of conflicting stores.
+memdepunit.memDep.conflictingStores 32 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 2431 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 2520 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1282 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1303 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 12773 # Number of instructions simulated
+sim_seconds 0.000014 # Number of seconds simulated
+sim_ticks 14251500 # Number of ticks simulated
+system.cpu.commit.COM:branches 2102 # Number of branches committed
+system.cpu.commit.COM:branches_0 1051 # Number of branches committed
+system.cpu.commit.COM:branches_1 1051 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 22837
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 16880 7391.51%
+ 1 3016 1320.66%
+ 2 1386 606.91%
+ 3 576 252.22%
+ 4 326 142.75%
+ 5 268 117.35%
+ 6 170 74.44%
+ 7 93 40.72%
+ 8 122 53.42%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 12807 # Number of instructions committed
+system.cpu.commit.COM:count_0 6403 # Number of instructions committed
+system.cpu.commit.COM:count_1 6404 # Number of instructions committed
+system.cpu.commit.COM:loads 2370 # Number of loads committed
+system.cpu.commit.COM:loads_0 1185 # Number of loads committed
+system.cpu.commit.COM:loads_1 1185 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed
+system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 4100 # Number of memory references committed
+system.cpu.commit.COM:refs_0 2050 # Number of memory references committed
+system.cpu.commit.COM:refs_1 2050 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed
+system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit
+system.cpu.committedInsts_0 6386 # Number of Instructions Simulated
+system.cpu.committedInsts_1 6387 # Number of Instructions Simulated
+system.cpu.committedInsts_total 12773 # Number of Instructions Simulated
+system.cpu.cpi_0 4.463514 # CPI: Cycles Per Instruction
+system.cpu.cpi_1 4.462815 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses_0 3925 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency_0 35473.913043 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36849.514563 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 3580 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits_0 3580 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 12238500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency_0 12238500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate_0 0.087898 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 345 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses_0 345 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 139 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits_0 139 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency_0 7591000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052484 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 206 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses_0 206 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses_0 1730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency_0 33703.947368 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36103.448276 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits_0 970 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 25615000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency_0 25615000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate_0 0.439306 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses_0 760 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 586 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits_0 586 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 6282000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency_0 6282000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100578 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses_0 5655 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency_0 34256.561086 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
+system.cpu.dcache.demand_hits 4550 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits_0 4550 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 37853500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency_0 37853500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate_0 0.195402 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1105 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses_0 1105 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 725 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits_0 725 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 13873000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency_0 13873000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate_0 0.067197 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 380 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses_0 380 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated
+system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 5655 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses_0 5655 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency_0 34256.561086 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 4550 # number of overall hits
+system.cpu.dcache.overall_hits_0 4550 # number of overall hits
+system.cpu.dcache.overall_hits_1 0 # number of overall hits
+system.cpu.dcache.overall_miss_latency 37853500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency_0 37853500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate_0 0.195402 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1105 # number of overall misses
+system.cpu.dcache.overall_misses_0 1105 # number of overall misses
+system.cpu.dcache.overall_misses_1 0 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 725 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits_0 725 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 13873000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency_0 13873000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate_0 0.067197 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 380 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses_0 380 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.replacements_0 0 # number of replacements
+system.cpu.dcache.replacements_1 0 # number of replacements
+system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.dcache.writebacks_0 0 # number of writebacks
+system.cpu.dcache.writebacks_1 0 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 33392 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 4878 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 2128 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 668 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 186 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 6300 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 6155 # DTB hits
+system.cpu.dtb.misses 145 # DTB misses
+system.cpu.dtb.read_accesses 4144 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 4056 # DTB read hits
+system.cpu.dtb.read_misses 88 # DTB read misses
+system.cpu.dtb.write_accesses 2156 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 2099 # DTB write hits
+system.cpu.dtb.write_misses 57 # DTB write misses
+system.cpu.fetch.Branches 5548 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 4113 # Number of cache lines fetched
+system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 1714 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 22904
+system.cpu.fetch.rateDist.min_value 0
+ 0 17622 7693.85%
+ 1 416 181.63%
+ 2 353 154.12%
+ 3 477 208.26%
+ 4 425 185.56%
+ 5 349 152.38%
+ 6 442 192.98%
+ 7 261 113.95%
+ 8 2559 1117.27%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses_0 4113 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency_0 35793.697979 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35516.155089 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 3272 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits_0 3272 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 30102500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency_0 30102500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate_0 0.204474 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 841 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses_0 841 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits_0 222 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 21984500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency_0 21984500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate_0 0.150498 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 4113 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses_0 4113 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency_0 35793.697979 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
+system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits
+system.cpu.icache.demand_hits_0 3272 # number of demand (read+write) hits
+system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 30102500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency_0 30102500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate_0 0.204474 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
+system.cpu.icache.demand_misses 841 # number of demand (read+write) misses
+system.cpu.icache.demand_misses_0 841 # number of demand (read+write) misses
+system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits_0 222 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 21984500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency_0 21984500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate_0 0.150498 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated
+system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses_0 4113 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency_0 35793.697979 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 3272 # number of overall hits
+system.cpu.icache.overall_hits_0 3272 # number of overall hits
+system.cpu.icache.overall_hits_1 0 # number of overall hits
+system.cpu.icache.overall_miss_latency 30102500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency_0 30102500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate_0 0.204474 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
+system.cpu.icache.overall_misses 841 # number of overall misses
+system.cpu.icache.overall_misses_0 841 # number of overall misses
+system.cpu.icache.overall_misses_1 0 # number of overall misses
+system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits_0 222 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 21984500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency_0 21984500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate_0 0.150498 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 6 # number of replacements
+system.cpu.icache.replacements_0 6 # number of replacements
+system.cpu.icache.replacements_1 0 # number of replacements
+system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use
+system.cpu.icache.total_refs 3272 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.writebacks_0 0 # number of writebacks
+system.cpu.icache.writebacks_1 0 # number of writebacks
+system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 3160 # Number of branches executed
+system.cpu.iew.EXEC:branches_0 1573 # Number of branches executed
+system.cpu.iew.EXEC:branches_1 1587 # Number of branches executed
+system.cpu.iew.EXEC:nop 135 # number of nop insts executed
+system.cpu.iew.EXEC:nop_0 70 # number of nop insts executed
+system.cpu.iew.EXEC:nop_1 65 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate
+system.cpu.iew.EXEC:refs 6321 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_0 3132 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_1 3189 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 2175 # Number of stores executed
+system.cpu.iew.EXEC:stores_0 1090 # Number of stores executed
+system.cpu.iew.EXEC:stores_1 1085 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed
+system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 11901 # num instructions consuming a value
+system.cpu.iew.WB:consumers_0 5984 # num instructions consuming a value
+system.cpu.iew.WB:consumers_1 5917 # num instructions consuming a value
+system.cpu.iew.WB:count 18426 # cumulative count of insts written-back
+system.cpu.iew.WB:count_0 9221 # cumulative count of insts written-back
+system.cpu.iew.WB:count_1 9205 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 1.552811 # average fanout of values written-back
+system.cpu.iew.WB:fanout_0 0.776404 # average fanout of values written-back
+system.cpu.iew.WB:fanout_1 0.776407 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 9240 # num instructions producing a value
+system.cpu.iew.WB:producers_0 4646 # num instructions producing a value
+system.cpu.iew.WB:producers_1 4594 # num instructions producing a value
+system.cpu.iew.WB:rate 0.646436 # insts written-back per cycle
+system.cpu.iew.WB:rate_0 0.323498 # insts written-back per cycle
+system.cpu.iew.WB:rate_1 0.322937 # insts written-back per cycle
+system.cpu.iew.WB:sent 18664 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_0 9324 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_1 9340 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 4146 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_0 2042 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_1 2104 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 2128 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1246 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 417 # Number of stores squashed
+system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.1.forwLoads 72 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.1.squashedLoads 1335 # Number of loads squashed
+system.cpu.iew.lsq.thread.1.squashedStores 438 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc_0 0.224039 # IPC: Instructions Per Cycle
+system.cpu.ipc_1 0.224074 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 10179 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 2 0.02% # Type of FU issued
+ IntAlu 6830 67.10% # Type of FU issued
+ IntMult 1 0.01% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2 0.02% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 2173 21.35% # Type of FU issued
+ MemWrite 1171 11.50% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:FU_type_1 10211 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_1.start_dist
+ No_OpClass 2 0.02% # Type of FU issued
+ IntAlu 6842 67.01% # Type of FU issued
+ IntMult 1 0.01% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2 0.02% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 2230 21.84% # Type of FU issued
+ MemWrite 1134 11.11% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_1.end_dist
+system.cpu.iq.ISSUE:FU_type 20390 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type.start_dist
+ No_OpClass 4 0.02% # Type of FU issued
+ IntAlu 13672 67.05% # Type of FU issued
+ IntMult 2 0.01% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 4 0.02% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 4403 21.59% # Type of FU issued
+ MemWrite 2305 11.30% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 172 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt_0 87 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt_1 85 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.008436 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_0 0.004267 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_1 0.004169 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 13 7.56% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 96 55.81% # attempts to use FU when none available
+ MemWrite 63 36.63% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 22904
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 14156 6180.58%
+ 1 3289 1435.99%
+ 2 2351 1026.46%
+ 3 1373 599.46%
+ 4 854 372.86%
+ 5 535 233.58%
+ 6 261 113.95%
+ 7 57 24.89%
+ 8 28 12.22%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate
+system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 9662 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 5422 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 4162 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 4113 # ITB hits
+system.cpu.itb.misses 49 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34643.835616 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31589.041096 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 5058000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency_0 5058000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4612000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4612000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses_0 825 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency_0 34555.285541 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31414.337789 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 28439000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency_0 28439000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate_0 0.997576 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses_0 823 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 25854000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25854000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997576 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 823 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses_0 823 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34482.142857 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31357.142857 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 965500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency_0 965500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 878000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 878000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6750 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 4 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 27000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses_0 971 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency_0 34568.627451 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 33497000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency_0 33497000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate_0 0.997940 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses_0 969 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 30466000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency_0 30466000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate_0 0.997940 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 969 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses_0 969 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated
+system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses_0 971 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency_0 34568.627451 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.overall_hits_0 2 # number of overall hits
+system.cpu.l2cache.overall_hits_1 0 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 33497000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency_0 33497000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate_0 0.997940 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 969 # number of overall misses
+system.cpu.l2cache.overall_misses_0 969 # number of overall misses
+system.cpu.l2cache.overall_misses_1 0 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 30466000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency_0 30466000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate_0 0.997940 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 969 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses_0 969 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.replacements_0 0 # number of replacements
+system.cpu.l2cache.replacements_1 0 # number of replacements
+system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.l2cache.writebacks_0 0 # number of writebacks
+system.cpu.l2cache.writebacks_1 0 # number of writebacks
+system.cpu.numCycles 28504 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 33866 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1399 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 32685 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 26128 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 19538 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 4546 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed
+system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
+system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Increasing stack size by one page.
-warn: Increasing stack size by one page.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:28:54
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Hello world!
-Hello world!
-Exiting @ tick 14251500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 4398 # Number of BTB hits
-global.BPredUnit.BTBLookups 9844 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 11413 # Number of conditional branches predicted
-global.BPredUnit.lookups 11413 # Number of BP lookups
-global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-host_inst_rate 55497 # Simulator instruction rate (inst/s)
-host_mem_usage 199732 # Number of bytes of host memory used
-host_seconds 0.26 # Real time elapsed on the host
-host_tick_rate 106451563 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 0 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 4960 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 3415 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 14449 # Number of instructions simulated
-sim_seconds 0.000028 # Number of seconds simulated
-sim_ticks 27756500 # Number of ticks simulated
-system.cpu.commit.COM:branches 3359 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 103 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 42766
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 34594 8089.14%
- 1 4804 1123.32%
- 2 1741 407.10%
- 3 720 168.36%
- 4 413 96.57%
- 5 144 33.67%
- 6 196 45.83%
- 7 51 11.93%
- 8 103 24.08%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 15175 # Number of instructions committed
-system.cpu.commit.COM:loads 2226 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 3674 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 2923 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 19906 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 14449 # Number of Instructions Simulated
-system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
-system.cpu.cpi 3.842065 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.842065 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 3844 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 35152.173913 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35569.230769 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4042500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.029917 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2312000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.016909 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
-system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
-system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 31253.950339 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35632.352941 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 13845500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 3634500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 32.229730 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 32057.347670 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 4728 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 17888000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.105562 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 558 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 391 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5946500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.031593 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 4728 # number of overall hits
-system.cpu.dcache.overall_miss_latency 17888000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.105562 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 558 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 391 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5946500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.031593 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 108.665251 # Cycle average of tags in use
-system.cpu.dcache.total_refs 4770 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 7143 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 51830 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 20508 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 14980 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 135 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 11413 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 7356 # Number of cache lines fetched
-system.cpu.fetch.Cycles 24020 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 845 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 58247 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 3019 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.205588 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.049231 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 47090
-system.cpu.fetch.rateDist.min_value 0
- 0 30448 6465.92%
- 1 7532 1599.49%
- 2 1217 258.44%
- 3 1059 224.89%
- 4 1060 225.10%
- 5 1193 253.34%
- 6 711 150.99%
- 7 327 69.44%
- 8 3543 752.39%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 7356 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 33620.560748 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 6821 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 17987000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.072730 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.048804 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 19.053073 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 7356 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 33620.560748 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
-system.cpu.icache.demand_hits 6821 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 17987000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.072730 # miss rate for demand accesses
-system.cpu.icache.demand_misses 535 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.048804 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 6821 # number of overall hits
-system.cpu.icache.overall_miss_latency 17987000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.072730 # miss rate for overall accesses
-system.cpu.icache.overall_misses 535 # number of overall misses
-system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.048804 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 226.836007 # Cycle average of tags in use
-system.cpu.icache.total_refs 6821 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 8424 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 4842 # Number of branches executed
-system.cpu.iew.EXEC:nop 2091 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.447815 # Inst execution rate
-system.cpu.iew.EXEC:refs 6412 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 2454 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 13039 # num instructions consuming a value
-system.cpu.iew.WB:count 23891 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.827287 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 10787 # num instructions producing a value
-system.cpu.iew.WB:rate 0.430360 # insts written-back per cycle
-system.cpu.iew.WB:sent 24098 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 3211 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 4960 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 3053 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 3415 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 3958 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 4360 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 24860 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 34 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 2734 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 1967 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 758 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 2453 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.260277 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.260277 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 29220 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 0 0.00% # Type of FU issued
- IntAlu 21395 73.22% # Type of FU issued
- IntMult 0 0.00% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 0 0.00% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 4720 16.15% # Type of FU issued
- MemWrite 3105 10.63% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.005921 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 40 23.12% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 20 11.56% # attempts to use FU when none available
- MemWrite 113 65.32% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 47090
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 34112 7244.00%
- 1 5516 1171.37%
- 2 3070 651.94%
- 3 2146 455.72%
- 4 997 211.72%
- 5 653 138.67%
- 6 342 72.63%
- 7 211 44.81%
- 8 43 9.13%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate
-system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 15806 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 120 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 12375 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34409.638554 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31307.228916 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2856000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2598500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34221.428571 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.333333 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 14373000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 13023500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34394.736842 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 653500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34252.485089 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 17229000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 15622000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 4 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 17229000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 503 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 15622000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 251.642612 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 55514 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 22322 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 74771 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 42575 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 13324 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 311 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 6777 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 5129 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 820 # count of temporary serializing insts renamed
-system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:43:55
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Begining test of difficult SPARC instructions...
+LDSTUB: Passed
+SWAP: Passed
+CAS FAIL: Passed
+CAS WORK: Passed
+CASX FAIL: Passed
+CASX WORK: Passed
+LDTX: Passed
+LDTW: Passed
+STTW: Passed
+Done
+Exiting @ tick 27756500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 4398 # Number of BTB hits
+global.BPredUnit.BTBLookups 9844 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 11413 # Number of conditional branches predicted
+global.BPredUnit.lookups 11413 # Number of BP lookups
+global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+host_inst_rate 55497 # Simulator instruction rate (inst/s)
+host_mem_usage 199732 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
+host_tick_rate 106451563 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 0 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 4960 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 3415 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 14449 # Number of instructions simulated
+sim_seconds 0.000028 # Number of seconds simulated
+sim_ticks 27756500 # Number of ticks simulated
+system.cpu.commit.COM:branches 3359 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 103 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 42766
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 34594 8089.14%
+ 1 4804 1123.32%
+ 2 1741 407.10%
+ 3 720 168.36%
+ 4 413 96.57%
+ 5 144 33.67%
+ 6 196 45.83%
+ 7 51 11.93%
+ 8 103 24.08%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 15175 # Number of instructions committed
+system.cpu.commit.COM:loads 2226 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 3674 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 2923 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 19906 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 14449 # Number of Instructions Simulated
+system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
+system.cpu.cpi 3.842065 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.842065 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 3844 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 35152.173913 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35569.230769 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4042500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.029917 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2312000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.016909 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
+system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 31253.950339 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35632.352941 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 13845500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 3634500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 32.229730 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 32057.347670 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 4728 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 17888000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.105562 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 558 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 391 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5946500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.031593 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 4728 # number of overall hits
+system.cpu.dcache.overall_miss_latency 17888000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.105562 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 558 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 391 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5946500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.031593 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 108.665251 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4770 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 7143 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 51830 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 20508 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 14980 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 135 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 11413 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 7356 # Number of cache lines fetched
+system.cpu.fetch.Cycles 24020 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 845 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 58247 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 3019 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.205588 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.049231 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 47090
+system.cpu.fetch.rateDist.min_value 0
+ 0 30448 6465.92%
+ 1 7532 1599.49%
+ 2 1217 258.44%
+ 3 1059 224.89%
+ 4 1060 225.10%
+ 5 1193 253.34%
+ 6 711 150.99%
+ 7 327 69.44%
+ 8 3543 752.39%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 7356 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 33620.560748 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 6821 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 17987000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.072730 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.048804 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 19.053073 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 7356 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 33620.560748 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
+system.cpu.icache.demand_hits 6821 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 17987000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.072730 # miss rate for demand accesses
+system.cpu.icache.demand_misses 535 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.048804 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 6821 # number of overall hits
+system.cpu.icache.overall_miss_latency 17987000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.072730 # miss rate for overall accesses
+system.cpu.icache.overall_misses 535 # number of overall misses
+system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.048804 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 226.836007 # Cycle average of tags in use
+system.cpu.icache.total_refs 6821 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 8424 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 4842 # Number of branches executed
+system.cpu.iew.EXEC:nop 2091 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.447815 # Inst execution rate
+system.cpu.iew.EXEC:refs 6412 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 2454 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 13039 # num instructions consuming a value
+system.cpu.iew.WB:count 23891 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.827287 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 10787 # num instructions producing a value
+system.cpu.iew.WB:rate 0.430360 # insts written-back per cycle
+system.cpu.iew.WB:sent 24098 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 3211 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 4960 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 3053 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 3415 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 3958 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 4360 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 24860 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 34 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 2734 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 1967 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 758 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 2453 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.260277 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.260277 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 29220 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 0 0.00% # Type of FU issued
+ IntAlu 21395 73.22% # Type of FU issued
+ IntMult 0 0.00% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 0 0.00% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 4720 16.15% # Type of FU issued
+ MemWrite 3105 10.63% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.005921 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 40 23.12% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 20 11.56% # attempts to use FU when none available
+ MemWrite 113 65.32% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 47090
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 34112 7244.00%
+ 1 5516 1171.37%
+ 2 3070 651.94%
+ 3 2146 455.72%
+ 4 997 211.72%
+ 5 653 138.67%
+ 6 342 72.63%
+ 7 211 44.81%
+ 8 43 9.13%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate
+system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 15806 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 120 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 12375 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34409.638554 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31307.228916 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2856000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2598500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34221.428571 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.333333 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 14373000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 13023500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34394.736842 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 653500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34252.485089 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 17229000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 15622000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 4 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 17229000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 503 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 15622000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 251.642612 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 55514 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 22322 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 74771 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 42575 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 13324 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 311 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 6777 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 5129 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 820 # count of temporary serializing insts renamed
+system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:43:55
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/o3-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Begining test of difficult SPARC instructions...
-LDSTUB: Passed
-SWAP: Passed
-CAS FAIL: Passed
-CAS WORK: Passed
-CASX FAIL: Passed
-CASX WORK: Passed
-LDTX: Passed
-LDTW: Passed
-STTW: Passed
-Done
-Exiting @ tick 27756500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 641188 # Simulator instruction rate (inst/s)
-host_mem_usage 191520 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 319099476 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 15175 # Number of instructions simulated
-sim_seconds 0.000008 # Number of seconds simulated
-sim_ticks 7618500 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 15238 # number of cpu cycles simulated
-system.cpu.num_insts 15175 # Number of instructions executed
-system.cpu.num_refs 3684 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:43:56
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Begining test of difficult SPARC instructions...
+LDSTUB: Passed
+SWAP: Passed
+CAS FAIL: Passed
+CAS WORK: Passed
+CASX FAIL: Passed
+CASX WORK: Passed
+LDTX: Passed
+LDTW: Passed
+STTW: Passed
+Done
+Exiting @ tick 7618500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 641188 # Simulator instruction rate (inst/s)
+host_mem_usage 191520 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 319099476 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 15175 # Number of instructions simulated
+sim_seconds 0.000008 # Number of seconds simulated
+sim_ticks 7618500 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 15238 # number of cpu cycles simulated
+system.cpu.num_insts 15175 # Number of instructions executed
+system.cpu.num_refs 3684 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:43:56
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Begining test of difficult SPARC instructions...
-LDSTUB: Passed
-SWAP: Passed
-CAS FAIL: Passed
-CAS WORK: Passed
-CASX FAIL: Passed
-CASX WORK: Passed
-LDTX: Passed
-LDTW: Passed
-STTW: Passed
-Done
-Exiting @ tick 7618500 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 494848 # Simulator instruction rate (inst/s)
-host_mem_usage 199068 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
-host_tick_rate 1383502218 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 15175 # Number of instructions simulated
-sim_seconds 0.000043 # Number of seconds simulated
-sim_ticks 42735000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2809000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses
-system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
-system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 1340 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5712000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.070735 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 102 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5406000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 3513 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8680000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.042257 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 155 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 8215000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.042257 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 3513 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8680000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 155 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 8215000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.042257 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 97.747327 # Cycle average of tags in use
-system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency
-system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses
-system.cpu.icache.demand_misses 280 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 14941 # number of overall hits
-system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses
-system.cpu.icache.overall_misses 280 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 153.073222 # Cycle average of tags in use
-system.cpu.icache.total_refs 14941 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 4420000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 3400000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 17212000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 680000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.006369 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 21632000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 16640000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 416 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 16640000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 174.433606 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 85470 # number of cpu cycles simulated
-system.cpu.num_insts 15175 # Number of instructions executed
-system.cpu.num_refs 3684 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Nov 5 2008 22:40:47
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov 5 2008 22:43:56
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Begining test of difficult SPARC instructions...
+LDSTUB: Passed
+SWAP: Passed
+CAS FAIL: Passed
+CAS WORK: Passed
+CASX FAIL: Passed
+CASX WORK: Passed
+LDTX: Passed
+LDTW: Passed
+STTW: Passed
+Done
+Exiting @ tick 42735000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 494848 # Simulator instruction rate (inst/s)
+host_mem_usage 199068 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
+host_tick_rate 1383502218 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 15175 # Number of instructions simulated
+sim_seconds 0.000043 # Number of seconds simulated
+sim_ticks 42735000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2809000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
+system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 1340 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 5712000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.070735 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 102 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 5406000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 3513 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 8680000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.042257 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 155 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 8215000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.042257 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 3513 # number of overall hits
+system.cpu.dcache.overall_miss_latency 8680000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 155 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 8215000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.042257 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 97.747327 # Cycle average of tags in use
+system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency
+system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses
+system.cpu.icache.demand_misses 280 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 14941 # number of overall hits
+system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses
+system.cpu.icache.overall_misses 280 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 153.073222 # Cycle average of tags in use
+system.cpu.icache.total_refs 14941 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 4420000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 3400000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 17212000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 680000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.006369 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 21632000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 16640000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 416 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 16640000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 174.433606 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 85470 # number of cpu cycles simulated
+system.cpu.num_insts 15175 # Number of instructions executed
+system.cpu.num_refs 3684 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Nov 5 2008 22:40:47
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:43:56
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/02.insttest/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Begining test of difficult SPARC instructions...
-LDSTUB: Passed
-SWAP: Passed
-CAS FAIL: Passed
-CAS WORK: Passed
-CASX FAIL: Passed
-CASX WORK: Passed
-LDTX: Passed
-LDTW: Passed
-STTW: Passed
-Done
-Exiting @ tick 42735000 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 3333474 # Simulator instruction rate (inst/s)
-host_mem_usage 290708 # Number of bytes of host memory used
-host_seconds 18.93 # Real time elapsed on the host
-host_tick_rate 98784311223 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 63113507 # Number of instructions simulated
-sim_seconds 1.870336 # Number of seconds simulated
-sim_ticks 1870335522500 # Number of ticks simulated
-system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses
-system.cpu0.dcache.ReadReq_accesses 8975619 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_hits 7292050 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 1683569 # number of ReadReq misses
-system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses
-system.cpu0.dcache.WriteReq_accesses 5746054 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits 5372248 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses
-system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 6.625587 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 14721673 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 12664298 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 2057375 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 14721673 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 12664298 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 2057375 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.dcache.replacements 1978967 # number of replacements
-system.cpu0.dcache.sampled_refs 1979479 # Sample count of references to valid blocks.
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 504.827685 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 13115211 # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 396793 # number of writebacks
-system.cpu0.dtb.accesses 698037 # DTB accesses
-system.cpu0.dtb.acv 251 # DTB access violations
-system.cpu0.dtb.hits 15082911 # DTB hits
-system.cpu0.dtb.misses 7805 # DTB misses
-system.cpu0.dtb.read_accesses 508987 # DTB read accesses
-system.cpu0.dtb.read_acv 152 # DTB read access violations
-system.cpu0.dtb.read_hits 9148351 # DTB read hits
-system.cpu0.dtb.read_misses 7079 # DTB read misses
-system.cpu0.dtb.write_accesses 189050 # DTB write accesses
-system.cpu0.dtb.write_acv 99 # DTB write access violations
-system.cpu0.dtb.write_hits 5934560 # DTB write hits
-system.cpu0.dtb.write_misses 726 # DTB write misses
-system.cpu0.icache.ReadReq_accesses 57189605 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_hits 56304737 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_rate 0.015473 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 884868 # number of ReadReq misses
-system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 63.636703 # Average number of references to valid blocks.
-system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 57189605 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu0.icache.demand_hits 56304737 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.015473 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 884868 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses 57189605 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 56304737 # number of overall hits
-system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.015473 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 884868 # number of overall misses
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.icache.replacements 884272 # number of replacements
-system.cpu0.icache.sampled_refs 884784 # Sample count of references to valid blocks.
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use
-system.cpu0.icache.total_refs 56304737 # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles
-system.cpu0.itb.accesses 3858857 # ITB accesses
-system.cpu0.itb.acv 127 # ITB acv
-system.cpu0.itb.hits 3855372 # ITB hits
-system.cpu0.itb.misses 3485 # ITB misses
-system.cpu0.kern.callpal 183274 # number of callpals executed
-system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed
-system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed
-system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed
-system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed
-system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed
-system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed
-system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed
-system.cpu0.kern.callpal_swpipl 168019 91.68% 93.82% # number of callpals executed
-system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed
-system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed
-system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed
-system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed
-system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed
-system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed
-system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed
-system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.hwrei 197103 # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed
-system.cpu0.kern.ipl_count 174852 # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31 101697 58.16% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0 1853125830000 99.08% 99.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31 17106381500 0.91% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31 0.684592 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good_kernel 1157
-system.cpu0.kern.mode_good_user 1158
-system.cpu0.kern.mode_good_idle 0
-system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches
-system.cpu0.kern.mode_switch_user 1158 # number of protection mode switches
-system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches
-system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel 0.163188 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3762 # number of times the context was actually changed
-system.cpu0.kern.syscall 226 # number of syscalls executed
-system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed
-system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed
-system.cpu0.kern.syscall_4 2 0.88% 11.95% # number of syscalls executed
-system.cpu0.kern.syscall_6 32 14.16% 26.11% # number of syscalls executed
-system.cpu0.kern.syscall_12 1 0.44% 26.55% # number of syscalls executed
-system.cpu0.kern.syscall_15 1 0.44% 26.99% # number of syscalls executed
-system.cpu0.kern.syscall_17 9 3.98% 30.97% # number of syscalls executed
-system.cpu0.kern.syscall_19 8 3.54% 34.51% # number of syscalls executed
-system.cpu0.kern.syscall_20 6 2.65% 37.17% # number of syscalls executed
-system.cpu0.kern.syscall_23 2 0.88% 38.05% # number of syscalls executed
-system.cpu0.kern.syscall_24 4 1.77% 39.82% # number of syscalls executed
-system.cpu0.kern.syscall_33 7 3.10% 42.92% # number of syscalls executed
-system.cpu0.kern.syscall_41 2 0.88% 43.81% # number of syscalls executed
-system.cpu0.kern.syscall_45 37 16.37% 60.18% # number of syscalls executed
-system.cpu0.kern.syscall_47 4 1.77% 61.95% # number of syscalls executed
-system.cpu0.kern.syscall_48 8 3.54% 65.49% # number of syscalls executed
-system.cpu0.kern.syscall_54 10 4.42% 69.91% # number of syscalls executed
-system.cpu0.kern.syscall_58 1 0.44% 70.35% # number of syscalls executed
-system.cpu0.kern.syscall_59 4 1.77% 72.12% # number of syscalls executed
-system.cpu0.kern.syscall_71 30 13.27% 85.40% # number of syscalls executed
-system.cpu0.kern.syscall_73 3 1.33% 86.73% # number of syscalls executed
-system.cpu0.kern.syscall_74 8 3.54% 90.27% # number of syscalls executed
-system.cpu0.kern.syscall_87 1 0.44% 90.71% # number of syscalls executed
-system.cpu0.kern.syscall_90 2 0.88% 91.59% # number of syscalls executed
-system.cpu0.kern.syscall_92 9 3.98% 95.58% # number of syscalls executed
-system.cpu0.kern.syscall_97 2 0.88% 96.46% # number of syscalls executed
-system.cpu0.kern.syscall_98 2 0.88% 97.35% # number of syscalls executed
-system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed
-system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed
-system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed
-system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles
-system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
-system.cpu0.num_insts 57181549 # Number of instructions executed
-system.cpu0.num_refs 15322361 # Number of memory references
-system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses
-system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses
-system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses
-system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses
-system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks.
-system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 1812118 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 72152 # number of overall misses
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.dcache.replacements 62338 # number of replacements
-system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks.
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 391.950049 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 30848 # number of writebacks
-system.cpu1.dtb.accesses 323622 # DTB accesses
-system.cpu1.dtb.acv 116 # DTB access violations
-system.cpu1.dtb.hits 1914885 # DTB hits
-system.cpu1.dtb.misses 3692 # DTB misses
-system.cpu1.dtb.read_accesses 220342 # DTB read accesses
-system.cpu1.dtb.read_acv 58 # DTB read access violations
-system.cpu1.dtb.read_hits 1163439 # DTB read hits
-system.cpu1.dtb.read_misses 3277 # DTB read misses
-system.cpu1.dtb.write_accesses 103280 # DTB write accesses
-system.cpu1.dtb.write_acv 58 # DTB write access violations
-system.cpu1.dtb.write_hits 751446 # DTB write hits
-system.cpu1.dtb.write_misses 415 # DTB write misses
-system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses
-system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks.
-system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits 5832136 # number of overall hits
-system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses
-system.cpu1.icache.overall_misses 103630 # number of overall misses
-system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.icache.replacements 103091 # number of replacements
-system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks.
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use
-system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
-system.cpu1.itb.accesses 1469938 # ITB accesses
-system.cpu1.itb.acv 57 # ITB acv
-system.cpu1.itb.hits 1468399 # ITB hits
-system.cpu1.itb.misses 1539 # ITB misses
-system.cpu1.kern.callpal 32131 # number of callpals executed
-system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed
-system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed
-system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed
-system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed
-system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed
-system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed
-system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed
-system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed
-system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed
-system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed
-system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed
-system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed
-system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed
-system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
-system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed
-system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks 1870124427000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good_kernel 612
-system.cpu1.kern.mode_good_user 580
-system.cpu1.kern.mode_good_idle 32
-system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches
-system.cpu1.kern.mode_switch_user 580 # number of protection mode switches
-system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches
-system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 471 # number of times the context was actually changed
-system.cpu1.kern.syscall 100 # number of syscalls executed
-system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed
-system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed
-system.cpu1.kern.syscall_4 2 2.00% 15.00% # number of syscalls executed
-system.cpu1.kern.syscall_6 10 10.00% 25.00% # number of syscalls executed
-system.cpu1.kern.syscall_17 6 6.00% 31.00% # number of syscalls executed
-system.cpu1.kern.syscall_19 2 2.00% 33.00% # number of syscalls executed
-system.cpu1.kern.syscall_23 2 2.00% 35.00% # number of syscalls executed
-system.cpu1.kern.syscall_24 2 2.00% 37.00% # number of syscalls executed
-system.cpu1.kern.syscall_33 4 4.00% 41.00% # number of syscalls executed
-system.cpu1.kern.syscall_45 17 17.00% 58.00% # number of syscalls executed
-system.cpu1.kern.syscall_47 2 2.00% 60.00% # number of syscalls executed
-system.cpu1.kern.syscall_48 2 2.00% 62.00% # number of syscalls executed
-system.cpu1.kern.syscall_59 3 3.00% 65.00% # number of syscalls executed
-system.cpu1.kern.syscall_71 24 24.00% 89.00% # number of syscalls executed
-system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed
-system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed
-system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed
-system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
-system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
-system.cpu1.num_insts 5931958 # Number of instructions executed
-system.cpu1.num_refs 1926645 # Number of memory references
-system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
-system.disk0.dma_write_txs 395 # Number of DMA write transactions.
-system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses 175 # number of ReadReq misses
-system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses 41552 # number of WriteReq misses
-system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses 41727 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency 0 # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.iocache.demand_hits 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate 1 # miss rate for demand accesses
-system.iocache.demand_misses 41727 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.overall_accesses 41727 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency 0 # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.iocache.overall_hits 0 # number of overall hits
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.overall_miss_rate 1 # miss rate for overall accesses
-system.iocache.overall_misses 41727 # number of overall misses
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.iocache.replacements 41695 # number of replacements
-system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0.435437 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 41520 # number of writebacks
-system.l2c.ReadExReq_accesses 306244 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 306244 # number of ReadExReq misses
-system.l2c.ReadReq_accesses 2724143 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits 1759609 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate 0.354069 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 964534 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses
-system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 427641 # number of Writeback hits
-system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 1.789118 # Average number of references to valid blocks.
-system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 3030387 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 0 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.l2c.demand_hits 1759609 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses
-system.l2c.demand_misses 1270778 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 3030387 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 0 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.l2c.overall_hits 1759609 # number of overall hits
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses
-system.l2c.overall_misses 1270778 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 1056800 # number of replacements
-system.l2c.sampled_refs 1091449 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30522.432687 # Cycle average of tags in use
-system.l2c.total_refs 1952731 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 123878 # number of writebacks
-system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
-system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
-system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: kernel located at: /dist/m5/system/binaries/vmlinux
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: 97861500: Trying to launch CPU number 1!
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:37:23
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 1870335522500 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 3333474 # Simulator instruction rate (inst/s)
+host_mem_usage 290708 # Number of bytes of host memory used
+host_seconds 18.93 # Real time elapsed on the host
+host_tick_rate 98784311223 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 63113507 # Number of instructions simulated
+sim_seconds 1.870336 # Number of seconds simulated
+sim_ticks 1870335522500 # Number of ticks simulated
+system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses
+system.cpu0.dcache.ReadReq_accesses 8975619 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_hits 7292050 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses 1683569 # number of ReadReq misses
+system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses
+system.cpu0.dcache.WriteReq_accesses 5746054 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_hits 5372248 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses
+system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu0.dcache.avg_refs 6.625587 # Average number of references to valid blocks.
+system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.demand_accesses 14721673 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu0.dcache.demand_hits 12664298 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 2057375 # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.overall_accesses 14721673 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_hits 12664298 # number of overall hits
+system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 2057375 # number of overall misses
+system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.dcache.replacements 1978967 # number of replacements
+system.cpu0.dcache.sampled_refs 1979479 # Sample count of references to valid blocks.
+system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.tagsinuse 504.827685 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 13115211 # Total number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.writebacks 396793 # number of writebacks
+system.cpu0.dtb.accesses 698037 # DTB accesses
+system.cpu0.dtb.acv 251 # DTB access violations
+system.cpu0.dtb.hits 15082911 # DTB hits
+system.cpu0.dtb.misses 7805 # DTB misses
+system.cpu0.dtb.read_accesses 508987 # DTB read accesses
+system.cpu0.dtb.read_acv 152 # DTB read access violations
+system.cpu0.dtb.read_hits 9148351 # DTB read hits
+system.cpu0.dtb.read_misses 7079 # DTB read misses
+system.cpu0.dtb.write_accesses 189050 # DTB write accesses
+system.cpu0.dtb.write_acv 99 # DTB write access violations
+system.cpu0.dtb.write_hits 5934560 # DTB write hits
+system.cpu0.dtb.write_misses 726 # DTB write misses
+system.cpu0.icache.ReadReq_accesses 57189605 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_hits 56304737 # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_rate 0.015473 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses 884868 # number of ReadReq misses
+system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu0.icache.avg_refs 63.636703 # Average number of references to valid blocks.
+system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.demand_accesses 57189605 # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu0.icache.demand_hits 56304737 # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate 0.015473 # miss rate for demand accesses
+system.cpu0.icache.demand_misses 884868 # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.icache.overall_accesses 57189605 # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu0.icache.overall_hits 56304737 # number of overall hits
+system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate 0.015473 # miss rate for overall accesses
+system.cpu0.icache.overall_misses 884868 # number of overall misses
+system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.icache.replacements 884272 # number of replacements
+system.cpu0.icache.sampled_refs 884784 # Sample count of references to valid blocks.
+system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use
+system.cpu0.icache.total_refs 56304737 # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.writebacks 0 # number of writebacks
+system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles
+system.cpu0.itb.accesses 3858857 # ITB accesses
+system.cpu0.itb.acv 127 # ITB acv
+system.cpu0.itb.hits 3855372 # ITB hits
+system.cpu0.itb.misses 3485 # ITB misses
+system.cpu0.kern.callpal 183274 # number of callpals executed
+system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed
+system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed
+system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed
+system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed
+system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed
+system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed
+system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed
+system.cpu0.kern.callpal_swpipl 168019 91.68% 93.82% # number of callpals executed
+system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed
+system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed
+system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed
+system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed
+system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed
+system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed
+system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed
+system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.hwrei 197103 # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed
+system.cpu0.kern.ipl_count 174852 # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31 101697 58.16% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0 1853125830000 99.08% 99.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31 17106381500 0.91% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_31 0.684592 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel 1157
+system.cpu0.kern.mode_good_user 1158
+system.cpu0.kern.mode_good_idle 0
+system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches
+system.cpu0.kern.mode_switch_user 1158 # number of protection mode switches
+system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches
+system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel 0.163188 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context 3762 # number of times the context was actually changed
+system.cpu0.kern.syscall 226 # number of syscalls executed
+system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed
+system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed
+system.cpu0.kern.syscall_4 2 0.88% 11.95% # number of syscalls executed
+system.cpu0.kern.syscall_6 32 14.16% 26.11% # number of syscalls executed
+system.cpu0.kern.syscall_12 1 0.44% 26.55% # number of syscalls executed
+system.cpu0.kern.syscall_15 1 0.44% 26.99% # number of syscalls executed
+system.cpu0.kern.syscall_17 9 3.98% 30.97% # number of syscalls executed
+system.cpu0.kern.syscall_19 8 3.54% 34.51% # number of syscalls executed
+system.cpu0.kern.syscall_20 6 2.65% 37.17% # number of syscalls executed
+system.cpu0.kern.syscall_23 2 0.88% 38.05% # number of syscalls executed
+system.cpu0.kern.syscall_24 4 1.77% 39.82% # number of syscalls executed
+system.cpu0.kern.syscall_33 7 3.10% 42.92% # number of syscalls executed
+system.cpu0.kern.syscall_41 2 0.88% 43.81% # number of syscalls executed
+system.cpu0.kern.syscall_45 37 16.37% 60.18% # number of syscalls executed
+system.cpu0.kern.syscall_47 4 1.77% 61.95% # number of syscalls executed
+system.cpu0.kern.syscall_48 8 3.54% 65.49% # number of syscalls executed
+system.cpu0.kern.syscall_54 10 4.42% 69.91% # number of syscalls executed
+system.cpu0.kern.syscall_58 1 0.44% 70.35% # number of syscalls executed
+system.cpu0.kern.syscall_59 4 1.77% 72.12% # number of syscalls executed
+system.cpu0.kern.syscall_71 30 13.27% 85.40% # number of syscalls executed
+system.cpu0.kern.syscall_73 3 1.33% 86.73% # number of syscalls executed
+system.cpu0.kern.syscall_74 8 3.54% 90.27% # number of syscalls executed
+system.cpu0.kern.syscall_87 1 0.44% 90.71% # number of syscalls executed
+system.cpu0.kern.syscall_90 2 0.88% 91.59% # number of syscalls executed
+system.cpu0.kern.syscall_92 9 3.98% 95.58% # number of syscalls executed
+system.cpu0.kern.syscall_97 2 0.88% 96.46% # number of syscalls executed
+system.cpu0.kern.syscall_98 2 0.88% 97.35% # number of syscalls executed
+system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed
+system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed
+system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed
+system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles
+system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
+system.cpu0.num_insts 57181549 # Number of instructions executed
+system.cpu0.num_refs 15322361 # Number of memory references
+system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses
+system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses
+system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses
+system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses
+system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks.
+system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses
+system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_hits 1812118 # number of overall hits
+system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses
+system.cpu1.dcache.overall_misses 72152 # number of overall misses
+system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.dcache.replacements 62338 # number of replacements
+system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks.
+system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.tagsinuse 391.950049 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks 30848 # number of writebacks
+system.cpu1.dtb.accesses 323622 # DTB accesses
+system.cpu1.dtb.acv 116 # DTB access violations
+system.cpu1.dtb.hits 1914885 # DTB hits
+system.cpu1.dtb.misses 3692 # DTB misses
+system.cpu1.dtb.read_accesses 220342 # DTB read accesses
+system.cpu1.dtb.read_acv 58 # DTB read access violations
+system.cpu1.dtb.read_hits 1163439 # DTB read hits
+system.cpu1.dtb.read_misses 3277 # DTB read misses
+system.cpu1.dtb.write_accesses 103280 # DTB write accesses
+system.cpu1.dtb.write_acv 58 # DTB write access violations
+system.cpu1.dtb.write_hits 751446 # DTB write hits
+system.cpu1.dtb.write_misses 415 # DTB write misses
+system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses
+system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks.
+system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses
+system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu1.icache.overall_hits 5832136 # number of overall hits
+system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses
+system.cpu1.icache.overall_misses 103630 # number of overall misses
+system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.icache.replacements 103091 # number of replacements
+system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks.
+system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use
+system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.writebacks 0 # number of writebacks
+system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
+system.cpu1.itb.accesses 1469938 # ITB accesses
+system.cpu1.itb.acv 57 # ITB acv
+system.cpu1.itb.hits 1468399 # ITB hits
+system.cpu1.itb.misses 1539 # ITB misses
+system.cpu1.kern.callpal 32131 # number of callpals executed
+system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed
+system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed
+system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed
+system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed
+system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed
+system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed
+system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed
+system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed
+system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed
+system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed
+system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed
+system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed
+system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed
+system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed
+system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed
+system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
+system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed
+system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks 1870124427000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel 612
+system.cpu1.kern.mode_good_user 580
+system.cpu1.kern.mode_good_idle 32
+system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches
+system.cpu1.kern.mode_switch_user 580 # number of protection mode switches
+system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches
+system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 471 # number of times the context was actually changed
+system.cpu1.kern.syscall 100 # number of syscalls executed
+system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed
+system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed
+system.cpu1.kern.syscall_4 2 2.00% 15.00% # number of syscalls executed
+system.cpu1.kern.syscall_6 10 10.00% 25.00% # number of syscalls executed
+system.cpu1.kern.syscall_17 6 6.00% 31.00% # number of syscalls executed
+system.cpu1.kern.syscall_19 2 2.00% 33.00% # number of syscalls executed
+system.cpu1.kern.syscall_23 2 2.00% 35.00% # number of syscalls executed
+system.cpu1.kern.syscall_24 2 2.00% 37.00% # number of syscalls executed
+system.cpu1.kern.syscall_33 4 4.00% 41.00% # number of syscalls executed
+system.cpu1.kern.syscall_45 17 17.00% 58.00% # number of syscalls executed
+system.cpu1.kern.syscall_47 2 2.00% 60.00% # number of syscalls executed
+system.cpu1.kern.syscall_48 2 2.00% 62.00% # number of syscalls executed
+system.cpu1.kern.syscall_59 3 3.00% 65.00% # number of syscalls executed
+system.cpu1.kern.syscall_71 24 24.00% 89.00% # number of syscalls executed
+system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed
+system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed
+system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed
+system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
+system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
+system.cpu1.num_insts 5931958 # Number of instructions executed
+system.cpu1.num_refs 1926645 # Number of memory references
+system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
+system.disk0.dma_write_txs 395 # Number of DMA write transactions.
+system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses 175 # number of ReadReq misses
+system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses 41552 # number of WriteReq misses
+system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.iocache.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_no_targets 0 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.demand_accesses 41727 # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency 0 # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.iocache.demand_hits 0 # number of demand (read+write) hits
+system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate 1 # miss rate for demand accesses
+system.iocache.demand_misses 41727 # number of demand (read+write) misses
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.overall_accesses 41727 # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency 0 # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.iocache.overall_hits 0 # number of overall hits
+system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.overall_miss_rate 1 # miss rate for overall accesses
+system.iocache.overall_misses 41727 # number of overall misses
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements 41695 # number of replacements
+system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse 0.435437 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
+system.iocache.writebacks 41520 # number of writebacks
+system.l2c.ReadExReq_accesses 306244 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 306244 # number of ReadExReq misses
+system.l2c.ReadReq_accesses 2724143 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits 1759609 # number of ReadReq hits
+system.l2c.ReadReq_miss_rate 0.354069 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 964534 # number of ReadReq misses
+system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses
+system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 427641 # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_refs 1.789118 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.demand_accesses 3030387 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 0 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.l2c.demand_hits 1759609 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses
+system.l2c.demand_misses 1270778 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.overall_accesses 3030387 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 0 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.l2c.overall_hits 1759609 # number of overall hits
+system.l2c.overall_miss_latency 0 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses
+system.l2c.overall_misses 1270778 # number of overall misses
+system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements 1056800 # number of replacements
+system.l2c.sampled_refs 1091449 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 30522.432687 # Cycle average of tags in use
+system.l2c.total_refs 1952731 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 123878 # number of writebacks
+system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: 97861500: Trying to launch CPU number 1!
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:30:58
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:37:23
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1870335522500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 2786128 # Simulator instruction rate (inst/s)
-host_mem_usage 289464 # Number of bytes of host memory used
-host_seconds 21.53 # Real time elapsed on the host
-host_tick_rate 84905818409 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 59995351 # Number of instructions simulated
-sim_seconds 1.828356 # Number of seconds simulated
-sim_ticks 1828355695500 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 183118 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate 0.085685 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses 17161 # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses 9523053 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits 7801372 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate 0.180791 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1721681 # number of ReadReq misses
-system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 169391 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_rate 0.149891 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses
-system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits 5750766 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate 0.064945 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 399423 # number of WriteReq misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 6.866519 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 15673242 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_hits 13552138 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.135333 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2121104 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 15673242 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 13552138 # number of overall hits
-system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.135333 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2121104 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 2042676 # number of replacements
-system.cpu.dcache.sampled_refs 2043188 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.997800 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14029590 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 428892 # number of writebacks
-system.cpu.dtb.accesses 1020787 # DTB accesses
-system.cpu.dtb.acv 367 # DTB access violations
-system.cpu.dtb.hits 16053817 # DTB hits
-system.cpu.dtb.misses 11471 # DTB misses
-system.cpu.dtb.read_accesses 728856 # DTB read accesses
-system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_hits 9703849 # DTB read hits
-system.cpu.dtb.read_misses 10329 # DTB read misses
-system.cpu.dtb.write_accesses 291931 # DTB write accesses
-system.cpu.dtb.write_acv 157 # DTB write access violations
-system.cpu.dtb.write_hits 6349968 # DTB write hits
-system.cpu.dtb.write_misses 1142 # DTB write misses
-system.cpu.icache.ReadReq_accesses 60007189 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits 59087131 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 920058 # number of ReadReq misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 64.229122 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 60007189 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_hits 59087131 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses
-system.cpu.icache.demand_misses 920058 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 60007189 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 59087131 # number of overall hits
-system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses
-system.cpu.icache.overall_misses 920058 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 919431 # number of replacements
-system.cpu.icache.sampled_refs 919943 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 511.214823 # Cycle average of tags in use
-system.cpu.icache.total_refs 59087131 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0.983588 # Percentage of idle cycles
-system.cpu.itb.accesses 4979228 # ITB accesses
-system.cpu.itb.acv 184 # ITB acv
-system.cpu.itb.hits 4974222 # ITB hits
-system.cpu.itb.misses 5006 # ITB misses
-system.cpu.kern.callpal 192140 # number of callpals executed
-system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed
-system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
-system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu.kern.callpal_swpipl 175211 91.19% 93.40% # number of callpals executed
-system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed
-system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed
-system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed
-system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed
-system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed
-system.cpu.kern.callpal_rti 5202 2.71% 99.64% # number of callpals executed
-system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
-system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.hwrei 211278 # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed
-system.cpu.kern.ipl_count 182522 # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31 105599 57.86% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks 1828355488000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0 1811087822500 99.06% 99.06% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31 17167360500 0.94% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31 0.695537 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel 1909
-system.cpu.kern.mode_good_user 1738
-system.cpu.kern.mode_good_idle 171
-system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches
-system.cpu.kern.mode_switch_user 1738 # number of protection mode switches
-system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches
-system.cpu.kern.mode_switch_good 1.402493 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel 0.320948 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel 26834029500 1.47% 1.47% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle 1800056383500 98.45% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4178 # number of times the context was actually changed
-system.cpu.kern.syscall 326 # number of syscalls executed
-system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
-system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
-system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed
-system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed
-system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed
-system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed
-system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed
-system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed
-system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed
-system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed
-system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed
-system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed
-system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed
-system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed
-system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed
-system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed
-system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed
-system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed
-system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed
-system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed
-system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed
-system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed
-system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed
-system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed
-system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed
-system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed
-system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed
-system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
-system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
-system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
-system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles
-system.cpu.numCycles 3656711283 # number of cpu cycles simulated
-system.cpu.num_insts 59995351 # Number of instructions executed
-system.cpu.num_refs 16302128 # Number of memory references
-system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
-system.disk0.dma_write_txs 395 # Number of DMA write transactions.
-system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses 174 # number of ReadReq misses
-system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses 41552 # number of WriteReq misses
-system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses 41726 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency 0 # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.iocache.demand_hits 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate 1 # miss rate for demand accesses
-system.iocache.demand_misses 41726 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.overall_accesses 41726 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency 0 # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.iocache.overall_hits 0 # number of overall hits
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.overall_miss_rate 1 # miss rate for overall accesses
-system.iocache.overall_misses 41726 # number of overall misses
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.iocache.replacements 41686 # number of replacements
-system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 1.226225 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 41512 # number of writebacks
-system.l2c.ReadExReq_accesses 304347 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 304347 # number of ReadExReq misses
-system.l2c.ReadReq_accesses 2658883 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits 1696464 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate 0.361964 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 962419 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses 124943 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 124943 # number of UpgradeReq misses
-system.l2c.Writeback_accesses 428892 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 428892 # number of Writeback hits
-system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 1.726803 # Average number of references to valid blocks.
-system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2963230 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 0 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.l2c.demand_hits 1696464 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.427495 # miss rate for demand accesses
-system.l2c.demand_misses 1266766 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 2963230 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 0 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.l2c.overall_hits 1696464 # number of overall hits
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.427495 # miss rate for overall accesses
-system.l2c.overall_misses 1266766 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 1050731 # number of replacements
-system.l2c.sampled_refs 1081071 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30223.992851 # Cycle average of tags in use
-system.l2c.total_refs 1866797 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 119150 # number of writebacks
-system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
-system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
-system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: kernel located at: /dist/m5/system/binaries/vmlinux
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:37:01
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 1828355695500 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2786128 # Simulator instruction rate (inst/s)
+host_mem_usage 289464 # Number of bytes of host memory used
+host_seconds 21.53 # Real time elapsed on the host
+host_tick_rate 84905818409 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 59995351 # Number of instructions simulated
+sim_seconds 1.828356 # Number of seconds simulated
+sim_ticks 1828355695500 # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits 183118 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_rate 0.085685 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses 17161 # number of LoadLockedReq misses
+system.cpu.dcache.ReadReq_accesses 9523053 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits 7801372 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate 0.180791 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1721681 # number of ReadReq misses
+system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits 169391 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_rate 0.149891 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses
+system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_hits 5750766 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate 0.064945 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 399423 # number of WriteReq misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 6.866519 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 15673242 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu.dcache.demand_hits 13552138 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.135333 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2121104 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 15673242 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 13552138 # number of overall hits
+system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.135333 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2121104 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 2042676 # number of replacements
+system.cpu.dcache.sampled_refs 2043188 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 511.997800 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14029590 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 428892 # number of writebacks
+system.cpu.dtb.accesses 1020787 # DTB accesses
+system.cpu.dtb.acv 367 # DTB access violations
+system.cpu.dtb.hits 16053817 # DTB hits
+system.cpu.dtb.misses 11471 # DTB misses
+system.cpu.dtb.read_accesses 728856 # DTB read accesses
+system.cpu.dtb.read_acv 210 # DTB read access violations
+system.cpu.dtb.read_hits 9703849 # DTB read hits
+system.cpu.dtb.read_misses 10329 # DTB read misses
+system.cpu.dtb.write_accesses 291931 # DTB write accesses
+system.cpu.dtb.write_acv 157 # DTB write access violations
+system.cpu.dtb.write_hits 6349968 # DTB write hits
+system.cpu.dtb.write_misses 1142 # DTB write misses
+system.cpu.icache.ReadReq_accesses 60007189 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_hits 59087131 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 920058 # number of ReadReq misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 64.229122 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 60007189 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu.icache.demand_hits 59087131 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses
+system.cpu.icache.demand_misses 920058 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 60007189 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 59087131 # number of overall hits
+system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses
+system.cpu.icache.overall_misses 920058 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 919431 # number of replacements
+system.cpu.icache.sampled_refs 919943 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 511.214823 # Cycle average of tags in use
+system.cpu.icache.total_refs 59087131 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0.983588 # Percentage of idle cycles
+system.cpu.itb.accesses 4979228 # ITB accesses
+system.cpu.itb.acv 184 # ITB acv
+system.cpu.itb.hits 4974222 # ITB hits
+system.cpu.itb.misses 5006 # ITB misses
+system.cpu.kern.callpal 192140 # number of callpals executed
+system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed
+system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
+system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed
+system.cpu.kern.callpal_swpipl 175211 91.19% 93.40% # number of callpals executed
+system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed
+system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed
+system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed
+system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed
+system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed
+system.cpu.kern.callpal_rti 5202 2.71% 99.64% # number of callpals executed
+system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
+system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.hwrei 211278 # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed
+system.cpu.kern.ipl_count 182522 # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31 105599 57.86% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks 1828355488000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0 1811087822500 99.06% 99.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31 17167360500 0.94% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_31 0.695537 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel 1909
+system.cpu.kern.mode_good_user 1738
+system.cpu.kern.mode_good_idle 171
+system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches
+system.cpu.kern.mode_switch_user 1738 # number of protection mode switches
+system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches
+system.cpu.kern.mode_switch_good 1.402493 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel 0.320948 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel 26834029500 1.47% 1.47% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle 1800056383500 98.45% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4178 # number of times the context was actually changed
+system.cpu.kern.syscall 326 # number of syscalls executed
+system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
+system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
+system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed
+system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed
+system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed
+system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed
+system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed
+system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed
+system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed
+system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed
+system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed
+system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed
+system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed
+system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed
+system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed
+system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed
+system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed
+system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed
+system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed
+system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed
+system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed
+system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed
+system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed
+system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed
+system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed
+system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed
+system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed
+system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
+system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
+system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
+system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles
+system.cpu.numCycles 3656711283 # number of cpu cycles simulated
+system.cpu.num_insts 59995351 # Number of instructions executed
+system.cpu.num_refs 16302128 # Number of memory references
+system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
+system.disk0.dma_write_txs 395 # Number of DMA write transactions.
+system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses 174 # number of ReadReq misses
+system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses 41552 # number of WriteReq misses
+system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.iocache.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_no_targets 0 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.demand_accesses 41726 # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency 0 # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.iocache.demand_hits 0 # number of demand (read+write) hits
+system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate 1 # miss rate for demand accesses
+system.iocache.demand_misses 41726 # number of demand (read+write) misses
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.overall_accesses 41726 # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency 0 # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.iocache.overall_hits 0 # number of overall hits
+system.iocache.overall_miss_latency 0 # number of overall miss cycles
+system.iocache.overall_miss_rate 1 # miss rate for overall accesses
+system.iocache.overall_misses 41726 # number of overall misses
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements 41686 # number of replacements
+system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse 1.226225 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit.
+system.iocache.writebacks 41512 # number of writebacks
+system.l2c.ReadExReq_accesses 304347 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 304347 # number of ReadExReq misses
+system.l2c.ReadReq_accesses 2658883 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits 1696464 # number of ReadReq hits
+system.l2c.ReadReq_miss_rate 0.361964 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 962419 # number of ReadReq misses
+system.l2c.UpgradeReq_accesses 124943 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 124943 # number of UpgradeReq misses
+system.l2c.Writeback_accesses 428892 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 428892 # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_refs 1.726803 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.demand_accesses 2963230 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 0 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.l2c.demand_hits 1696464 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.427495 # miss rate for demand accesses
+system.l2c.demand_misses 1266766 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.overall_accesses 2963230 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 0 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.l2c.overall_hits 1696464 # number of overall hits
+system.l2c.overall_miss_latency 0 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.427495 # miss rate for overall accesses
+system.l2c.overall_misses 1266766 # number of overall misses
+system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements 1050731 # number of replacements
+system.l2c.sampled_refs 1081071 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 30223.992851 # Cycle average of tags in use
+system.l2c.total_refs 1866797 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 119150 # number of writebacks
+system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:30:58
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:37:01
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1828355695500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1388930 # Simulator instruction rate (inst/s)
-host_mem_usage 287800 # Number of bytes of host memory used
-host_seconds 42.75 # Real time elapsed on the host
-host_tick_rate 46129218174 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 59379829 # Number of instructions simulated
-sim_seconds 1.972135 # Number of seconds simulated
-sim_ticks 1972135479000 # Number of ticks simulated
-system.cpu0.dcache.LoadLockedReq_accesses 192618 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14266.203842 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11266.203842 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits 175909 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency 238374000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate 0.086747 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses 16709 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086747 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 16709 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses 8482392 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 25694.187455 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.147984 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits 7443656 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 26689477500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate 0.122458 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 1038736 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 23573228500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122458 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 1038736 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 868701000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses 191654 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency 55352.322833 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52352.322833 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits 163305 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency 1569183000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate 0.147918 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses 28349 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1484136000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147918 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses 28349 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses 5845269 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 55891.595936 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.595936 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits 5466012 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 21197279000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.064883 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 379257 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency 20059508000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064883 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 379257 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1225890000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 9.984583 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 14327661 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 33770.798939 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 12909668 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 47886756500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.098969 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 1417993 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 43632736500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.098969 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 1417993 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 14327661 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 33770.798939 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 12909668 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 47886756500 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.098969 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 1417993 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 43632736500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.098969 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 1417993 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 2094591000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.dcache.replacements 1338626 # number of replacements
-system.cpu0.dcache.sampled_refs 1339138 # Sample count of references to valid blocks.
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 503.746259 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 13370734 # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 403562 # number of writebacks
-system.cpu0.dtb.accesses 719860 # DTB accesses
-system.cpu0.dtb.acv 289 # DTB access violations
-system.cpu0.dtb.hits 14696400 # DTB hits
-system.cpu0.dtb.misses 8485 # DTB misses
-system.cpu0.dtb.read_accesses 524201 # DTB read accesses
-system.cpu0.dtb.read_acv 174 # DTB read access violations
-system.cpu0.dtb.read_hits 8658591 # DTB read hits
-system.cpu0.dtb.read_misses 7687 # DTB read misses
-system.cpu0.dtb.write_accesses 195659 # DTB write accesses
-system.cpu0.dtb.write_acv 115 # DTB write access violations
-system.cpu0.dtb.write_hits 6037809 # DTB write hits
-system.cpu0.dtb.write_misses 798 # DTB write misses
-system.cpu0.icache.ReadReq_accesses 54124252 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 14681.475669 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.724759 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits 53208030 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 13451491000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate 0.016928 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 916222 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 10702137000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.016928 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses 916222 # number of ReadReq MSHR misses
-system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 58.081472 # Average number of references to valid blocks.
-system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 54124252 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 14681.475669 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency
-system.cpu0.icache.demand_hits 53208030 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 13451491000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.016928 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 916222 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 10702137000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0.016928 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 916222 # number of demand (read+write) MSHR misses
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses 54124252 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 14681.475669 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 53208030 # number of overall hits
-system.cpu0.icache.overall_miss_latency 13451491000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.016928 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 916222 # number of overall misses
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 10702137000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0.016928 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 916222 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.icache.replacements 915582 # number of replacements
-system.cpu0.icache.sampled_refs 916093 # Sample count of references to valid blocks.
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 508.642784 # Cycle average of tags in use
-system.cpu0.icache.total_refs 53208030 # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idle_fraction 0.933199 # Percentage of idle cycles
-system.cpu0.itb.accesses 3953623 # ITB accesses
-system.cpu0.itb.acv 143 # ITB acv
-system.cpu0.itb.hits 3949782 # ITB hits
-system.cpu0.itb.misses 3841 # ITB misses
-system.cpu0.kern.callpal 187998 # number of callpals executed
-system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed
-system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal_swpctx 3868 2.06% 2.11% # number of callpals executed
-system.cpu0.kern.callpal_tbi 44 0.02% 2.13% # number of callpals executed
-system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed
-system.cpu0.kern.callpal_swpipl 172054 91.52% 93.65% # number of callpals executed
-system.cpu0.kern.callpal_rdps 6698 3.56% 97.22% # number of callpals executed
-system.cpu0.kern.callpal_wrkgp 1 0.00% 97.22% # number of callpals executed
-system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed
-system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed
-system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed
-system.cpu0.kern.callpal_rti 4713 2.51% 99.73% # number of callpals executed
-system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed
-system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.hwrei 202882 # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce 6254 # number of quiesce instructions executed
-system.cpu0.kern.ipl_count 178892 # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0 72633 40.60% 40.60% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_21 131 0.07% 40.67% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_22 1987 1.11% 41.79% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_30 6 0.00% 41.79% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31 104135 58.21% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_good 144646 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_0 71264 49.27% 49.27% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_31 71258 49.26% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks 1972134721000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0 1908424308500 96.77% 96.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_21 96335500 0.00% 96.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22 576469500 0.03% 96.80% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.80% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31 63032165000 3.20% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used_0 0.981152 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31 0.684285 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good_kernel 1232
-system.cpu0.kern.mode_good_user 1233
-system.cpu0.kern.mode_good_idle 0
-system.cpu0.kern.mode_switch_kernel 7237 # number of protection mode switches
-system.cpu0.kern.mode_switch_user 1233 # number of protection mode switches
-system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches
-system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel 0.170236 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks_kernel 1968330428000 99.81% 99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_user 3804291000 0.19% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3869 # number of times the context was actually changed
-system.cpu0.kern.syscall 224 # number of syscalls executed
-system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed
-system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed
-system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed
-system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed
-system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed
-system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed
-system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed
-system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed
-system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed
-system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed
-system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed
-system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed
-system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed
-system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed
-system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed
-system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed
-system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed
-system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed
-system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed
-system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed
-system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed
-system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed
-system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed
-system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed
-system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed
-system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed
-system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed
-system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed
-system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed
-system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed
-system.cpu0.not_idle_fraction 0.066801 # Percentage of non-idle cycles
-system.cpu0.numCycles 3944270958 # number of cpu cycles simulated
-system.cpu0.num_insts 54115477 # Number of instructions executed
-system.cpu0.num_refs 14937789 # Number of memory references
-system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13393.700787 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10393.700787 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits 11318 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency 13608000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate 0.082374 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses 1016 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10560000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.082374 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses 1016 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses 1020508 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 15788.930188 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12788.832374 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits 984726 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 564959500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate 0.035063 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 35782 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 457610000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035063 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses 35782 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses 12269 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency 46915.603129 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43915.603129 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits 9840 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency 113958000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate 0.197979 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses 2429 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106671000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197979 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses 2429 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses 649988 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 54642.103265 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51642.103265 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits 623648 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 1439273000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate 0.040524 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 26340 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_miss_latency 1360253000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040524 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses 26340 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303022000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 30.126995 # Average number of references to valid blocks.
-system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 1670496 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 32262.845691 # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 1608374 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 2004232500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.037188 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 62122 # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 1817863000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate 0.037188 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 62122 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.overall_accesses 1670496 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 32262.845691 # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 1608374 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 2004232500 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.037188 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 62122 # number of overall misses
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 1817863000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate 0.037188 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses 62122 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency 315548000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.dcache.replacements 53749 # number of replacements
-system.cpu1.dcache.sampled_refs 54144 # Sample count of references to valid blocks.
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 388.873056 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 1631196 # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 1954644714000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 26833 # number of writebacks
-system.cpu1.dtb.accesses 302878 # DTB accesses
-system.cpu1.dtb.acv 84 # DTB access violations
-system.cpu1.dtb.hits 1693796 # DTB hits
-system.cpu1.dtb.misses 3106 # DTB misses
-system.cpu1.dtb.read_accesses 205838 # DTB read accesses
-system.cpu1.dtb.read_acv 36 # DTB read access violations
-system.cpu1.dtb.read_hits 1029675 # DTB read hits
-system.cpu1.dtb.read_misses 2750 # DTB read misses
-system.cpu1.dtb.write_accesses 97040 # DTB write accesses
-system.cpu1.dtb.write_acv 48 # DTB write access violations
-system.cpu1.dtb.write_hits 664121 # DTB write hits
-system.cpu1.dtb.write_misses 356 # DTB write misses
-system.cpu1.icache.ReadReq_accesses 5267542 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency 14619.415532 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11618.958024 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits 5180112 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency 1278175500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate 0.016598 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses 87430 # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_miss_latency 1015845500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate 0.016598 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses 87430 # number of ReadReq MSHR misses
-system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 59.267660 # Average number of references to valid blocks.
-system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses 5267542 # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 14619.415532 # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency
-system.cpu1.icache.demand_hits 5180112 # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency 1278175500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate 0.016598 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 87430 # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 1015845500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate 0.016598 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses 87430 # number of demand (read+write) MSHR misses
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.overall_accesses 5267542 # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 14619.415532 # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits 5180112 # number of overall hits
-system.cpu1.icache.overall_miss_latency 1278175500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate 0.016598 # miss rate for overall accesses
-system.cpu1.icache.overall_misses 87430 # number of overall misses
-system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency 1015845500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate 0.016598 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses 87430 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.icache.replacements 86890 # number of replacements
-system.cpu1.icache.sampled_refs 87402 # Sample count of references to valid blocks.
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 419.405623 # Cycle average of tags in use
-system.cpu1.icache.total_refs 5180112 # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1967879772000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles
-system.cpu1.itb.accesses 1397499 # ITB accesses
-system.cpu1.itb.acv 41 # ITB acv
-system.cpu1.itb.hits 1396253 # ITB hits
-system.cpu1.itb.misses 1246 # ITB misses
-system.cpu1.kern.callpal 29501 # number of callpals executed
-system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed
-system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal_swpctx 365 1.24% 1.27% # number of callpals executed
-system.cpu1.kern.callpal_tbi 10 0.03% 1.30% # number of callpals executed
-system.cpu1.kern.callpal_wrent 7 0.02% 1.33% # number of callpals executed
-system.cpu1.kern.callpal_swpipl 24142 81.83% 83.16% # number of callpals executed
-system.cpu1.kern.callpal_rdps 2172 7.36% 90.52% # number of callpals executed
-system.cpu1.kern.callpal_wrkgp 1 0.00% 90.53% # number of callpals executed
-system.cpu1.kern.callpal_wrusp 3 0.01% 90.54% # number of callpals executed
-system.cpu1.kern.callpal_rdusp 2 0.01% 90.54% # number of callpals executed
-system.cpu1.kern.callpal_whami 3 0.01% 90.55% # number of callpals executed
-system.cpu1.kern.callpal_rti 2594 8.79% 99.35% # number of callpals executed
-system.cpu1.kern.callpal_callsys 161 0.55% 99.89% # number of callpals executed
-system.cpu1.kern.callpal_imb 31 0.11% 100.00% # number of callpals executed
-system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.hwrei 36051 # number of hwrei instructions executed
-system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed
-system.cpu1.kern.ipl_count 28808 # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_0 9172 31.84% 31.84% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_22 1980 6.87% 38.71% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_30 91 0.32% 39.03% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_31 17565 60.97% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_good 20308 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_0 9164 45.13% 45.13% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_31 9073 44.68% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks 1971683837000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0 1927969399500 97.78% 97.78% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_22 511268500 0.03% 97.81% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_30 58584000 0.00% 97.81% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_31 43144585000 2.19% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used_0 0.999128 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_31 0.516539 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good_kernel 532
-system.cpu1.kern.mode_good_user 516
-system.cpu1.kern.mode_good_idle 16
-system.cpu1.kern.mode_switch_kernel 880 # number of protection mode switches
-system.cpu1.kern.mode_switch_user 516 # number of protection mode switches
-system.cpu1.kern.mode_switch_idle 2081 # number of protection mode switches
-system.cpu1.kern.mode_switch_good 1.612234 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_kernel 0.604545 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_idle 0.007689 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel 4597806000 0.23% 0.23% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_user 1703603000 0.09% 0.32% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle 1964669629000 99.68% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 366 # number of times the context was actually changed
-system.cpu1.kern.syscall 102 # number of syscalls executed
-system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed
-system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed
-system.cpu1.kern.syscall_4 1 0.98% 13.73% # number of syscalls executed
-system.cpu1.kern.syscall_6 12 11.76% 25.49% # number of syscalls executed
-system.cpu1.kern.syscall_17 5 4.90% 30.39% # number of syscalls executed
-system.cpu1.kern.syscall_19 4 3.92% 34.31% # number of syscalls executed
-system.cpu1.kern.syscall_20 2 1.96% 36.27% # number of syscalls executed
-system.cpu1.kern.syscall_23 2 1.96% 38.24% # number of syscalls executed
-system.cpu1.kern.syscall_24 2 1.96% 40.20% # number of syscalls executed
-system.cpu1.kern.syscall_33 3 2.94% 43.14% # number of syscalls executed
-system.cpu1.kern.syscall_45 15 14.71% 57.84% # number of syscalls executed
-system.cpu1.kern.syscall_47 2 1.96% 59.80% # number of syscalls executed
-system.cpu1.kern.syscall_48 3 2.94% 62.75% # number of syscalls executed
-system.cpu1.kern.syscall_54 1 0.98% 63.73% # number of syscalls executed
-system.cpu1.kern.syscall_59 2 1.96% 65.69% # number of syscalls executed
-system.cpu1.kern.syscall_71 22 21.57% 87.25% # number of syscalls executed
-system.cpu1.kern.syscall_74 7 6.86% 94.12% # number of syscalls executed
-system.cpu1.kern.syscall_90 1 0.98% 95.10% # number of syscalls executed
-system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed
-system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed
-system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed
-system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles
-system.cpu1.numCycles 3943367734 # number of cpu cycles simulated
-system.cpu1.num_insts 5264352 # Number of instructions executed
-system.cpu1.num_refs 1703685 # Number of memory references
-system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
-system.disk0.dma_write_txs 395 # Number of DMA write transactions.
-system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.iocache.ReadReq_accesses 178 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency 115196.617978 # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses 178 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses
-system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency 137906.834954 # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85903.204082 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 5730304806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses 41552 # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency 3569449936 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles_no_mshrs 6168.564107 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.blocked_no_mshrs 10459 # number of cycles access was blocked
-system.iocache.blocked_no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_mshrs 64517012 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses 41730 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency 137809.964150 # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency
-system.iocache.demand_hits 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 5750809804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate 1 # miss rate for demand accesses
-system.iocache.demand_misses 41730 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 3580698934 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.overall_accesses 41730 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency 137809.964150 # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.iocache.overall_hits 0 # number of overall hits
-system.iocache.overall_miss_latency 5750809804 # number of overall miss cycles
-system.iocache.overall_miss_rate 1 # miss rate for overall accesses
-system.iocache.overall_misses 41730 # number of overall misses
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 3580698934 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.iocache.replacements 41698 # number of replacements
-system.iocache.sampled_refs 41714 # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0.582076 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 1762323729000 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 41520 # number of writebacks
-system.l2c.ReadExReq_accesses 306796 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 52002.653229 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40002.653229 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 15954206000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 306796 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 12272654000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 306796 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 2090247 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 52016.274350 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.322096 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits 1782800 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 15992247500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.147086 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 307447 # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 12302458000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.147081 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 307436 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 789200000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses 127300 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 50741.146897 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40004.988217 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 6459348000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 127300 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 5092635000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 127300 # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1381237000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 430395 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 430395 # number of Writeback hits
-system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 4.558799 # Average number of references to valid blocks.
-system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2397043 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 52009.471007 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency
-system.l2c.demand_hits 1782800 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 31946453500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.256250 # miss rate for demand accesses
-system.l2c.demand_misses 614243 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 24575112000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.256246 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 614232 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 2397043 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 52009.471007 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 1782800 # number of overall hits
-system.l2c.overall_miss_latency 31946453500 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.256250 # miss rate for overall accesses
-system.l2c.overall_misses 614243 # number of overall misses
-system.l2c.overall_mshr_hits 11 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 24575112000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.256246 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 614232 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 2170437000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 399043 # number of replacements
-system.l2c.sampled_refs 430765 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30865.823052 # Cycle average of tags in use
-system.l2c.total_refs 1963771 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 123178 # number of writebacks
-system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
-system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
-system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: kernel located at: /dist/m5/system/binaries/vmlinux
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: 591544000: Trying to launch CPU number 1!
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:38:12
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 1972135479000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1388930 # Simulator instruction rate (inst/s)
+host_mem_usage 287800 # Number of bytes of host memory used
+host_seconds 42.75 # Real time elapsed on the host
+host_tick_rate 46129218174 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 59379829 # Number of instructions simulated
+sim_seconds 1.972135 # Number of seconds simulated
+sim_ticks 1972135479000 # Number of ticks simulated
+system.cpu0.dcache.LoadLockedReq_accesses 192618 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14266.203842 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11266.203842 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits 175909 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency 238374000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate 0.086747 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses 16709 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086747 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_misses 16709 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses 8482392 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency 25694.187455 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.147984 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_hits 7443656 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 26689477500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate 0.122458 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses 1038736 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency 23573228500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122458 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_misses 1038736 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 868701000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses 191654 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency 55352.322833 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52352.322833 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits 163305 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency 1569183000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate 0.147918 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses 28349 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1484136000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147918 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_misses 28349 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses 5845269 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency 55891.595936 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.595936 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_hits 5466012 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 21197279000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate 0.064883 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 379257 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_miss_latency 20059508000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064883 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses 379257 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1225890000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu0.dcache.avg_refs 9.984583 # Average number of references to valid blocks.
+system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.demand_accesses 14327661 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 33770.798939 # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits 12909668 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 47886756500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate 0.098969 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 1417993 # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency 43632736500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate 0.098969 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses 1417993 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.overall_accesses 14327661 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 33770.798939 # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_hits 12909668 # number of overall hits
+system.cpu0.dcache.overall_miss_latency 47886756500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate 0.098969 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 1417993 # number of overall misses
+system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency 43632736500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate 0.098969 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses 1417993 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency 2094591000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.dcache.replacements 1338626 # number of replacements
+system.cpu0.dcache.sampled_refs 1339138 # Sample count of references to valid blocks.
+system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.tagsinuse 503.746259 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 13370734 # Total number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.writebacks 403562 # number of writebacks
+system.cpu0.dtb.accesses 719860 # DTB accesses
+system.cpu0.dtb.acv 289 # DTB access violations
+system.cpu0.dtb.hits 14696400 # DTB hits
+system.cpu0.dtb.misses 8485 # DTB misses
+system.cpu0.dtb.read_accesses 524201 # DTB read accesses
+system.cpu0.dtb.read_acv 174 # DTB read access violations
+system.cpu0.dtb.read_hits 8658591 # DTB read hits
+system.cpu0.dtb.read_misses 7687 # DTB read misses
+system.cpu0.dtb.write_accesses 195659 # DTB write accesses
+system.cpu0.dtb.write_acv 115 # DTB write access violations
+system.cpu0.dtb.write_hits 6037809 # DTB write hits
+system.cpu0.dtb.write_misses 798 # DTB write misses
+system.cpu0.icache.ReadReq_accesses 54124252 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency 14681.475669 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.724759 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits 53208030 # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency 13451491000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate 0.016928 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses 916222 # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_miss_latency 10702137000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate 0.016928 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_misses 916222 # number of ReadReq MSHR misses
+system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu0.icache.avg_refs 58.081472 # Average number of references to valid blocks.
+system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.demand_accesses 54124252 # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 14681.475669 # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency
+system.cpu0.icache.demand_hits 53208030 # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency 13451491000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate 0.016928 # miss rate for demand accesses
+system.cpu0.icache.demand_misses 916222 # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency 10702137000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate 0.016928 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses 916222 # number of demand (read+write) MSHR misses
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.icache.overall_accesses 54124252 # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 14681.475669 # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu0.icache.overall_hits 53208030 # number of overall hits
+system.cpu0.icache.overall_miss_latency 13451491000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate 0.016928 # miss rate for overall accesses
+system.cpu0.icache.overall_misses 916222 # number of overall misses
+system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency 10702137000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate 0.016928 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses 916222 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.icache.replacements 915582 # number of replacements
+system.cpu0.icache.sampled_refs 916093 # Sample count of references to valid blocks.
+system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.tagsinuse 508.642784 # Cycle average of tags in use
+system.cpu0.icache.total_refs 53208030 # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.writebacks 0 # number of writebacks
+system.cpu0.idle_fraction 0.933199 # Percentage of idle cycles
+system.cpu0.itb.accesses 3953623 # ITB accesses
+system.cpu0.itb.acv 143 # ITB acv
+system.cpu0.itb.hits 3949782 # ITB hits
+system.cpu0.itb.misses 3841 # ITB misses
+system.cpu0.kern.callpal 187998 # number of callpals executed
+system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed
+system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed
+system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed
+system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed
+system.cpu0.kern.callpal_swpctx 3868 2.06% 2.11% # number of callpals executed
+system.cpu0.kern.callpal_tbi 44 0.02% 2.13% # number of callpals executed
+system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed
+system.cpu0.kern.callpal_swpipl 172054 91.52% 93.65% # number of callpals executed
+system.cpu0.kern.callpal_rdps 6698 3.56% 97.22% # number of callpals executed
+system.cpu0.kern.callpal_wrkgp 1 0.00% 97.22% # number of callpals executed
+system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed
+system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed
+system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed
+system.cpu0.kern.callpal_rti 4713 2.51% 99.73% # number of callpals executed
+system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed
+system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.hwrei 202882 # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce 6254 # number of quiesce instructions executed
+system.cpu0.kern.ipl_count 178892 # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0 72633 40.60% 40.60% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21 131 0.07% 40.67% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_22 1987 1.11% 41.79% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_30 6 0.00% 41.79% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31 104135 58.21% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good 144646 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0 71264 49.27% 49.27% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31 71258 49.26% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks 1972134721000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0 1908424308500 96.77% 96.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21 96335500 0.00% 96.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22 576469500 0.03% 96.80% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.80% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31 63032165000 3.20% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used_0 0.981152 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_31 0.684285 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel 1232
+system.cpu0.kern.mode_good_user 1233
+system.cpu0.kern.mode_good_idle 0
+system.cpu0.kern.mode_switch_kernel 7237 # number of protection mode switches
+system.cpu0.kern.mode_switch_user 1233 # number of protection mode switches
+system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches
+system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel 0.170236 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks_kernel 1968330428000 99.81% 99.81% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user 3804291000 0.19% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context 3869 # number of times the context was actually changed
+system.cpu0.kern.syscall 224 # number of syscalls executed
+system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed
+system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed
+system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed
+system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed
+system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed
+system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed
+system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed
+system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed
+system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed
+system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed
+system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed
+system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed
+system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed
+system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed
+system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed
+system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed
+system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed
+system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed
+system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed
+system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed
+system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed
+system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed
+system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed
+system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed
+system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed
+system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed
+system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed
+system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed
+system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed
+system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed
+system.cpu0.not_idle_fraction 0.066801 # Percentage of non-idle cycles
+system.cpu0.numCycles 3944270958 # number of cpu cycles simulated
+system.cpu0.num_insts 54115477 # Number of instructions executed
+system.cpu0.num_refs 14937789 # Number of memory references
+system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13393.700787 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10393.700787 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits 11318 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency 13608000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate 0.082374 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses 1016 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10560000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.082374 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_misses 1016 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses 1020508 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency 15788.930188 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12788.832374 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_hits 984726 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency 564959500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate 0.035063 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses 35782 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency 457610000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035063 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_misses 35782 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.StoreCondReq_accesses 12269 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency 46915.603129 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43915.603129 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits 9840 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency 113958000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate 0.197979 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses 2429 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106671000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197979 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_misses 2429 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses 649988 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency 54642.103265 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51642.103265 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_hits 623648 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency 1439273000 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate 0.040524 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses 26340 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_miss_latency 1360253000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040524 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_misses 26340 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303022000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu1.dcache.avg_refs 30.126995 # Average number of references to valid blocks.
+system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.demand_accesses 1670496 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 32262.845691 # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency
+system.cpu1.dcache.demand_hits 1608374 # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency 2004232500 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate 0.037188 # miss rate for demand accesses
+system.cpu1.dcache.demand_misses 62122 # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency 1817863000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate 0.037188 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses 62122 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.overall_accesses 1670496 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 32262.845691 # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_hits 1608374 # number of overall hits
+system.cpu1.dcache.overall_miss_latency 2004232500 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate 0.037188 # miss rate for overall accesses
+system.cpu1.dcache.overall_misses 62122 # number of overall misses
+system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency 1817863000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate 0.037188 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses 62122 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency 315548000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.dcache.replacements 53749 # number of replacements
+system.cpu1.dcache.sampled_refs 54144 # Sample count of references to valid blocks.
+system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.tagsinuse 388.873056 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 1631196 # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 1954644714000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks 26833 # number of writebacks
+system.cpu1.dtb.accesses 302878 # DTB accesses
+system.cpu1.dtb.acv 84 # DTB access violations
+system.cpu1.dtb.hits 1693796 # DTB hits
+system.cpu1.dtb.misses 3106 # DTB misses
+system.cpu1.dtb.read_accesses 205838 # DTB read accesses
+system.cpu1.dtb.read_acv 36 # DTB read access violations
+system.cpu1.dtb.read_hits 1029675 # DTB read hits
+system.cpu1.dtb.read_misses 2750 # DTB read misses
+system.cpu1.dtb.write_accesses 97040 # DTB write accesses
+system.cpu1.dtb.write_acv 48 # DTB write access violations
+system.cpu1.dtb.write_hits 664121 # DTB write hits
+system.cpu1.dtb.write_misses 356 # DTB write misses
+system.cpu1.icache.ReadReq_accesses 5267542 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency 14619.415532 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11618.958024 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits 5180112 # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency 1278175500 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate 0.016598 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses 87430 # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_miss_latency 1015845500 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate 0.016598 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_misses 87430 # number of ReadReq MSHR misses
+system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu1.icache.avg_refs 59.267660 # Average number of references to valid blocks.
+system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.demand_accesses 5267542 # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 14619.415532 # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency
+system.cpu1.icache.demand_hits 5180112 # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency 1278175500 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate 0.016598 # miss rate for demand accesses
+system.cpu1.icache.demand_misses 87430 # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency 1015845500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate 0.016598 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses 87430 # number of demand (read+write) MSHR misses
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.overall_accesses 5267542 # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 14619.415532 # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu1.icache.overall_hits 5180112 # number of overall hits
+system.cpu1.icache.overall_miss_latency 1278175500 # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate 0.016598 # miss rate for overall accesses
+system.cpu1.icache.overall_misses 87430 # number of overall misses
+system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency 1015845500 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate 0.016598 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses 87430 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.icache.replacements 86890 # number of replacements
+system.cpu1.icache.sampled_refs 87402 # Sample count of references to valid blocks.
+system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.tagsinuse 419.405623 # Cycle average of tags in use
+system.cpu1.icache.total_refs 5180112 # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1967879772000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.writebacks 0 # number of writebacks
+system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles
+system.cpu1.itb.accesses 1397499 # ITB accesses
+system.cpu1.itb.acv 41 # ITB acv
+system.cpu1.itb.hits 1396253 # ITB hits
+system.cpu1.itb.misses 1246 # ITB misses
+system.cpu1.kern.callpal 29501 # number of callpals executed
+system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed
+system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed
+system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed
+system.cpu1.kern.callpal_swpctx 365 1.24% 1.27% # number of callpals executed
+system.cpu1.kern.callpal_tbi 10 0.03% 1.30% # number of callpals executed
+system.cpu1.kern.callpal_wrent 7 0.02% 1.33% # number of callpals executed
+system.cpu1.kern.callpal_swpipl 24142 81.83% 83.16% # number of callpals executed
+system.cpu1.kern.callpal_rdps 2172 7.36% 90.52% # number of callpals executed
+system.cpu1.kern.callpal_wrkgp 1 0.00% 90.53% # number of callpals executed
+system.cpu1.kern.callpal_wrusp 3 0.01% 90.54% # number of callpals executed
+system.cpu1.kern.callpal_rdusp 2 0.01% 90.54% # number of callpals executed
+system.cpu1.kern.callpal_whami 3 0.01% 90.55% # number of callpals executed
+system.cpu1.kern.callpal_rti 2594 8.79% 99.35% # number of callpals executed
+system.cpu1.kern.callpal_callsys 161 0.55% 99.89% # number of callpals executed
+system.cpu1.kern.callpal_imb 31 0.11% 100.00% # number of callpals executed
+system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.hwrei 36051 # number of hwrei instructions executed
+system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed
+system.cpu1.kern.ipl_count 28808 # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0 9172 31.84% 31.84% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_22 1980 6.87% 38.71% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_30 91 0.32% 39.03% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31 17565 60.97% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good 20308 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0 9164 45.13% 45.13% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31 9073 44.68% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks 1971683837000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0 1927969399500 97.78% 97.78% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22 511268500 0.03% 97.81% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30 58584000 0.00% 97.81% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31 43144585000 2.19% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used_0 0.999128 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_31 0.516539 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel 532
+system.cpu1.kern.mode_good_user 516
+system.cpu1.kern.mode_good_idle 16
+system.cpu1.kern.mode_switch_kernel 880 # number of protection mode switches
+system.cpu1.kern.mode_switch_user 516 # number of protection mode switches
+system.cpu1.kern.mode_switch_idle 2081 # number of protection mode switches
+system.cpu1.kern.mode_switch_good 1.612234 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel 0.604545 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_idle 0.007689 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel 4597806000 0.23% 0.23% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user 1703603000 0.09% 0.32% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle 1964669629000 99.68% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 366 # number of times the context was actually changed
+system.cpu1.kern.syscall 102 # number of syscalls executed
+system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed
+system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed
+system.cpu1.kern.syscall_4 1 0.98% 13.73% # number of syscalls executed
+system.cpu1.kern.syscall_6 12 11.76% 25.49% # number of syscalls executed
+system.cpu1.kern.syscall_17 5 4.90% 30.39% # number of syscalls executed
+system.cpu1.kern.syscall_19 4 3.92% 34.31% # number of syscalls executed
+system.cpu1.kern.syscall_20 2 1.96% 36.27% # number of syscalls executed
+system.cpu1.kern.syscall_23 2 1.96% 38.24% # number of syscalls executed
+system.cpu1.kern.syscall_24 2 1.96% 40.20% # number of syscalls executed
+system.cpu1.kern.syscall_33 3 2.94% 43.14% # number of syscalls executed
+system.cpu1.kern.syscall_45 15 14.71% 57.84% # number of syscalls executed
+system.cpu1.kern.syscall_47 2 1.96% 59.80% # number of syscalls executed
+system.cpu1.kern.syscall_48 3 2.94% 62.75% # number of syscalls executed
+system.cpu1.kern.syscall_54 1 0.98% 63.73% # number of syscalls executed
+system.cpu1.kern.syscall_59 2 1.96% 65.69% # number of syscalls executed
+system.cpu1.kern.syscall_71 22 21.57% 87.25% # number of syscalls executed
+system.cpu1.kern.syscall_74 7 6.86% 94.12% # number of syscalls executed
+system.cpu1.kern.syscall_90 1 0.98% 95.10% # number of syscalls executed
+system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed
+system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed
+system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed
+system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles
+system.cpu1.numCycles 3943367734 # number of cpu cycles simulated
+system.cpu1.num_insts 5264352 # Number of instructions executed
+system.cpu1.num_refs 1703685 # Number of memory references
+system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
+system.disk0.dma_write_txs 395 # Number of DMA write transactions.
+system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iocache.ReadReq_accesses 178 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_avg_miss_latency 115196.617978 # average ReadReq miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses 178 # number of ReadReq misses
+system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses
+system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_avg_miss_latency 137906.834954 # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85903.204082 # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency 5730304806 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses 41552 # number of WriteReq misses
+system.iocache.WriteReq_mshr_miss_latency 3569449936 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
+system.iocache.avg_blocked_cycles_no_mshrs 6168.564107 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.iocache.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs 10459 # number of cycles access was blocked
+system.iocache.blocked_no_targets 0 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs 64517012 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.demand_accesses 41730 # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency 137809.964150 # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency
+system.iocache.demand_hits 0 # number of demand (read+write) hits
+system.iocache.demand_miss_latency 5750809804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate 1 # miss rate for demand accesses
+system.iocache.demand_misses 41730 # number of demand (read+write) misses
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency 3580698934 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.overall_accesses 41730 # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency 137809.964150 # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.iocache.overall_hits 0 # number of overall hits
+system.iocache.overall_miss_latency 5750809804 # number of overall miss cycles
+system.iocache.overall_miss_rate 1 # miss rate for overall accesses
+system.iocache.overall_misses 41730 # number of overall misses
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency 3580698934 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements 41698 # number of replacements
+system.iocache.sampled_refs 41714 # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse 0.582076 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.warmup_cycle 1762323729000 # Cycle when the warmup percentage was hit.
+system.iocache.writebacks 41520 # number of writebacks
+system.l2c.ReadExReq_accesses 306796 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 52002.653229 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40002.653229 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 15954206000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 306796 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 12272654000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 306796 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 2090247 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 52016.274350 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.322096 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits 1782800 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 15992247500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.147086 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 307447 # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency 12302458000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.147081 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 307436 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 789200000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses 127300 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 50741.146897 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40004.988217 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 6459348000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 127300 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 5092635000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 127300 # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency 1381237000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses 430395 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 430395 # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_refs 4.558799 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.demand_accesses 2397043 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 52009.471007 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency
+system.l2c.demand_hits 1782800 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 31946453500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.256250 # miss rate for demand accesses
+system.l2c.demand_misses 614243 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 24575112000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.256246 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 614232 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.overall_accesses 2397043 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 52009.471007 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.overall_hits 1782800 # number of overall hits
+system.l2c.overall_miss_latency 31946453500 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.256250 # miss rate for overall accesses
+system.l2c.overall_misses 614243 # number of overall misses
+system.l2c.overall_mshr_hits 11 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 24575112000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.256246 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 614232 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 2170437000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements 399043 # number of replacements
+system.l2c.sampled_refs 430765 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 30865.823052 # Cycle average of tags in use
+system.l2c.total_refs 1963771 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 123178 # number of writebacks
+system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: 591544000: Trying to launch CPU number 1!
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:30:58
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:38:12
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1972135479000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1283720 # Simulator instruction rate (inst/s)
-host_mem_usage 286560 # Number of bytes of host memory used
-host_seconds 43.75 # Real time elapsed on the host
-host_tick_rate 44115985890 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 56165112 # Number of instructions simulated
-sim_seconds 1.930166 # Number of seconds simulated
-sim_ticks 1930165791000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 200388 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.212121 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.212121 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits 183063 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 248808000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate 0.086457 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses 17325 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196833000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086457 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 17325 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses 8882666 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 25452.857499 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.814515 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits 7812517 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 27238350000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.120476 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1070149 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 24027857000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.120476 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1070149 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 847845000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses 199368 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.365794 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.365794 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits 169362 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_latency 1680467000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_rate 0.150506 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses 30006 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590449000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150506 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_misses 30006 # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6158164 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56004.032630 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.032630 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits 5757309 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 22449496500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.065093 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 21246931500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.065093 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1186275000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 10.091593 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 15040830 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 33778.185851 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 13569826 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 49687846500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.097801 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1471004 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 45274788500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.097801 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1471004 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 15040830 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 33778.185851 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 13569826 # number of overall hits
-system.cpu.dcache.overall_miss_latency 49687846500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.097801 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1471004 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 45274788500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.097801 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1471004 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 2034120000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 1391586 # number of replacements
-system.cpu.dcache.sampled_refs 1392098 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.984141 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14048487 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 430461 # number of writebacks
-system.cpu.dtb.accesses 1020784 # DTB accesses
-system.cpu.dtb.acv 367 # DTB access violations
-system.cpu.dtb.hits 15421361 # DTB hits
-system.cpu.dtb.misses 11466 # DTB misses
-system.cpu.dtb.read_accesses 728853 # DTB read accesses
-system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_hits 9063577 # DTB read hits
-system.cpu.dtb.read_misses 10324 # DTB read misses
-system.cpu.dtb.write_accesses 291931 # DTB write accesses
-system.cpu.dtb.write_acv 157 # DTB write access violations
-system.cpu.dtb.write_hits 6357784 # DTB write hits
-system.cpu.dtb.write_misses 1142 # DTB write misses
-system.cpu.icache.ReadReq_accesses 56176946 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 14711.628674 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.898216 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 55246023 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 13695393500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.016571 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 930923 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 10901944500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.016571 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 930923 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 59.355692 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 56176946 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 14711.628674 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency
-system.cpu.icache.demand_hits 55246023 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 13695393500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.016571 # miss rate for demand accesses
-system.cpu.icache.demand_misses 930923 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 10901944500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.016571 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 930923 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 56176946 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 14711.628674 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 55246023 # number of overall hits
-system.cpu.icache.overall_miss_latency 13695393500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.016571 # miss rate for overall accesses
-system.cpu.icache.overall_misses 930923 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 10901944500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.016571 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 930923 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 930251 # number of replacements
-system.cpu.icache.sampled_refs 930762 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 508.559731 # Cycle average of tags in use
-system.cpu.icache.total_refs 55246023 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0.929251 # Percentage of idle cycles
-system.cpu.itb.accesses 4982832 # ITB accesses
-system.cpu.itb.acv 184 # ITB acv
-system.cpu.itb.hits 4977822 # ITB hits
-system.cpu.itb.misses 5010 # ITB misses
-system.cpu.kern.callpal 193204 # number of callpals executed
-system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed
-system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed
-system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed
-system.cpu.kern.callpal_swpipl 176240 91.22% 93.41% # number of callpals executed
-system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed
-system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal_rti 5169 2.68% 99.64% # number of callpals executed
-system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
-system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.hwrei 212308 # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce 6258 # number of quiesce instructions executed
-system.cpu.kern.ipl_count 183485 # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0 74993 40.87% 40.87% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31 106417 58.00% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good 149327 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0 73626 49.31% 49.31% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31 73626 49.31% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks 1930165033000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0 1867007591000 96.73% 96.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_21 96059500 0.00% 96.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_22 565327500 0.03% 96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31 62496055000 3.24% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used_0 0.981772 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31 0.691863 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel 1910
-system.cpu.kern.mode_good_user 1743
-system.cpu.kern.mode_good_idle 167
-system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches
-system.cpu.kern.mode_switch_user 1743 # number of protection mode switches
-system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches
-system.cpu.kern.mode_switch_good 1.402741 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel 0.322799 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel 48448667000 2.51% 2.51% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user 5540662000 0.29% 2.80% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle 1876175702000 97.20% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4172 # number of times the context was actually changed
-system.cpu.kern.syscall 326 # number of syscalls executed
-system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
-system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
-system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed
-system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed
-system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed
-system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed
-system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed
-system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed
-system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed
-system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed
-system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed
-system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed
-system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed
-system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed
-system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed
-system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed
-system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed
-system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed
-system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed
-system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed
-system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed
-system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed
-system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed
-system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed
-system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed
-system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed
-system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed
-system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
-system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
-system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
-system.cpu.not_idle_fraction 0.070749 # Percentage of non-idle cycles
-system.cpu.numCycles 3860331582 # number of cpu cycles simulated
-system.cpu.num_insts 56165112 # Number of instructions executed
-system.cpu.num_refs 15669461 # Number of memory references
-system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
-system.disk0.dma_write_txs 395 # Number of DMA write transactions.
-system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses 173 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
-system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency 137880.578697 # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85877.091981 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 5729213806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses 41552 # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency 3568364926 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles_no_mshrs 6163.865928 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked
-system.iocache.blocked_no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_mshrs 64548004 # number of cycles access was blocked
-system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency 137786.765824 # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency
-system.iocache.demand_hits 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 5749152804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate 1 # miss rate for demand accesses
-system.iocache.demand_misses 41725 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 3579307924 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency 137786.765824 # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.iocache.overall_hits 0 # number of overall hits
-system.iocache.overall_miss_latency 5749152804 # number of overall miss cycles
-system.iocache.overall_miss_rate 1 # miss rate for overall accesses
-system.iocache.overall_misses 41725 # number of overall misses
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 3579307924 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.iocache.replacements 41685 # number of replacements
-system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 1.353410 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 1762299198000 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 41512 # number of writebacks
-system.l2c.ReadExReq_accesses 304625 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 52003.272876 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40003.272876 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 15841497000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 304625 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 12185997000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 304625 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 2018377 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 52016.376522 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.358642 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits 1710772 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 16000497500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.152402 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 307605 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 12309232000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.152402 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 307605 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 759315000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses 126236 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 52001.881397 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.980861 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 6564509500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 126236 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 5050195000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 126236 # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1071771000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 430461 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 430461 # number of Writeback hits
-system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 4.436452 # Average number of references to valid blocks.
-system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 2323002 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 52009.856590 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency
-system.l2c.demand_hits 1710772 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 31841994500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.263551 # miss rate for demand accesses
-system.l2c.demand_misses 612230 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 24495229000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.263551 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 612230 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 2323002 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 52009.856590 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 1710772 # number of overall hits
-system.l2c.overall_miss_latency 31841994500 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.263551 # miss rate for overall accesses
-system.l2c.overall_misses 612230 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 24495229000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.263551 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 612230 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 1831086000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 394925 # number of replacements
-system.l2c.sampled_refs 425907 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30594.024615 # Cycle average of tags in use
-system.l2c.total_refs 1889516 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 119047 # number of writebacks
-system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
-system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
-system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: kernel located at: /dist/m5/system/binaries/vmlinux
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:37:43
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 1930165791000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1283720 # Simulator instruction rate (inst/s)
+host_mem_usage 286560 # Number of bytes of host memory used
+host_seconds 43.75 # Real time elapsed on the host
+host_tick_rate 44115985890 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 56165112 # Number of instructions simulated
+sim_seconds 1.930166 # Number of seconds simulated
+sim_ticks 1930165791000 # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses 200388 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.212121 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.212121 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits 183063 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 248808000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate 0.086457 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses 17325 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196833000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086457 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_misses 17325 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 8882666 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 25452.857499 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.814515 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_hits 7812517 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 27238350000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.120476 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1070149 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 24027857000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.120476 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1070149 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 847845000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses 199368 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.365794 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.365794 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_hits 169362 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_latency 1680467000 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_rate 0.150506 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses 30006 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590449000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150506 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_misses 30006 # number of StoreCondReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6158164 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56004.032630 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.032630 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_hits 5757309 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 22449496500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.065093 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 21246931500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.065093 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1186275000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 10.091593 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 15040830 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 33778.185851 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 13569826 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 49687846500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.097801 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1471004 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 45274788500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.097801 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1471004 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 15040830 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 33778.185851 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 30778.154580 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 13569826 # number of overall hits
+system.cpu.dcache.overall_miss_latency 49687846500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.097801 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1471004 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 45274788500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.097801 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1471004 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 2034120000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 1391586 # number of replacements
+system.cpu.dcache.sampled_refs 1392098 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 511.984141 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14048487 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 430461 # number of writebacks
+system.cpu.dtb.accesses 1020784 # DTB accesses
+system.cpu.dtb.acv 367 # DTB access violations
+system.cpu.dtb.hits 15421361 # DTB hits
+system.cpu.dtb.misses 11466 # DTB misses
+system.cpu.dtb.read_accesses 728853 # DTB read accesses
+system.cpu.dtb.read_acv 210 # DTB read access violations
+system.cpu.dtb.read_hits 9063577 # DTB read hits
+system.cpu.dtb.read_misses 10324 # DTB read misses
+system.cpu.dtb.write_accesses 291931 # DTB write accesses
+system.cpu.dtb.write_acv 157 # DTB write access violations
+system.cpu.dtb.write_hits 6357784 # DTB write hits
+system.cpu.dtb.write_misses 1142 # DTB write misses
+system.cpu.icache.ReadReq_accesses 56176946 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 14711.628674 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.898216 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 55246023 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 13695393500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.016571 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 930923 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 10901944500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.016571 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 930923 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 59.355692 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 56176946 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 14711.628674 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency
+system.cpu.icache.demand_hits 55246023 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 13695393500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.016571 # miss rate for demand accesses
+system.cpu.icache.demand_misses 930923 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 10901944500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.016571 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 930923 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 56176946 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 14711.628674 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11710.898216 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 55246023 # number of overall hits
+system.cpu.icache.overall_miss_latency 13695393500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.016571 # miss rate for overall accesses
+system.cpu.icache.overall_misses 930923 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 10901944500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.016571 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 930923 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 930251 # number of replacements
+system.cpu.icache.sampled_refs 930762 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 508.559731 # Cycle average of tags in use
+system.cpu.icache.total_refs 55246023 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 39055604000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0.929251 # Percentage of idle cycles
+system.cpu.itb.accesses 4982832 # ITB accesses
+system.cpu.itb.acv 184 # ITB acv
+system.cpu.itb.hits 4977822 # ITB hits
+system.cpu.itb.misses 5010 # ITB misses
+system.cpu.kern.callpal 193204 # number of callpals executed
+system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
+system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed
+system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed
+system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed
+system.cpu.kern.callpal_swpipl 176240 91.22% 93.41% # number of callpals executed
+system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed
+system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal_rti 5169 2.68% 99.64% # number of callpals executed
+system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
+system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.hwrei 212308 # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce 6258 # number of quiesce instructions executed
+system.cpu.kern.ipl_count 183485 # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0 74993 40.87% 40.87% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31 106417 58.00% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good 149327 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0 73626 49.31% 49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31 73626 49.31% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks 1930165033000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0 1867007591000 96.73% 96.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21 96059500 0.00% 96.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22 565327500 0.03% 96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31 62496055000 3.24% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used_0 0.981772 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_31 0.691863 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel 1910
+system.cpu.kern.mode_good_user 1743
+system.cpu.kern.mode_good_idle 167
+system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches
+system.cpu.kern.mode_switch_user 1743 # number of protection mode switches
+system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches
+system.cpu.kern.mode_switch_good 1.402741 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel 0.322799 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel 48448667000 2.51% 2.51% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user 5540662000 0.29% 2.80% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle 1876175702000 97.20% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4172 # number of times the context was actually changed
+system.cpu.kern.syscall 326 # number of syscalls executed
+system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
+system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
+system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed
+system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed
+system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed
+system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed
+system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed
+system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed
+system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed
+system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed
+system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed
+system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed
+system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed
+system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed
+system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed
+system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed
+system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed
+system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed
+system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed
+system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed
+system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed
+system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed
+system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed
+system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed
+system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed
+system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed
+system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed
+system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
+system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
+system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
+system.cpu.not_idle_fraction 0.070749 # Percentage of non-idle cycles
+system.cpu.numCycles 3860331582 # number of cpu cycles simulated
+system.cpu.num_insts 56165112 # Number of instructions executed
+system.cpu.num_refs 15669461 # Number of memory references
+system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
+system.disk0.dma_write_txs 395 # Number of DMA write transactions.
+system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses 173 # number of ReadReq misses
+system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
+system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_avg_miss_latency 137880.578697 # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85877.091981 # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency 5729213806 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses 41552 # number of WriteReq misses
+system.iocache.WriteReq_mshr_miss_latency 3568364926 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
+system.iocache.avg_blocked_cycles_no_mshrs 6163.865928 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.iocache.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked
+system.iocache.blocked_no_targets 0 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs 64548004 # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency 137786.765824 # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency
+system.iocache.demand_hits 0 # number of demand (read+write) hits
+system.iocache.demand_miss_latency 5749152804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate 1 # miss rate for demand accesses
+system.iocache.demand_misses 41725 # number of demand (read+write) misses
+system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency 3579307924 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency 137786.765824 # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 85783.293565 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.iocache.overall_hits 0 # number of overall hits
+system.iocache.overall_miss_latency 5749152804 # number of overall miss cycles
+system.iocache.overall_miss_rate 1 # miss rate for overall accesses
+system.iocache.overall_misses 41725 # number of overall misses
+system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency 3579307924 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements 41685 # number of replacements
+system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse 1.353410 # Cycle average of tags in use
+system.iocache.total_refs 0 # Total number of references to valid blocks.
+system.iocache.warmup_cycle 1762299198000 # Cycle when the warmup percentage was hit.
+system.iocache.writebacks 41512 # number of writebacks
+system.l2c.ReadExReq_accesses 304625 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 52003.272876 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40003.272876 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 15841497000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 304625 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 12185997000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 304625 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 2018377 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 52016.376522 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.358642 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits 1710772 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 16000497500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.152402 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 307605 # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency 12309232000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.152402 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 307605 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 759315000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses 126236 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 52001.881397 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.980861 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 6564509500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 126236 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 5050195000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 126236 # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency 1071771000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses 430461 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 430461 # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_refs 4.436452 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.demand_accesses 2323002 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 52009.856590 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency
+system.l2c.demand_hits 1710772 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 31841994500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.263551 # miss rate for demand accesses
+system.l2c.demand_misses 612230 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 24495229000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.263551 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 612230 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.overall_accesses 2323002 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 52009.856590 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40009.847606 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.overall_hits 1710772 # number of overall hits
+system.l2c.overall_miss_latency 31841994500 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.263551 # miss rate for overall accesses
+system.l2c.overall_misses 612230 # number of overall misses
+system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 24495229000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.263551 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 612230 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 1831086000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements 394925 # number of replacements
+system.l2c.sampled_refs 425907 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 30594.024615 # Cycle average of tags in use
+system.l2c.total_refs 1889516 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 119047 # number of writebacks
+system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
+system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
+system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:30:58
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:37:43
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1930165791000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 47245 # Number of BTB hits
-global.BPredUnit.BTBLookups 62226 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 88 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 3133 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 48198 # Number of conditional branches predicted
-global.BPredUnit.lookups 72853 # Number of BP lookups
-global.BPredUnit.usedRAS 7892 # Number of times the RAS was used to get a target.
-host_inst_rate 90438 # Simulator instruction rate (inst/s)
-host_mem_usage 148172 # Number of bytes of host memory used
-host_seconds 5.53 # Real time elapsed on the host
-host_tick_rate 35958 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 15372 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 1808 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 147140 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 63225 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 500002 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 198813 # Number of ticks simulated
-system.cpu.commit.COM:branches 61160 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 24524 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 189916
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 37455 1972.19%
- 1 50343 2650.80%
- 2 29014 1527.73%
- 3 12786 673.25%
- 4 19808 1042.99%
- 5 2516 132.48%
- 6 10075 530.50%
- 7 3395 178.76%
- 8 24524 1291.31%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 518948 # Number of instructions committed
-system.cpu.commit.COM:loads 131376 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 189772 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 2863 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 518948 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 18 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 59006 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 500002 # Number of Instructions Simulated
-system.cpu.committedInsts_total 500002 # Number of Instructions Simulated
-system.cpu.cpi 0.397624 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.397624 # CPI: Total CPI of All Threads
-system.cpu.decode.DECODE:BlockedCycles 2191 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 297 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 16283 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 604200 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 76141 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 110735 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 8898 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 1017 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 849 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 72853 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 72795 # Number of cache lines fetched
-system.cpu.fetch.Cycles 186280 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.Insts 616104 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 3180 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.366438 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 72795 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 55137 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 3.098896 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 198814
-system.cpu.fetch.rateDist.min_value 0
- 0 85330 4291.95%
- 1 3737 187.96%
- 2 9626 484.17%
- 3 11018 554.19%
- 4 8626 433.87%
- 5 19021 956.72%
- 6 27490 1382.70%
- 7 6216 312.65%
- 8 27750 1395.78%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.iew.EXEC:branches 65998 # Number of branches executed
-system.cpu.iew.EXEC:insts 534582 # Number of executed instructions
-system.cpu.iew.EXEC:loads 141825 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 21827 # number of nop insts executed
-system.cpu.iew.EXEC:rate 2.688855 # Inst execution rate
-system.cpu.iew.EXEC:refs 202010 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 7038 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 60185 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 413743 # num instructions consuming a value
-system.cpu.iew.WB:count 532886 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.745847 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 308589 # num instructions producing a value
-system.cpu.iew.WB:rate 2.680324 # insts written-back per cycle
-system.cpu.iew.WB:sent 533753 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 3004 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 147140 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 1292 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 63225 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 578006 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 8898 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 22061 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 15747 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 4825 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 48 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 1801 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 1203 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 2.514936 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.514936 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 98 0
-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:IntDiv.max_value 0
-system.cpu.iq.IQ:residence:IntDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatAdd.samples 0
-system.cpu.iq.IQ:residence:FloatAdd.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:FloatAdd.max_value 0
-system.cpu.iq.IQ:residence:FloatAdd.end_dist
-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCmp.samples 0
-system.cpu.iq.IQ:residence:FloatCmp.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:FloatCmp.max_value 0
-system.cpu.iq.IQ:residence:FloatCmp.end_dist
-
-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCvt.samples 0
-system.cpu.iq.IQ:residence:FloatCvt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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-system.cpu.iq.IQ:residence:FloatCvt.max_value 0
-system.cpu.iq.IQ:residence:FloatCvt.end_dist
-
-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatMult.samples 0
-system.cpu.iq.IQ:residence:FloatMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:FloatMult.max_value 0
-system.cpu.iq.IQ:residence:FloatMult.end_dist
-
-system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatDiv.samples 0
-system.cpu.iq.IQ:residence:FloatDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 98 0
-system.cpu.iq.IQ:residence:FloatDiv.max_value 0
-system.cpu.iq.IQ:residence:FloatDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatSqrt.samples 0
-system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 98 0
-system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
-system.cpu.iq.IQ:residence:FloatSqrt.end_dist
-
-system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemRead.samples 0
-system.cpu.iq.IQ:residence:MemRead.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 98 0
-system.cpu.iq.IQ:residence:MemRead.max_value 0
-system.cpu.iq.IQ:residence:MemRead.end_dist
-
-system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemWrite.samples 0
-system.cpu.iq.IQ:residence:MemWrite.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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-system.cpu.iq.IQ:residence:MemWrite.max_value 0
-system.cpu.iq.IQ:residence:MemWrite.end_dist
-
-system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IprAccess.samples 0
-system.cpu.iq.IQ:residence:IprAccess.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 98 0
-system.cpu.iq.IQ:residence:IprAccess.max_value 0
-system.cpu.iq.IQ:residence:IprAccess.end_dist
-
-system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:InstPrefetch.samples 0
-system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 98 0
-system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
-system.cpu.iq.IQ:residence:InstPrefetch.end_dist
-
-system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:(null)_delay.samples 0
-system.cpu.iq.ISSUE:(null)_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
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- 98 0
-system.cpu.iq.ISSUE:(null)_delay.max_value 0
-system.cpu.iq.ISSUE:(null)_delay.end_dist
-
-system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntAlu_delay.samples 0
-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 92 0
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- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntMult_delay.samples 0
-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
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- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntMult_delay.max_value 0
-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntDiv_delay.samples 0
-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 541621 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 0 0.00% # Type of FU issued
- IntAlu 336144 62.06% # Type of FU issued
- IntMult 10 0.00% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 13 0.00% # Type of FU issued
- FloatCmp 3 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 2 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 144008 26.59% # Type of FU issued
- MemWrite 61441 11.34% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 10389 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.019181 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 6229 59.96% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 2497 24.04% # attempts to use FU when none available
- MemWrite 1663 16.01% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 198814
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 27333 1374.80%
- 1 36906 1856.31%
- 2 35716 1796.45%
- 3 28916 1454.42%
- 4 31868 1602.91%
- 5 13027 655.24%
- 6 21677 1090.32%
- 7 3102 156.03%
- 8 269 13.53%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 2.724260 # Inst issue rate
-system.cpu.iq.iqInstsAdded 556152 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 541621 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 55198 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 404 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 27398 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.numCycles 198814 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 266 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 386063 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 78342 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 1401 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 775201 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 594947 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 443127 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 109388 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 8898 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1662 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 57015 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 258 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 41 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 4872 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 39 # count of temporary serializing insts renamed
-system.workload.PROG:num_syscalls 18 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Entering event queue @ 0. Starting simulation...
+warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
+
+gzip: stdout: Broken pipe
--- /dev/null
+main dictionary has 1245 entries
+49508 bytes wasted
+>M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jul 27 2006 17:25:03
+M5 started Thu Jul 27 17:25:11 2006
+M5 executing on zamp.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/detailed tests/test1/run.py --detailed
+Exiting @ tick 198813 because a thread reached the max instruction count
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 47245 # Number of BTB hits
+global.BPredUnit.BTBLookups 62226 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 88 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 3133 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 48198 # Number of conditional branches predicted
+global.BPredUnit.lookups 72853 # Number of BP lookups
+global.BPredUnit.usedRAS 7892 # Number of times the RAS was used to get a target.
+host_inst_rate 90438 # Simulator instruction rate (inst/s)
+host_mem_usage 148172 # Number of bytes of host memory used
+host_seconds 5.53 # Real time elapsed on the host
+host_tick_rate 35958 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 15372 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 1808 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 147140 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 63225 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 500002 # Number of instructions simulated
+sim_seconds 0.000000 # Number of seconds simulated
+sim_ticks 198813 # Number of ticks simulated
+system.cpu.commit.COM:branches 61160 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 24524 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 189916
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 37455 1972.19%
+ 1 50343 2650.80%
+ 2 29014 1527.73%
+ 3 12786 673.25%
+ 4 19808 1042.99%
+ 5 2516 132.48%
+ 6 10075 530.50%
+ 7 3395 178.76%
+ 8 24524 1291.31%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 518948 # Number of instructions committed
+system.cpu.commit.COM:loads 131376 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 189772 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 2863 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 518948 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 18 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 59006 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 500002 # Number of Instructions Simulated
+system.cpu.committedInsts_total 500002 # Number of Instructions Simulated
+system.cpu.cpi 0.397624 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.397624 # CPI: Total CPI of All Threads
+system.cpu.decode.DECODE:BlockedCycles 2191 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 297 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 16283 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 604200 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 76141 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 110735 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 8898 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1017 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 849 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 72853 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 72795 # Number of cache lines fetched
+system.cpu.fetch.Cycles 186280 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Insts 616104 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 3180 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.366438 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 72795 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 55137 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 3.098896 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 198814
+system.cpu.fetch.rateDist.min_value 0
+ 0 85330 4291.95%
+ 1 3737 187.96%
+ 2 9626 484.17%
+ 3 11018 554.19%
+ 4 8626 433.87%
+ 5 19021 956.72%
+ 6 27490 1382.70%
+ 7 6216 312.65%
+ 8 27750 1395.78%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.iew.EXEC:branches 65998 # Number of branches executed
+system.cpu.iew.EXEC:insts 534582 # Number of executed instructions
+system.cpu.iew.EXEC:loads 141825 # Number of load instructions executed
+system.cpu.iew.EXEC:nop 21827 # number of nop insts executed
+system.cpu.iew.EXEC:rate 2.688855 # Inst execution rate
+system.cpu.iew.EXEC:refs 202010 # number of memory reference insts executed
+system.cpu.iew.EXEC:squashedInsts 7038 # Number of squashed instructions skipped in execute
+system.cpu.iew.EXEC:stores 60185 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 413743 # num instructions consuming a value
+system.cpu.iew.WB:count 532886 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.745847 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 308589 # num instructions producing a value
+system.cpu.iew.WB:rate 2.680324 # insts written-back per cycle
+system.cpu.iew.WB:sent 533753 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 3004 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 147140 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1292 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 63225 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 578006 # Number of instructions dispatched to IQ
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 8898 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 22061 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 15747 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 4825 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 48 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1801 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1203 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 2.514936 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.514936 # IPC: Total IPC of All Threads
+system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
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+
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+
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+
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+
+system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatSqrt.end_dist
+
+system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:MemWrite.end_dist
+
+system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:IprAccess.max_value 0
+system.cpu.iq.IQ:residence:IprAccess.end_dist
+
+system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
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+system.cpu.iq.ISSUE:(null)_delay.min_value 0
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+
+system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
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+
+system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
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+
+system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
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+
+system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
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+
+system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
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+
+system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
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+
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+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
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+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
+system.cpu.iq.ISSUE:FloatMult_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
+system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
+system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
+
+system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemRead_delay.samples 0
+system.cpu.iq.ISSUE:MemRead_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemRead_delay.max_value 0
+system.cpu.iq.ISSUE:MemRead_delay.end_dist
+
+system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemWrite_delay.samples 0
+system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
+system.cpu.iq.ISSUE:MemWrite_delay.end_dist
+
+system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IprAccess_delay.samples 0
+system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
+system.cpu.iq.ISSUE:IprAccess_delay.end_dist
+
+system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
+
+system.cpu.iq.ISSUE:FU_type_0 541621 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 336144 62.06% # Type of FU issued
+ IntMult 10 0.00% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 13 0.00% # Type of FU issued
+ FloatCmp 3 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 2 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 144008 26.59% # Type of FU issued
+ MemWrite 61441 11.34% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 10389 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.019181 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 6229 59.96% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 2497 24.04% # attempts to use FU when none available
+ MemWrite 1663 16.01% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 198814
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 27333 1374.80%
+ 1 36906 1856.31%
+ 2 35716 1796.45%
+ 3 28916 1454.42%
+ 4 31868 1602.91%
+ 5 13027 655.24%
+ 6 21677 1090.32%
+ 7 3102 156.03%
+ 8 269 13.53%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 2.724260 # Inst issue rate
+system.cpu.iq.iqInstsAdded 556152 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 541621 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 55198 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 404 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 27398 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.numCycles 198814 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 266 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 386063 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 78342 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1401 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 775201 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 594947 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 443127 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 109388 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 8898 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1662 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 57015 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 258 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 41 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 4872 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 39 # count of temporary serializing insts renamed
+system.workload.PROG:num_syscalls 18 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-
-gzip: stdout: Broken pipe
+++ /dev/null
-main dictionary has 1245 entries
-49508 bytes wasted
->M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Jul 27 2006 17:25:03
-M5 started Thu Jul 27 17:25:11 2006
-M5 executing on zamp.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/test1/detailed tests/test1/run.py --detailed
-Exiting @ tick 198813 because a thread reached the max instruction count
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 4911987 # Simulator instruction rate (inst/s)
-host_mem_usage 189996 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
-host_tick_rate 2448419888 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 500001 # Number of instructions simulated
-sim_seconds 0.000250 # Number of seconds simulated
-sim_ticks 250015500 # Number of ticks simulated
-system.cpu.dtb.accesses 180793 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 180775 # DTB hits
-system.cpu.dtb.misses 18 # DTB misses
-system.cpu.dtb.read_accesses 124443 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 124435 # DTB read hits
-system.cpu.dtb.read_misses 8 # DTB read misses
-system.cpu.dtb.write_accesses 56350 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 56340 # DTB write hits
-system.cpu.dtb.write_misses 10 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 500032 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 500019 # ITB hits
-system.cpu.itb.misses 13 # ITB misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 500032 # number of cpu cycles simulated
-system.cpu.num_insts 500001 # Number of instructions executed
-system.cpu.num_refs 182222 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:27:20
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 250015500 because a thread reached the max instruction count
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 4911987 # Simulator instruction rate (inst/s)
+host_mem_usage 189996 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+host_tick_rate 2448419888 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 500001 # Number of instructions simulated
+sim_seconds 0.000250 # Number of seconds simulated
+sim_ticks 250015500 # Number of ticks simulated
+system.cpu.dtb.accesses 180793 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 180775 # DTB hits
+system.cpu.dtb.misses 18 # DTB misses
+system.cpu.dtb.read_accesses 124443 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 124435 # DTB read hits
+system.cpu.dtb.read_misses 8 # DTB read misses
+system.cpu.dtb.write_accesses 56350 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 56340 # DTB write hits
+system.cpu.dtb.write_misses 10 # DTB write misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 500032 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 500019 # ITB hits
+system.cpu.itb.misses 13 # ITB misses
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 500032 # number of cpu cycles simulated
+system.cpu.num_insts 500001 # Number of instructions executed
+system.cpu.num_refs 182222 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:27:20
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-main dictionary has 1245 entries
-49508 bytes wasted
->Exiting @ tick 250015500 because a thread reached the max instruction count
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 883179 # Simulator instruction rate (inst/s)
-host_mem_usage 197372 # Number of bytes of host memory used
-host_seconds 0.57 # Real time elapsed on the host
-host_tick_rate 1301859777 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 500001 # Number of instructions simulated
-sim_seconds 0.000737 # Number of seconds simulated
-sim_ticks 737389000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 17640000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 16695000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 17416000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 16483000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 35056000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 33178000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 180149 # number of overall hits
-system.cpu.dcache.overall_miss_latency 35056000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 626 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 33178000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 286.463742 # Cycle average of tags in use
-system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dtb.accesses 180793 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 180775 # DTB hits
-system.cpu.dtb.misses 18 # DTB misses
-system.cpu.dtb.read_accesses 124443 # DTB read accesses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 124435 # DTB read hits
-system.cpu.dtb.read_misses 8 # DTB read misses
-system.cpu.dtb.write_accesses 56350 # DTB write accesses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 56340 # DTB write hits
-system.cpu.dtb.write_misses 10 # DTB write misses
-system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 22568000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
-system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 21359000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 499617 # number of overall hits
-system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
-system.cpu.icache.overall_misses 403 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 21359000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 264.328816 # Cycle average of tags in use
-system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 500033 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 500020 # ITB hits
-system.cpu.itb.misses 13 # ITB misses
-system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 7228000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 5560000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 37336000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 8944000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6880000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 44564000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 34280000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 857 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 34280000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 370.220381 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1474778 # number of cpu cycles simulated
-system.cpu.num_insts 500001 # Number of instructions executed
-system.cpu.num_refs 182222 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:29:51
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 737389000 because a thread reached the max instruction count
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 883179 # Simulator instruction rate (inst/s)
+host_mem_usage 197372 # Number of bytes of host memory used
+host_seconds 0.57 # Real time elapsed on the host
+host_tick_rate 1301859777 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 500001 # Number of instructions simulated
+sim_seconds 0.000737 # Number of seconds simulated
+sim_ticks 737389000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 17640000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 16695000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 17416000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 16483000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 35056000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 33178000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 180149 # number of overall hits
+system.cpu.dcache.overall_miss_latency 35056000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 626 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 33178000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 286.463742 # Cycle average of tags in use
+system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.dtb.accesses 180793 # DTB accesses
+system.cpu.dtb.acv 0 # DTB access violations
+system.cpu.dtb.hits 180775 # DTB hits
+system.cpu.dtb.misses 18 # DTB misses
+system.cpu.dtb.read_accesses 124443 # DTB read accesses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_hits 124435 # DTB read hits
+system.cpu.dtb.read_misses 8 # DTB read misses
+system.cpu.dtb.write_accesses 56350 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 56340 # DTB write hits
+system.cpu.dtb.write_misses 10 # DTB write misses
+system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 22568000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
+system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 21359000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 499617 # number of overall hits
+system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
+system.cpu.icache.overall_misses 403 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 21359000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 264.328816 # Cycle average of tags in use
+system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 500033 # ITB accesses
+system.cpu.itb.acv 0 # ITB acv
+system.cpu.itb.hits 500020 # ITB hits
+system.cpu.itb.misses 13 # ITB misses
+system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 7228000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 5560000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 37336000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 8944000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6880000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 44564000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 34280000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 0 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 857 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 34280000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 370.220381 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1474778 # number of cpu cycles simulated
+system.cpu.num_insts 500001 # Number of instructions executed
+system.cpu.num_refs 182222 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:29:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-main dictionary has 1245 entries
-49508 bytes wasted
->Exiting @ tick 737389000 because a thread reached the max instruction count
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 2958551 # Simulator instruction rate (inst/s)
-host_mem_usage 1121980 # Number of bytes of host memory used
-host_seconds 0.68 # Real time elapsed on the host
-host_tick_rate 369689554 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2000004 # Number of instructions simulated
-sim_seconds 0.000250 # Number of seconds simulated
-sim_ticks 250015500 # Number of ticks simulated
-system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 180140 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 635 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.dcache.replacements 61 # number of replacements
-system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 29 # number of writebacks
-system.cpu0.dtb.accesses 180793 # DTB accesses
-system.cpu0.dtb.acv 0 # DTB access violations
-system.cpu0.dtb.hits 180775 # DTB hits
-system.cpu0.dtb.misses 18 # DTB misses
-system.cpu0.dtb.read_accesses 124443 # DTB read accesses
-system.cpu0.dtb.read_acv 0 # DTB read access violations
-system.cpu0.dtb.read_hits 124435 # DTB read hits
-system.cpu0.dtb.read_misses 8 # DTB read misses
-system.cpu0.dtb.write_accesses 56350 # DTB write accesses
-system.cpu0.dtb.write_acv 0 # DTB write access violations
-system.cpu0.dtb.write_hits 56340 # DTB write hits
-system.cpu0.dtb.write_misses 10 # DTB write misses
-system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 499556 # number of overall hits
-system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 463 # number of overall misses
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.icache.replacements 152 # number of replacements
-system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idle_fraction 0 # Percentage of idle cycles
-system.cpu0.itb.accesses 500032 # ITB accesses
-system.cpu0.itb.acv 0 # ITB acv
-system.cpu0.itb.hits 500019 # ITB hits
-system.cpu0.itb.misses 13 # ITB misses
-system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu0.numCycles 500032 # number of cpu cycles simulated
-system.cpu0.num_insts 500001 # Number of instructions executed
-system.cpu0.num_refs 182222 # Number of memory references
-system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 180140 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 180140 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 635 # number of overall misses
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.dcache.replacements 61 # number of replacements
-system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 29 # number of writebacks
-system.cpu1.dtb.accesses 180793 # DTB accesses
-system.cpu1.dtb.acv 0 # DTB access violations
-system.cpu1.dtb.hits 180775 # DTB hits
-system.cpu1.dtb.misses 18 # DTB misses
-system.cpu1.dtb.read_accesses 124443 # DTB read accesses
-system.cpu1.dtb.read_acv 0 # DTB read access violations
-system.cpu1.dtb.read_hits 124435 # DTB read hits
-system.cpu1.dtb.read_misses 8 # DTB read misses
-system.cpu1.dtb.write_accesses 56350 # DTB write accesses
-system.cpu1.dtb.write_acv 0 # DTB write access violations
-system.cpu1.dtb.write_hits 56340 # DTB write hits
-system.cpu1.dtb.write_misses 10 # DTB write misses
-system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits 499556 # number of overall hits
-system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu1.icache.overall_misses 463 # number of overall misses
-system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.icache.replacements 152 # number of replacements
-system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.idle_fraction 0 # Percentage of idle cycles
-system.cpu1.itb.accesses 500032 # ITB accesses
-system.cpu1.itb.acv 0 # ITB acv
-system.cpu1.itb.hits 500019 # ITB hits
-system.cpu1.itb.misses 13 # ITB misses
-system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu1.numCycles 500032 # number of cpu cycles simulated
-system.cpu1.num_insts 500001 # Number of instructions executed
-system.cpu1.num_refs 182222 # Number of memory references
-system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits
-system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses
-system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.fast_writes 0 # number of fast writes performed
-system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu2.dcache.overall_hits 180140 # number of overall hits
-system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu2.dcache.overall_misses 635 # number of overall misses
-system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu2.dcache.replacements 61 # number of replacements
-system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks.
-system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.writebacks 29 # number of writebacks
-system.cpu2.dtb.accesses 180793 # DTB accesses
-system.cpu2.dtb.acv 0 # DTB access violations
-system.cpu2.dtb.hits 180775 # DTB hits
-system.cpu2.dtb.misses 18 # DTB misses
-system.cpu2.dtb.read_accesses 124443 # DTB read accesses
-system.cpu2.dtb.read_acv 0 # DTB read access violations
-system.cpu2.dtb.read_hits 124435 # DTB read hits
-system.cpu2.dtb.read_misses 8 # DTB read misses
-system.cpu2.dtb.write_accesses 56350 # DTB write accesses
-system.cpu2.dtb.write_acv 0 # DTB write access violations
-system.cpu2.dtb.write_hits 56340 # DTB write hits
-system.cpu2.dtb.write_misses 10 # DTB write misses
-system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits
-system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.demand_accesses 500019 # number of demand (read+write) accesses
-system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits
-system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu2.icache.fast_writes 0 # number of fast writes performed
-system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses
-system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu2.icache.overall_hits 499556 # number of overall hits
-system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu2.icache.overall_misses 463 # number of overall misses
-system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu2.icache.replacements 152 # number of replacements
-system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks.
-system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.writebacks 0 # number of writebacks
-system.cpu2.idle_fraction 0 # Percentage of idle cycles
-system.cpu2.itb.accesses 500032 # ITB accesses
-system.cpu2.itb.acv 0 # ITB acv
-system.cpu2.itb.hits 500019 # ITB hits
-system.cpu2.itb.misses 13 # ITB misses
-system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu2.numCycles 500032 # number of cpu cycles simulated
-system.cpu2.num_insts 500001 # Number of instructions executed
-system.cpu2.num_refs 182222 # Number of memory references
-system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.cache_copies 0 # number of cache copies performed
-system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu3.dcache.demand_hits 180140 # number of demand (read+write) hits
-system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses
-system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.fast_writes 0 # number of fast writes performed
-system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu3.dcache.overall_hits 180140 # number of overall hits
-system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu3.dcache.overall_misses 635 # number of overall misses
-system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu3.dcache.replacements 61 # number of replacements
-system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks.
-system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.writebacks 29 # number of writebacks
-system.cpu3.dtb.accesses 180793 # DTB accesses
-system.cpu3.dtb.acv 0 # DTB access violations
-system.cpu3.dtb.hits 180775 # DTB hits
-system.cpu3.dtb.misses 18 # DTB misses
-system.cpu3.dtb.read_accesses 124443 # DTB read accesses
-system.cpu3.dtb.read_acv 0 # DTB read access violations
-system.cpu3.dtb.read_hits 124435 # DTB read hits
-system.cpu3.dtb.read_misses 8 # DTB read misses
-system.cpu3.dtb.write_accesses 56350 # DTB write accesses
-system.cpu3.dtb.write_acv 0 # DTB write access violations
-system.cpu3.dtb.write_hits 56340 # DTB write hits
-system.cpu3.dtb.write_misses 10 # DTB write misses
-system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits
-system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.demand_accesses 500019 # number of demand (read+write) accesses
-system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits
-system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu3.icache.fast_writes 0 # number of fast writes performed
-system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses
-system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu3.icache.overall_hits 499556 # number of overall hits
-system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu3.icache.overall_misses 463 # number of overall misses
-system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu3.icache.replacements 152 # number of replacements
-system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks.
-system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.writebacks 0 # number of writebacks
-system.cpu3.idle_fraction 0 # Percentage of idle cycles
-system.cpu3.itb.accesses 500032 # ITB accesses
-system.cpu3.itb.acv 0 # ITB acv
-system.cpu3.itb.hits 500019 # ITB hits
-system.cpu3.itb.misses 13 # ITB misses
-system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu3.numCycles 500032 # number of cpu cycles simulated
-system.cpu3.num_insts 500001 # Number of instructions executed
-system.cpu3.num_refs 182222 # Number of memory references
-system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
-system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 556 # number of ReadExReq misses
-system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits 276 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 2872 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses
-system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 116 # number of Writeback hits
-system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 0.120000 # Average number of references to valid blocks.
-system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 3704 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 0 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.l2c.demand_hits 276 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses
-system.l2c.demand_misses 3428 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 3704 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 0 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.l2c.overall_hits 276 # number of overall hits
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses
-system.l2c.overall_misses 3428 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 2300 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 1529.374598 # Cycle average of tags in use
-system.l2c.total_refs 276 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 0 # number of writebacks
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-atomic-mp
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+>>>>Exiting @ tick 250015500 because a thread reached the max instruction count
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 2958551 # Simulator instruction rate (inst/s)
+host_mem_usage 1121980 # Number of bytes of host memory used
+host_seconds 0.68 # Real time elapsed on the host
+host_tick_rate 369689554 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 2000004 # Number of instructions simulated
+sim_seconds 0.000250 # Number of seconds simulated
+sim_ticks 250015500 # Number of ticks simulated
+system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
+system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_hits 180140 # number of overall hits
+system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 635 # number of overall misses
+system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.dcache.replacements 61 # number of replacements
+system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.writebacks 29 # number of writebacks
+system.cpu0.dtb.accesses 180793 # DTB accesses
+system.cpu0.dtb.acv 0 # DTB access violations
+system.cpu0.dtb.hits 180775 # DTB hits
+system.cpu0.dtb.misses 18 # DTB misses
+system.cpu0.dtb.read_accesses 124443 # DTB read accesses
+system.cpu0.dtb.read_acv 0 # DTB read access violations
+system.cpu0.dtb.read_hits 124435 # DTB read hits
+system.cpu0.dtb.read_misses 8 # DTB read misses
+system.cpu0.dtb.write_accesses 56350 # DTB write accesses
+system.cpu0.dtb.write_acv 0 # DTB write access violations
+system.cpu0.dtb.write_hits 56340 # DTB write hits
+system.cpu0.dtb.write_misses 10 # DTB write misses
+system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
+system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
+system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
+system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu0.icache.overall_hits 499556 # number of overall hits
+system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
+system.cpu0.icache.overall_misses 463 # number of overall misses
+system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.icache.replacements 152 # number of replacements
+system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use
+system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.writebacks 0 # number of writebacks
+system.cpu0.idle_fraction 0 # Percentage of idle cycles
+system.cpu0.itb.accesses 500032 # ITB accesses
+system.cpu0.itb.acv 0 # ITB acv
+system.cpu0.itb.hits 500019 # ITB hits
+system.cpu0.itb.misses 13 # ITB misses
+system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu0.numCycles 500032 # number of cpu cycles simulated
+system.cpu0.num_insts 500001 # Number of instructions executed
+system.cpu0.num_refs 182222 # Number of memory references
+system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_hits 56029 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
+system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu1.dcache.demand_hits 180140 # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
+system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_hits 180140 # number of overall hits
+system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
+system.cpu1.dcache.overall_misses 635 # number of overall misses
+system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.dcache.replacements 61 # number of replacements
+system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks 29 # number of writebacks
+system.cpu1.dtb.accesses 180793 # DTB accesses
+system.cpu1.dtb.acv 0 # DTB access violations
+system.cpu1.dtb.hits 180775 # DTB hits
+system.cpu1.dtb.misses 18 # DTB misses
+system.cpu1.dtb.read_accesses 124443 # DTB read accesses
+system.cpu1.dtb.read_acv 0 # DTB read access violations
+system.cpu1.dtb.read_hits 124435 # DTB read hits
+system.cpu1.dtb.read_misses 8 # DTB read misses
+system.cpu1.dtb.write_accesses 56350 # DTB write accesses
+system.cpu1.dtb.write_acv 0 # DTB write access violations
+system.cpu1.dtb.write_hits 56340 # DTB write hits
+system.cpu1.dtb.write_misses 10 # DTB write misses
+system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses
+system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
+system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
+system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu1.icache.overall_hits 499556 # number of overall hits
+system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
+system.cpu1.icache.overall_misses 463 # number of overall misses
+system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.icache.replacements 152 # number of replacements
+system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use
+system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.writebacks 0 # number of writebacks
+system.cpu1.idle_fraction 0 # Percentage of idle cycles
+system.cpu1.itb.accesses 500032 # ITB accesses
+system.cpu1.itb.acv 0 # ITB acv
+system.cpu1.itb.hits 500019 # ITB hits
+system.cpu1.itb.misses 13 # ITB misses
+system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu1.numCycles 500032 # number of cpu cycles simulated
+system.cpu1.num_insts 500001 # Number of instructions executed
+system.cpu1.num_refs 182222 # Number of memory references
+system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits
+system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
+system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits
+system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
+system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu2.dcache.cache_copies 0 # number of cache copies performed
+system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses
+system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits
+system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
+system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.fast_writes 0 # number of fast writes performed
+system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses
+system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu2.dcache.overall_hits 180140 # number of overall hits
+system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
+system.cpu2.dcache.overall_misses 635 # number of overall misses
+system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu2.dcache.replacements 61 # number of replacements
+system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use
+system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks.
+system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.writebacks 29 # number of writebacks
+system.cpu2.dtb.accesses 180793 # DTB accesses
+system.cpu2.dtb.acv 0 # DTB access violations
+system.cpu2.dtb.hits 180775 # DTB hits
+system.cpu2.dtb.misses 18 # DTB misses
+system.cpu2.dtb.read_accesses 124443 # DTB read accesses
+system.cpu2.dtb.read_acv 0 # DTB read access violations
+system.cpu2.dtb.read_hits 124435 # DTB read hits
+system.cpu2.dtb.read_misses 8 # DTB read misses
+system.cpu2.dtb.write_accesses 56350 # DTB write accesses
+system.cpu2.dtb.write_acv 0 # DTB write access violations
+system.cpu2.dtb.write_hits 56340 # DTB write hits
+system.cpu2.dtb.write_misses 10 # DTB write misses
+system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits
+system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses
+system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
+system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu2.icache.cache_copies 0 # number of cache copies performed
+system.cpu2.icache.demand_accesses 500019 # number of demand (read+write) accesses
+system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits
+system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
+system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
+system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu2.icache.fast_writes 0 # number of fast writes performed
+system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses
+system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu2.icache.overall_hits 499556 # number of overall hits
+system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
+system.cpu2.icache.overall_misses 463 # number of overall misses
+system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu2.icache.replacements 152 # number of replacements
+system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use
+system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks.
+system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu2.icache.writebacks 0 # number of writebacks
+system.cpu2.idle_fraction 0 # Percentage of idle cycles
+system.cpu2.itb.accesses 500032 # ITB accesses
+system.cpu2.itb.acv 0 # ITB acv
+system.cpu2.itb.hits 500019 # ITB hits
+system.cpu2.itb.misses 13 # ITB misses
+system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu2.numCycles 500032 # number of cpu cycles simulated
+system.cpu2.num_insts 500001 # Number of instructions executed
+system.cpu2.num_refs 182222 # Number of memory references
+system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits
+system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
+system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_hits 56029 # number of WriteReq hits
+system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
+system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu3.dcache.cache_copies 0 # number of cache copies performed
+system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses
+system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu3.dcache.demand_hits 180140 # number of demand (read+write) hits
+system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
+system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu3.dcache.fast_writes 0 # number of fast writes performed
+system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses
+system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu3.dcache.overall_hits 180140 # number of overall hits
+system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
+system.cpu3.dcache.overall_misses 635 # number of overall misses
+system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu3.dcache.replacements 61 # number of replacements
+system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use
+system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks.
+system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.writebacks 29 # number of writebacks
+system.cpu3.dtb.accesses 180793 # DTB accesses
+system.cpu3.dtb.acv 0 # DTB access violations
+system.cpu3.dtb.hits 180775 # DTB hits
+system.cpu3.dtb.misses 18 # DTB misses
+system.cpu3.dtb.read_accesses 124443 # DTB read accesses
+system.cpu3.dtb.read_acv 0 # DTB read access violations
+system.cpu3.dtb.read_hits 124435 # DTB read hits
+system.cpu3.dtb.read_misses 8 # DTB read misses
+system.cpu3.dtb.write_accesses 56350 # DTB write accesses
+system.cpu3.dtb.write_acv 0 # DTB write access violations
+system.cpu3.dtb.write_hits 56340 # DTB write hits
+system.cpu3.dtb.write_misses 10 # DTB write misses
+system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits
+system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses
+system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
+system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu3.icache.cache_copies 0 # number of cache copies performed
+system.cpu3.icache.demand_accesses 500019 # number of demand (read+write) accesses
+system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits
+system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
+system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses
+system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.cpu3.icache.fast_writes 0 # number of fast writes performed
+system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses
+system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu3.icache.overall_hits 499556 # number of overall hits
+system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles
+system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
+system.cpu3.icache.overall_misses 463 # number of overall misses
+system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu3.icache.replacements 152 # number of replacements
+system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use
+system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks.
+system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.icache.writebacks 0 # number of writebacks
+system.cpu3.idle_fraction 0 # Percentage of idle cycles
+system.cpu3.itb.accesses 500032 # ITB accesses
+system.cpu3.itb.acv 0 # ITB acv
+system.cpu3.itb.hits 500019 # ITB hits
+system.cpu3.itb.misses 13 # ITB misses
+system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu3.numCycles 500032 # number of cpu cycles simulated
+system.cpu3.num_insts 500001 # Number of instructions executed
+system.cpu3.num_refs 182222 # Number of memory references
+system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
+system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 556 # number of ReadExReq misses
+system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits 276 # number of ReadReq hits
+system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 2872 # number of ReadReq misses
+system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses
+system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 116 # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_refs 0.120000 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.demand_accesses 3704 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 0 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.l2c.demand_hits 276 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses
+system.l2c.demand_misses 3428 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.overall_accesses 3704 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 0 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.l2c.overall_hits 276 # number of overall hits
+system.l2c.overall_miss_latency 0 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses
+system.l2c.overall_misses 3428 # number of overall misses
+system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements 0 # number of replacements
+system.l2c.sampled_refs 2300 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 1529.374598 # Cycle average of tags in use
+system.l2c.total_refs 276 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 0 # number of writebacks
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:45
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-atomic-mp
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
->>>>Exiting @ tick 250015500 because a thread reached the max instruction count
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1370296 # Simulator instruction rate (inst/s)
-host_mem_usage 204468 # Number of bytes of host memory used
-host_seconds 1.46 # Real time elapsed on the host
-host_tick_rate 505820394 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1999941 # Number of instructions simulated
-sim_seconds 0.000738 # Number of seconds simulated
-sim_ticks 738387000 # Number of ticks simulated
-system.cpu0.dcache.ReadReq_accesses 124432 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 54932.098765 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51932.098765 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_hits 124108 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 17798000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 16826000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_hits 56028 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
-system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 389.434125 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 180771 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 180136 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 35230000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 33325000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 180771 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 180136 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 35230000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 635 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 33325000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.dcache.replacements 61 # number of replacements
-system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 272.914158 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 180308 # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 29 # number of writebacks
-system.cpu0.dtb.accesses 180789 # DTB accesses
-system.cpu0.dtb.acv 0 # DTB access violations
-system.cpu0.dtb.hits 180771 # DTB hits
-system.cpu0.dtb.misses 18 # DTB misses
-system.cpu0.dtb.read_accesses 124440 # DTB read accesses
-system.cpu0.dtb.read_acv 0 # DTB read access violations
-system.cpu0.dtb.read_hits 124432 # DTB read hits
-system.cpu0.dtb.read_misses 8 # DTB read misses
-system.cpu0.dtb.write_accesses 56349 # DTB write accesses
-system.cpu0.dtb.write_acv 0 # DTB write access violations
-system.cpu0.dtb.write_hits 56339 # DTB write hits
-system.cpu0.dtb.write_misses 10 # DTB write misses
-system.cpu0.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 50723.542117 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47723.542117 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits 499537 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 23485000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
-system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 1078.913607 # Average number of references to valid blocks.
-system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 500000 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency
-system.cpu0.icache.demand_hits 499537 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 23485000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 22096000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses 500000 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 499537 # number of overall hits
-system.cpu0.icache.overall_miss_latency 23485000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 463 # number of overall misses
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 22096000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.icache.replacements 152 # number of replacements
-system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 215.953225 # Cycle average of tags in use
-system.cpu0.icache.total_refs 499537 # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idle_fraction 0 # Percentage of idle cycles
-system.cpu0.itb.accesses 500013 # ITB accesses
-system.cpu0.itb.acv 0 # ITB acv
-system.cpu0.itb.hits 500000 # ITB hits
-system.cpu0.itb.misses 13 # ITB misses
-system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu0.numCycles 1476774 # number of cpu cycles simulated
-system.cpu0.num_insts 499981 # Number of instructions executed
-system.cpu0.num_refs 182218 # Number of memory references
-system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu1.dcache.ReadReq_accesses 124429 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_hits 124105 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 56041.800643 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53041.800643 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_hits 56028 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 17429000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
-system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 389.427646 # Average number of references to valid blocks.
-system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 180768 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 180133 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 35220000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 33315000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.overall_accesses 180768 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 180133 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 35220000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 635 # number of overall misses
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 33315000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses 635 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.dcache.replacements 61 # number of replacements
-system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 272.910830 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 180305 # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 29 # number of writebacks
-system.cpu1.dtb.accesses 180786 # DTB accesses
-system.cpu1.dtb.acv 0 # DTB access violations
-system.cpu1.dtb.hits 180768 # DTB hits
-system.cpu1.dtb.misses 18 # DTB misses
-system.cpu1.dtb.read_accesses 124437 # DTB read accesses
-system.cpu1.dtb.read_acv 0 # DTB read access violations
-system.cpu1.dtb.read_hits 124429 # DTB read hits
-system.cpu1.dtb.read_misses 8 # DTB read misses
-system.cpu1.dtb.write_accesses 56349 # DTB write accesses
-system.cpu1.dtb.write_acv 0 # DTB write access violations
-system.cpu1.dtb.write_hits 56339 # DTB write hits
-system.cpu1.dtb.write_misses 10 # DTB write misses
-system.cpu1.icache.ReadReq_accesses 499994 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency 50764.578834 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47764.578834 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits 499531 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency 23504000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
-system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 1078.900648 # Average number of references to valid blocks.
-system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses 499994 # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency
-system.cpu1.icache.demand_hits 499531 # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency 23504000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 22115000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.overall_accesses 499994 # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits 499531 # number of overall hits
-system.cpu1.icache.overall_miss_latency 23504000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu1.icache.overall_misses 463 # number of overall misses
-system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.icache.replacements 152 # number of replacements
-system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 215.951034 # Cycle average of tags in use
-system.cpu1.icache.total_refs 499531 # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.idle_fraction 0 # Percentage of idle cycles
-system.cpu1.itb.accesses 500007 # ITB accesses
-system.cpu1.itb.acv 0 # ITB acv
-system.cpu1.itb.hits 499994 # ITB hits
-system.cpu1.itb.misses 13 # ITB misses
-system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu1.numCycles 1476774 # number of cpu cycles simulated
-system.cpu1.num_insts 499975 # Number of instructions executed
-system.cpu1.num_refs 182214 # Number of memory references
-system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
-system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency
-system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits
-system.cpu2.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses
-system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.fast_writes 0 # number of fast writes performed
-system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu2.dcache.overall_hits 180140 # number of overall hits
-system.cpu2.dcache.overall_miss_latency 35212000 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu2.dcache.overall_misses 635 # number of overall misses
-system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_misses 635 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu2.dcache.replacements 61 # number of replacements
-system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.dcache.tagsinuse 272.921161 # Cycle average of tags in use
-system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks.
-system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.writebacks 29 # number of writebacks
-system.cpu2.dtb.accesses 180793 # DTB accesses
-system.cpu2.dtb.acv 0 # DTB access violations
-system.cpu2.dtb.hits 180775 # DTB hits
-system.cpu2.dtb.misses 18 # DTB misses
-system.cpu2.dtb.read_accesses 124443 # DTB read accesses
-system.cpu2.dtb.read_acv 0 # DTB read access violations
-system.cpu2.dtb.read_hits 124435 # DTB read hits
-system.cpu2.dtb.read_misses 8 # DTB read misses
-system.cpu2.dtb.write_accesses 56350 # DTB write accesses
-system.cpu2.dtb.write_acv 0 # DTB write access violations
-system.cpu2.dtb.write_hits 56340 # DTB write hits
-system.cpu2.dtb.write_misses 10 # DTB write misses
-system.cpu2.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_hits 499557 # number of ReadReq hits
-system.cpu2.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu2.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
-system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu2.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
-system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.demand_accesses 500020 # number of demand (read+write) accesses
-system.cpu2.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency
-system.cpu2.icache.demand_hits 499557 # number of demand (read+write) hits
-system.cpu2.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu2.icache.fast_writes 0 # number of fast writes performed
-system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.icache.overall_accesses 500020 # number of overall (read+write) accesses
-system.cpu2.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu2.icache.overall_hits 499557 # number of overall hits
-system.cpu2.icache.overall_miss_latency 23479000 # number of overall miss cycles
-system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu2.icache.overall_misses 463 # number of overall misses
-system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu2.icache.replacements 152 # number of replacements
-system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.icache.tagsinuse 215.959580 # Cycle average of tags in use
-system.cpu2.icache.total_refs 499557 # Total number of references to valid blocks.
-system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.writebacks 0 # number of writebacks
-system.cpu2.idle_fraction 0 # Percentage of idle cycles
-system.cpu2.itb.accesses 500033 # ITB accesses
-system.cpu2.itb.acv 0 # ITB acv
-system.cpu2.itb.hits 500020 # ITB hits
-system.cpu2.itb.misses 13 # ITB misses
-system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu2.numCycles 1476774 # number of cpu cycles simulated
-system.cpu2.num_insts 500001 # Number of instructions executed
-system.cpu2.num_refs 182222 # Number of memory references
-system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu3.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_hits 124109 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_hits 56028 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu3.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
-system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu3.dcache.avg_refs 389.436285 # Average number of references to valid blocks.
-system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.cache_copies 0 # number of cache copies performed
-system.cpu3.dcache.demand_accesses 180772 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency
-system.cpu3.dcache.demand_hits 180137 # number of demand (read+write) hits
-system.cpu3.dcache.demand_miss_latency 35229000 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses
-system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_miss_latency 33324000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.fast_writes 0 # number of fast writes performed
-system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dcache.overall_accesses 180772 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu3.dcache.overall_hits 180137 # number of overall hits
-system.cpu3.dcache.overall_miss_latency 35229000 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu3.dcache.overall_misses 635 # number of overall misses
-system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_miss_latency 33324000 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_misses 635 # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu3.dcache.replacements 61 # number of replacements
-system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.dcache.tagsinuse 272.916356 # Cycle average of tags in use
-system.cpu3.dcache.total_refs 180309 # Total number of references to valid blocks.
-system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.writebacks 29 # number of writebacks
-system.cpu3.dtb.accesses 180790 # DTB accesses
-system.cpu3.dtb.acv 0 # DTB access violations
-system.cpu3.dtb.hits 180772 # DTB hits
-system.cpu3.dtb.misses 18 # DTB misses
-system.cpu3.dtb.read_accesses 124441 # DTB read accesses
-system.cpu3.dtb.read_acv 0 # DTB read access violations
-system.cpu3.dtb.read_hits 124433 # DTB read hits
-system.cpu3.dtb.read_misses 8 # DTB read misses
-system.cpu3.dtb.write_accesses 56349 # DTB write accesses
-system.cpu3.dtb.write_acv 0 # DTB write access violations
-system.cpu3.dtb.write_hits 56339 # DTB write hits
-system.cpu3.dtb.write_misses 10 # DTB write misses
-system.cpu3.icache.ReadReq_accesses 500003 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_avg_miss_latency 50717.062635 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47717.062635 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_hits 499540 # number of ReadReq hits
-system.cpu3.icache.ReadReq_miss_latency 23482000 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu3.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
-system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu3.icache.avg_refs 1078.920086 # Average number of references to valid blocks.
-system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.demand_accesses 500003 # number of demand (read+write) accesses
-system.cpu3.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency
-system.cpu3.icache.demand_hits 499540 # number of demand (read+write) hits
-system.cpu3.icache.demand_miss_latency 23482000 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_miss_latency 22093000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu3.icache.fast_writes 0 # number of fast writes performed
-system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.overall_accesses 500003 # number of overall (read+write) accesses
-system.cpu3.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu3.icache.overall_hits 499540 # number of overall hits
-system.cpu3.icache.overall_miss_latency 23482000 # number of overall miss cycles
-system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu3.icache.overall_misses 463 # number of overall misses
-system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_miss_latency 22093000 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu3.icache.replacements 152 # number of replacements
-system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.icache.tagsinuse 215.955045 # Cycle average of tags in use
-system.cpu3.icache.total_refs 499540 # Total number of references to valid blocks.
-system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.writebacks 0 # number of writebacks
-system.cpu3.idle_fraction 0 # Percentage of idle cycles
-system.cpu3.itb.accesses 500016 # ITB accesses
-system.cpu3.itb.acv 0 # ITB acv
-system.cpu3.itb.hits 500003 # ITB hits
-system.cpu3.itb.misses 13 # ITB misses
-system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu3.numCycles 1476774 # number of cpu cycles simulated
-system.cpu3.num_insts 499984 # Number of instructions executed
-system.cpu3.num_refs 182219 # Number of memory references
-system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
-system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 52008.992806 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40008.992806 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 28917000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 556 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 22245000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 52008.008357 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40008.008357 # average ReadReq mshr miss latency
-system.l2c.ReadReq_hits 276 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 149367000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 2872 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 114903000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.912325 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 52001.453488 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.453488 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 35777000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 27521000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 688 # number of UpgradeReq MSHR misses
-system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 116 # number of Writeback hits
-system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 0.120000 # Average number of references to valid blocks.
-system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 3704 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 52008.168028 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency
-system.l2c.demand_hits 276 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 178284000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses
-system.l2c.demand_misses 3428 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 137148000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.925486 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 3428 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 3704 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 52008.168028 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.l2c.overall_hits 276 # number of overall hits
-system.l2c.overall_miss_latency 178284000 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses
-system.l2c.overall_misses 3428 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 137148000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.925486 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 2300 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 1511.572121 # Cycle average of tags in use
-system.l2c.total_refs 276 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 0 # number of writebacks
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:30:50
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-timing-mp
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+main dictionary has 1245 entries
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+49508 bytes wasted
+>>>>Exiting @ tick 738387000 because a thread reached the max instruction count
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1370296 # Simulator instruction rate (inst/s)
+host_mem_usage 204468 # Number of bytes of host memory used
+host_seconds 1.46 # Real time elapsed on the host
+host_tick_rate 505820394 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1999941 # Number of instructions simulated
+sim_seconds 0.000738 # Number of seconds simulated
+sim_ticks 738387000 # Number of ticks simulated
+system.cpu0.dcache.ReadReq_accesses 124432 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency 54932.098765 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51932.098765 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_hits 124108 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 17798000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency 16826000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_hits 56028 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
+system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu0.dcache.avg_refs 389.434125 # Average number of references to valid blocks.
+system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.demand_accesses 180771 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits 180136 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 35230000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency 33325000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.overall_accesses 180771 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_hits 180136 # number of overall hits
+system.cpu0.dcache.overall_miss_latency 35230000 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 635 # number of overall misses
+system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency 33325000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.dcache.replacements 61 # number of replacements
+system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.tagsinuse 272.914158 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 180308 # Total number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.writebacks 29 # number of writebacks
+system.cpu0.dtb.accesses 180789 # DTB accesses
+system.cpu0.dtb.acv 0 # DTB access violations
+system.cpu0.dtb.hits 180771 # DTB hits
+system.cpu0.dtb.misses 18 # DTB misses
+system.cpu0.dtb.read_accesses 124440 # DTB read accesses
+system.cpu0.dtb.read_acv 0 # DTB read access violations
+system.cpu0.dtb.read_hits 124432 # DTB read hits
+system.cpu0.dtb.read_misses 8 # DTB read misses
+system.cpu0.dtb.write_accesses 56349 # DTB write accesses
+system.cpu0.dtb.write_acv 0 # DTB write access violations
+system.cpu0.dtb.write_hits 56339 # DTB write hits
+system.cpu0.dtb.write_misses 10 # DTB write misses
+system.cpu0.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency 50723.542117 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47723.542117 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits 499537 # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency 23485000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
+system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu0.icache.avg_refs 1078.913607 # Average number of references to valid blocks.
+system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.demand_accesses 500000 # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency
+system.cpu0.icache.demand_hits 499537 # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency 23485000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
+system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency 22096000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.icache.overall_accesses 500000 # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu0.icache.overall_hits 499537 # number of overall hits
+system.cpu0.icache.overall_miss_latency 23485000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
+system.cpu0.icache.overall_misses 463 # number of overall misses
+system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency 22096000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.icache.replacements 152 # number of replacements
+system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.tagsinuse 215.953225 # Cycle average of tags in use
+system.cpu0.icache.total_refs 499537 # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.writebacks 0 # number of writebacks
+system.cpu0.idle_fraction 0 # Percentage of idle cycles
+system.cpu0.itb.accesses 500013 # ITB accesses
+system.cpu0.itb.acv 0 # ITB acv
+system.cpu0.itb.hits 500000 # ITB hits
+system.cpu0.itb.misses 13 # ITB misses
+system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu0.numCycles 1476774 # number of cpu cycles simulated
+system.cpu0.num_insts 499981 # Number of instructions executed
+system.cpu0.num_refs 182218 # Number of memory references
+system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu1.dcache.ReadReq_accesses 124429 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_hits 124105 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency 56041.800643 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53041.800643 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_hits 56028 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency 17429000 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
+system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu1.dcache.avg_refs 389.427646 # Average number of references to valid blocks.
+system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.demand_accesses 180768 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency
+system.cpu1.dcache.demand_hits 180133 # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency 35220000 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
+system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency 33315000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.overall_accesses 180768 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_hits 180133 # number of overall hits
+system.cpu1.dcache.overall_miss_latency 35220000 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
+system.cpu1.dcache.overall_misses 635 # number of overall misses
+system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency 33315000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses 635 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.dcache.replacements 61 # number of replacements
+system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.tagsinuse 272.910830 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 180305 # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks 29 # number of writebacks
+system.cpu1.dtb.accesses 180786 # DTB accesses
+system.cpu1.dtb.acv 0 # DTB access violations
+system.cpu1.dtb.hits 180768 # DTB hits
+system.cpu1.dtb.misses 18 # DTB misses
+system.cpu1.dtb.read_accesses 124437 # DTB read accesses
+system.cpu1.dtb.read_acv 0 # DTB read access violations
+system.cpu1.dtb.read_hits 124429 # DTB read hits
+system.cpu1.dtb.read_misses 8 # DTB read misses
+system.cpu1.dtb.write_accesses 56349 # DTB write accesses
+system.cpu1.dtb.write_acv 0 # DTB write access violations
+system.cpu1.dtb.write_hits 56339 # DTB write hits
+system.cpu1.dtb.write_misses 10 # DTB write misses
+system.cpu1.icache.ReadReq_accesses 499994 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency 50764.578834 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47764.578834 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits 499531 # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency 23504000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
+system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu1.icache.avg_refs 1078.900648 # Average number of references to valid blocks.
+system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.demand_accesses 499994 # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency
+system.cpu1.icache.demand_hits 499531 # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency 23504000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
+system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency 22115000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.overall_accesses 499994 # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu1.icache.overall_hits 499531 # number of overall hits
+system.cpu1.icache.overall_miss_latency 23504000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
+system.cpu1.icache.overall_misses 463 # number of overall misses
+system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.icache.replacements 152 # number of replacements
+system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.tagsinuse 215.951034 # Cycle average of tags in use
+system.cpu1.icache.total_refs 499531 # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.writebacks 0 # number of writebacks
+system.cpu1.idle_fraction 0 # Percentage of idle cycles
+system.cpu1.itb.accesses 500007 # ITB accesses
+system.cpu1.itb.acv 0 # ITB acv
+system.cpu1.itb.hits 499994 # ITB hits
+system.cpu1.itb.misses 13 # ITB misses
+system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu1.numCycles 1476774 # number of cpu cycles simulated
+system.cpu1.num_insts 499975 # Number of instructions executed
+system.cpu1.num_refs 182214 # Number of memory references
+system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits
+system.cpu2.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits
+system.cpu2.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu2.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
+system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
+system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu2.dcache.cache_copies 0 # number of cache copies performed
+system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses
+system.cpu2.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency
+system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits
+system.cpu2.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
+system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.fast_writes 0 # number of fast writes performed
+system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses
+system.cpu2.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu2.dcache.overall_hits 180140 # number of overall hits
+system.cpu2.dcache.overall_miss_latency 35212000 # number of overall miss cycles
+system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
+system.cpu2.dcache.overall_misses 635 # number of overall misses
+system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_misses 635 # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu2.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu2.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu2.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu2.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu2.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu2.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu2.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu2.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu2.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu2.dcache.replacements 61 # number of replacements
+system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.tagsinuse 272.921161 # Cycle average of tags in use
+system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks.
+system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.writebacks 29 # number of writebacks
+system.cpu2.dtb.accesses 180793 # DTB accesses
+system.cpu2.dtb.acv 0 # DTB access violations
+system.cpu2.dtb.hits 180775 # DTB hits
+system.cpu2.dtb.misses 18 # DTB misses
+system.cpu2.dtb.read_accesses 124443 # DTB read accesses
+system.cpu2.dtb.read_acv 0 # DTB read access violations
+system.cpu2.dtb.read_hits 124435 # DTB read hits
+system.cpu2.dtb.read_misses 8 # DTB read misses
+system.cpu2.dtb.write_accesses 56350 # DTB write accesses
+system.cpu2.dtb.write_acv 0 # DTB write access violations
+system.cpu2.dtb.write_hits 56340 # DTB write hits
+system.cpu2.dtb.write_misses 10 # DTB write misses
+system.cpu2.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_hits 499557 # number of ReadReq hits
+system.cpu2.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses
+system.cpu2.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
+system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu2.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
+system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu2.icache.cache_copies 0 # number of cache copies performed
+system.cpu2.icache.demand_accesses 500020 # number of demand (read+write) accesses
+system.cpu2.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency
+system.cpu2.icache.demand_hits 499557 # number of demand (read+write) hits
+system.cpu2.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
+system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
+system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
+system.cpu2.icache.fast_writes 0 # number of fast writes performed
+system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.icache.overall_accesses 500020 # number of overall (read+write) accesses
+system.cpu2.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu2.icache.overall_hits 499557 # number of overall hits
+system.cpu2.icache.overall_miss_latency 23479000 # number of overall miss cycles
+system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
+system.cpu2.icache.overall_misses 463 # number of overall misses
+system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu2.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu2.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu2.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu2.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu2.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu2.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu2.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu2.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu2.icache.replacements 152 # number of replacements
+system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu2.icache.tagsinuse 215.959580 # Cycle average of tags in use
+system.cpu2.icache.total_refs 499557 # Total number of references to valid blocks.
+system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu2.icache.writebacks 0 # number of writebacks
+system.cpu2.idle_fraction 0 # Percentage of idle cycles
+system.cpu2.itb.accesses 500033 # ITB accesses
+system.cpu2.itb.acv 0 # ITB acv
+system.cpu2.itb.hits 500020 # ITB hits
+system.cpu2.itb.misses 13 # ITB misses
+system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu2.numCycles 1476774 # number of cpu cycles simulated
+system.cpu2.num_insts 500001 # Number of instructions executed
+system.cpu2.num_refs 182222 # Number of memory references
+system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu3.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_hits 124109 # number of ReadReq hits
+system.cpu3.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_hits 56028 # number of WriteReq hits
+system.cpu3.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu3.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
+system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu3.dcache.avg_refs 389.436285 # Average number of references to valid blocks.
+system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu3.dcache.cache_copies 0 # number of cache copies performed
+system.cpu3.dcache.demand_accesses 180772 # number of demand (read+write) accesses
+system.cpu3.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency
+system.cpu3.dcache.demand_hits 180137 # number of demand (read+write) hits
+system.cpu3.dcache.demand_miss_latency 35229000 # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
+system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_miss_latency 33324000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
+system.cpu3.dcache.fast_writes 0 # number of fast writes performed
+system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.dcache.overall_accesses 180772 # number of overall (read+write) accesses
+system.cpu3.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu3.dcache.overall_hits 180137 # number of overall hits
+system.cpu3.dcache.overall_miss_latency 35229000 # number of overall miss cycles
+system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
+system.cpu3.dcache.overall_misses 635 # number of overall misses
+system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_miss_latency 33324000 # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_misses 635 # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu3.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu3.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu3.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu3.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu3.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu3.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu3.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu3.dcache.replacements 61 # number of replacements
+system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu3.dcache.tagsinuse 272.916356 # Cycle average of tags in use
+system.cpu3.dcache.total_refs 180309 # Total number of references to valid blocks.
+system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.writebacks 29 # number of writebacks
+system.cpu3.dtb.accesses 180790 # DTB accesses
+system.cpu3.dtb.acv 0 # DTB access violations
+system.cpu3.dtb.hits 180772 # DTB hits
+system.cpu3.dtb.misses 18 # DTB misses
+system.cpu3.dtb.read_accesses 124441 # DTB read accesses
+system.cpu3.dtb.read_acv 0 # DTB read access violations
+system.cpu3.dtb.read_hits 124433 # DTB read hits
+system.cpu3.dtb.read_misses 8 # DTB read misses
+system.cpu3.dtb.write_accesses 56349 # DTB write accesses
+system.cpu3.dtb.write_acv 0 # DTB write access violations
+system.cpu3.dtb.write_hits 56339 # DTB write hits
+system.cpu3.dtb.write_misses 10 # DTB write misses
+system.cpu3.icache.ReadReq_accesses 500003 # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_avg_miss_latency 50717.062635 # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47717.062635 # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_hits 499540 # number of ReadReq hits
+system.cpu3.icache.ReadReq_miss_latency 23482000 # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses
+system.cpu3.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
+system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu3.icache.avg_refs 1078.920086 # Average number of references to valid blocks.
+system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu3.icache.cache_copies 0 # number of cache copies performed
+system.cpu3.icache.demand_accesses 500003 # number of demand (read+write) accesses
+system.cpu3.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency
+system.cpu3.icache.demand_hits 499540 # number of demand (read+write) hits
+system.cpu3.icache.demand_miss_latency 23482000 # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
+system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses
+system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_miss_latency 22093000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
+system.cpu3.icache.fast_writes 0 # number of fast writes performed
+system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.icache.overall_accesses 500003 # number of overall (read+write) accesses
+system.cpu3.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu3.icache.overall_hits 499540 # number of overall hits
+system.cpu3.icache.overall_miss_latency 23482000 # number of overall miss cycles
+system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
+system.cpu3.icache.overall_misses 463 # number of overall misses
+system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_miss_latency 22093000 # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu3.icache.replacements 152 # number of replacements
+system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
+system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu3.icache.tagsinuse 215.955045 # Cycle average of tags in use
+system.cpu3.icache.total_refs 499540 # Total number of references to valid blocks.
+system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.icache.writebacks 0 # number of writebacks
+system.cpu3.idle_fraction 0 # Percentage of idle cycles
+system.cpu3.itb.accesses 500016 # ITB accesses
+system.cpu3.itb.acv 0 # ITB acv
+system.cpu3.itb.hits 500003 # ITB hits
+system.cpu3.itb.misses 13 # ITB misses
+system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu3.numCycles 1476774 # number of cpu cycles simulated
+system.cpu3.num_insts 499984 # Number of instructions executed
+system.cpu3.num_refs 182219 # Number of memory references
+system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
+system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 52008.992806 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40008.992806 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 28917000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 556 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 22245000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 52008.008357 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40008.008357 # average ReadReq mshr miss latency
+system.l2c.ReadReq_hits 276 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 149367000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 2872 # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency 114903000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.912325 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 52001.453488 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.453488 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 35777000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 27521000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 688 # number of UpgradeReq MSHR misses
+system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 116 # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_refs 0.120000 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.demand_accesses 3704 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 52008.168028 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency
+system.l2c.demand_hits 276 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 178284000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses
+system.l2c.demand_misses 3428 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 137148000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.925486 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 3428 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.overall_accesses 3704 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 52008.168028 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.l2c.overall_hits 276 # number of overall hits
+system.l2c.overall_miss_latency 178284000 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses
+system.l2c.overall_misses 3428 # number of overall misses
+system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 137148000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.925486 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements 0 # number of replacements
+system.l2c.sampled_refs 2300 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 1511.572121 # Cycle average of tags in use
+system.l2c.total_refs 276 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 0 # number of writebacks
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:30:50
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-timing-mp
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
->>>>Exiting @ tick 738387000 because a thread reached the max instruction count
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_mem_usage 324480 # Number of bytes of host memory used
-host_seconds 257.27 # Real time elapsed on the host
-host_tick_rate 1045249 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_seconds 0.000269 # Number of seconds simulated
-sim_ticks 268915439 # Number of ticks simulated
-system.cpu0.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_hits 7762 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_misses 37405 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_hits 912 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_misses 23362 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.avg_blocked_cycles_no_mshrs 3772.150399 # average number of cycles each access was blocked
-system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu0.l1c.avg_refs 0.412252 # Average number of references to valid blocks.
-system.cpu0.l1c.blocked_no_mshrs 69914 # number of cycles access was blocked
-system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles_no_mshrs 263726123 # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.demand_accesses 69441 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency
-system.cpu0.l1c.demand_hits 8674 # number of demand (read+write) hits
-system.cpu0.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses
-system.cpu0.l1c.demand_misses 60767 # number of demand (read+write) misses
-system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.fast_writes 0 # number of fast writes performed
-system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.l1c.overall_accesses 69441 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_hits 8674 # number of overall hits
-system.cpu0.l1c.overall_miss_latency 2449640896 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses
-system.cpu0.l1c.overall_misses 60767 # number of overall misses
-system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_misses 60767 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu0.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu0.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l1c.replacements 28158 # number of replacements
-system.cpu0.l1c.sampled_refs 28502 # Sample count of references to valid blocks.
-system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.l1c.tagsinuse 346.020042 # Cycle average of tags in use
-system.cpu0.l1c.total_refs 11750 # Total number of references to valid blocks.
-system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.writebacks 11054 # number of writebacks
-system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.num_reads 99578 # number of read accesses completed
-system.cpu0.num_writes 53795 # number of write accesses completed
-system.cpu1.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_hits 7617 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_misses 37080 # number of ReadReq misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_hits 934 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_misses 23370 # number of WriteReq misses
-system.cpu1.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.avg_blocked_cycles_no_mshrs 3775.982019 # average number of cycles each access was blocked
-system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu1.l1c.avg_refs 0.415709 # Average number of references to valid blocks.
-system.cpu1.l1c.blocked_no_mshrs 69517 # number of cycles access was blocked
-system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked_cycles_no_mshrs 262494942 # number of cycles access was blocked
-system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.demand_accesses 69001 # number of demand (read+write) accesses
-system.cpu1.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency
-system.cpu1.l1c.demand_hits 8551 # number of demand (read+write) hits
-system.cpu1.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses
-system.cpu1.l1c.demand_misses 60450 # number of demand (read+write) misses
-system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.fast_writes 0 # number of fast writes performed
-system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.l1c.overall_accesses 69001 # number of overall (read+write) accesses
-system.cpu1.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_hits 8551 # number of overall hits
-system.cpu1.l1c.overall_miss_latency 2447852326 # number of overall miss cycles
-system.cpu1.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses
-system.cpu1.l1c.overall_misses 60450 # number of overall misses
-system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_misses 60450 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu1.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu1.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu1.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l1c.replacements 27563 # number of replacements
-system.cpu1.l1c.sampled_refs 27921 # Sample count of references to valid blocks.
-system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.l1c.tagsinuse 342.745179 # Cycle average of tags in use
-system.cpu1.l1c.total_refs 11607 # Total number of references to valid blocks.
-system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.writebacks 10923 # number of writebacks
-system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu1.num_reads 99680 # number of read accesses completed
-system.cpu1.num_writes 54175 # number of write accesses completed
-system.cpu2.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_hits 7547 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_misses 37391 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_hits 890 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_misses 23171 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.avg_blocked_cycles_no_mshrs 3785.643263 # average number of cycles each access was blocked
-system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu2.l1c.avg_refs 0.410349 # Average number of references to valid blocks.
-system.cpu2.l1c.blocked_no_mshrs 69704 # number of cycles access was blocked
-system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked_cycles_no_mshrs 263874478 # number of cycles access was blocked
-system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.demand_accesses 68999 # number of demand (read+write) accesses
-system.cpu2.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency
-system.cpu2.l1c.demand_hits 8437 # number of demand (read+write) hits
-system.cpu2.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses
-system.cpu2.l1c.demand_misses 60562 # number of demand (read+write) misses
-system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.fast_writes 0 # number of fast writes performed
-system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.l1c.overall_accesses 68999 # number of overall (read+write) accesses
-system.cpu2.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_hits 8437 # number of overall hits
-system.cpu2.l1c.overall_miss_latency 2458156635 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses
-system.cpu2.l1c.overall_misses 60562 # number of overall misses
-system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu2.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_misses 60562 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu2.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu2.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu2.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu2.l1c.replacements 27725 # number of replacements
-system.cpu2.l1c.sampled_refs 28081 # Sample count of references to valid blocks.
-system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.l1c.tagsinuse 346.450009 # Cycle average of tags in use
-system.cpu2.l1c.total_refs 11523 # Total number of references to valid blocks.
-system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.writebacks 10868 # number of writebacks
-system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.num_reads 99153 # number of read accesses completed
-system.cpu2.num_writes 52976 # number of write accesses completed
-system.cpu3.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_hits 7629 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_misses 37136 # number of ReadReq misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_hits 906 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_misses 23397 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.avg_blocked_cycles_no_mshrs 3780.086099 # average number of cycles each access was blocked
-system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu3.l1c.avg_refs 0.418843 # Average number of references to valid blocks.
-system.cpu3.l1c.blocked_no_mshrs 69350 # number of cycles access was blocked
-system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked_cycles_no_mshrs 262148971 # number of cycles access was blocked
-system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.demand_accesses 69068 # number of demand (read+write) accesses
-system.cpu3.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency
-system.cpu3.l1c.demand_hits 8535 # number of demand (read+write) hits
-system.cpu3.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses
-system.cpu3.l1c.demand_misses 60533 # number of demand (read+write) misses
-system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.fast_writes 0 # number of fast writes performed
-system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.l1c.overall_accesses 69068 # number of overall (read+write) accesses
-system.cpu3.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_hits 8535 # number of overall hits
-system.cpu3.l1c.overall_miss_latency 2459294321 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses
-system.cpu3.l1c.overall_misses 60533 # number of overall misses
-system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu3.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_misses 60533 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu3.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu3.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu3.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu3.l1c.replacements 27562 # number of replacements
-system.cpu3.l1c.sampled_refs 27915 # Sample count of references to valid blocks.
-system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.l1c.tagsinuse 345.337496 # Cycle average of tags in use
-system.cpu3.l1c.total_refs 11692 # Total number of references to valid blocks.
-system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.writebacks 10850 # number of writebacks
-system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.num_reads 99282 # number of read accesses completed
-system.cpu3.num_writes 53764 # number of write accesses completed
-system.cpu4.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_hits 7462 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_misses 37225 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_hits 973 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_misses 23193 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.avg_blocked_cycles_no_mshrs 3787.291600 # average number of cycles each access was blocked
-system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu4.l1c.avg_refs 0.411354 # Average number of references to valid blocks.
-system.cpu4.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked
-system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked_cycles_no_mshrs 263356896 # number of cycles access was blocked
-system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.demand_accesses 68853 # number of demand (read+write) accesses
-system.cpu4.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency
-system.cpu4.l1c.demand_hits 8435 # number of demand (read+write) hits
-system.cpu4.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses
-system.cpu4.l1c.demand_misses 60418 # number of demand (read+write) misses
-system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu4.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.fast_writes 0 # number of fast writes performed
-system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.l1c.overall_accesses 68853 # number of overall (read+write) accesses
-system.cpu4.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_hits 8435 # number of overall hits
-system.cpu4.l1c.overall_miss_latency 2449625152 # number of overall miss cycles
-system.cpu4.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses
-system.cpu4.l1c.overall_misses 60418 # number of overall misses
-system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu4.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_misses 60418 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu4.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu4.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu4.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu4.l1c.replacements 27721 # number of replacements
-system.cpu4.l1c.sampled_refs 28078 # Sample count of references to valid blocks.
-system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu4.l1c.tagsinuse 344.718702 # Cycle average of tags in use
-system.cpu4.l1c.total_refs 11550 # Total number of references to valid blocks.
-system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.writebacks 10846 # number of writebacks
-system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.num_reads 99301 # number of read accesses completed
-system.cpu4.num_writes 53586 # number of write accesses completed
-system.cpu5.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_hits 7472 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_misses 37075 # number of ReadReq misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_hits 890 # number of WriteReq hits
-system.cpu5.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_misses 23395 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.avg_blocked_cycles_no_mshrs 3783.632237 # average number of cycles each access was blocked
-system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu5.l1c.avg_refs 0.410620 # Average number of references to valid blocks.
-system.cpu5.l1c.blocked_no_mshrs 69474 # number of cycles access was blocked
-system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked_cycles_no_mshrs 262864066 # number of cycles access was blocked
-system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.demand_accesses 68832 # number of demand (read+write) accesses
-system.cpu5.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency
-system.cpu5.l1c.demand_hits 8362 # number of demand (read+write) hits
-system.cpu5.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses
-system.cpu5.l1c.demand_misses 60470 # number of demand (read+write) misses
-system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu5.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.fast_writes 0 # number of fast writes performed
-system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.l1c.overall_accesses 68832 # number of overall (read+write) accesses
-system.cpu5.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_hits 8362 # number of overall hits
-system.cpu5.l1c.overall_miss_latency 2452523238 # number of overall miss cycles
-system.cpu5.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses
-system.cpu5.l1c.overall_misses 60470 # number of overall misses
-system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu5.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_misses 60470 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu5.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu5.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu5.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu5.l1c.replacements 27632 # number of replacements
-system.cpu5.l1c.sampled_refs 27965 # Sample count of references to valid blocks.
-system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu5.l1c.tagsinuse 343.014216 # Cycle average of tags in use
-system.cpu5.l1c.total_refs 11483 # Total number of references to valid blocks.
-system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.writebacks 10950 # number of writebacks
-system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.num_reads 99024 # number of read accesses completed
-system.cpu5.num_writes 53903 # number of write accesses completed
-system.cpu6.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_hits 7473 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_misses 37586 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_hits 923 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_misses 23387 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.avg_blocked_cycles_no_mshrs 3751.801399 # average number of cycles each access was blocked
-system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu6.l1c.avg_refs 0.403583 # Average number of references to valid blocks.
-system.cpu6.l1c.blocked_no_mshrs 69894 # number of cycles access was blocked
-system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked_cycles_no_mshrs 262228407 # number of cycles access was blocked
-system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.demand_accesses 69369 # number of demand (read+write) accesses
-system.cpu6.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency
-system.cpu6.l1c.demand_hits 8396 # number of demand (read+write) hits
-system.cpu6.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses
-system.cpu6.l1c.demand_misses 60973 # number of demand (read+write) misses
-system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu6.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.fast_writes 0 # number of fast writes performed
-system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.l1c.overall_accesses 69369 # number of overall (read+write) accesses
-system.cpu6.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_hits 8396 # number of overall hits
-system.cpu6.l1c.overall_miss_latency 2453091767 # number of overall miss cycles
-system.cpu6.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses
-system.cpu6.l1c.overall_misses 60973 # number of overall misses
-system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu6.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_misses 60973 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu6.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu6.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu6.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu6.l1c.replacements 28139 # number of replacements
-system.cpu6.l1c.sampled_refs 28470 # Sample count of references to valid blocks.
-system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu6.l1c.tagsinuse 343.673683 # Cycle average of tags in use
-system.cpu6.l1c.total_refs 11490 # Total number of references to valid blocks.
-system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.writebacks 11130 # number of writebacks
-system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu6.num_reads 100000 # number of read accesses completed
-system.cpu6.num_writes 54239 # number of write accesses completed
-system.cpu7.l1c.ReadReq_accesses 44716 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_avg_miss_latency 35110.555319 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 34106.579783 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_hits 7559 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_miss_latency 1304602904 # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_rate 0.830955 # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_misses 37157 # number of ReadReq misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency 1267298185 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830955 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_misses 37157 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 815723673 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_accesses 24205 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_avg_miss_latency 49444.663145 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 48440.833956 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_hits 922 # number of WriteReq hits
-system.cpu7.l1c.WriteReq_miss_latency 1151220092 # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_rate 0.961909 # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_misses 23283 # number of WriteReq misses
-system.cpu7.l1c.WriteReq_mshr_miss_latency 1127847937 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_rate 0.961909 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_misses 23283 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 536405254 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.avg_blocked_cycles_no_mshrs 3782.889997 # average number of cycles each access was blocked
-system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu7.l1c.avg_refs 0.414017 # Average number of references to valid blocks.
-system.cpu7.l1c.blocked_no_mshrs 69498 # number of cycles access was blocked
-system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked_cycles_no_mshrs 262903289 # number of cycles access was blocked
-system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.demand_accesses 68921 # number of demand (read+write) accesses
-system.cpu7.l1c.demand_avg_miss_latency 40632.412244 # average overall miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency
-system.cpu7.l1c.demand_hits 8481 # number of demand (read+write) hits
-system.cpu7.l1c.demand_miss_latency 2455822996 # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_rate 0.876946 # miss rate for demand accesses
-system.cpu7.l1c.demand_misses 60440 # number of demand (read+write) misses
-system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu7.l1c.demand_mshr_miss_latency 2395146122 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_rate 0.876946 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_misses 60440 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.fast_writes 0 # number of fast writes performed
-system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.l1c.overall_accesses 68921 # number of overall (read+write) accesses
-system.cpu7.l1c.overall_avg_miss_latency 40632.412244 # average overall miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_hits 8481 # number of overall hits
-system.cpu7.l1c.overall_miss_latency 2455822996 # number of overall miss cycles
-system.cpu7.l1c.overall_miss_rate 0.876946 # miss rate for overall accesses
-system.cpu7.l1c.overall_misses 60440 # number of overall misses
-system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu7.l1c.overall_mshr_miss_latency 2395146122 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_rate 0.876946 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_misses 60440 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_uncacheable_latency 1352128927 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu7.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu7.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu7.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu7.l1c.replacements 27627 # number of replacements
-system.cpu7.l1c.sampled_refs 27994 # Sample count of references to valid blocks.
-system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu7.l1c.tagsinuse 345.707784 # Cycle average of tags in use
-system.cpu7.l1c.total_refs 11590 # Total number of references to valid blocks.
-system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.writebacks 10984 # number of writebacks
-system.cpu7.num_copies 0 # number of copy accesses completed
-system.cpu7.num_reads 99634 # number of read accesses completed
-system.cpu7.num_writes 53744 # number of write accesses completed
-system.l2c.ReadExReq_accesses 75142 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency 49861.980677 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 39995.605218 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 3746728952 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses 75142 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_hits 587 # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_miss_latency 2981872347 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate 0.992188 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 74555 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses 137922 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency 49640.109276 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 39996.564362 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits 89906 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 2383519487 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate 0.348139 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses 48016 # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits 1016 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 1879838525 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate 0.340772 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 47000 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 3163753169 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses 18428 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency 27998.751357 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 39992.012512 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 515960990 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses 18428 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_hits 45 # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_miss_latency 735173166 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate 0.997558 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 18383 # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1717039696 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses 86929 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits 86929 # number of Writeback hits
-system.l2c.avg_blocked_cycles_no_mshrs 7154.090909 # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.l2c.avg_refs 2.005630 # Average number of references to valid blocks.
-system.l2c.blocked_no_mshrs 11 # number of cycles access was blocked
-system.l2c.blocked_no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_mshrs 78695 # number of cycles access was blocked
-system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses 213064 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency 49775.478970 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency
-system.l2c.demand_hits 89906 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 6130248439 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate 0.578033 # miss rate for demand accesses
-system.l2c.demand_misses 123158 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 1603 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 4861710872 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate 0.570509 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 121555 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.overall_accesses 213064 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency 49775.478970 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits 89906 # number of overall hits
-system.l2c.overall_miss_latency 6130248439 # number of overall miss cycles
-system.l2c.overall_miss_rate 0.578033 # miss rate for overall accesses
-system.l2c.overall_misses 123158 # number of overall misses
-system.l2c.overall_mshr_hits 1603 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 4861710872 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate 0.570509 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 121555 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 4880792865 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements 73303 # number of replacements
-system.l2c.sampled_refs 73894 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 633.737828 # Cycle average of tags in use
-system.l2c.total_refs 148204 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 47216 # number of writebacks
-
----------- End Simulation Statistics ----------
--- /dev/null
+system.cpu3: completed 10000 read accesses @26226880
+system.cpu6: completed 10000 read accesses @26416342
+system.cpu2: completed 10000 read accesses @26427251
+system.cpu5: completed 10000 read accesses @26798889
+system.cpu0: completed 10000 read accesses @26886521
+system.cpu7: completed 10000 read accesses @27109446
+system.cpu1: completed 10000 read accesses @27197408
+system.cpu4: completed 10000 read accesses @27318359
+system.cpu3: completed 20000 read accesses @53279230
+system.cpu6: completed 20000 read accesses @53417084
+system.cpu2: completed 20000 read accesses @53757092
+system.cpu0: completed 20000 read accesses @53888320
+system.cpu5: completed 20000 read accesses @53947132
+system.cpu4: completed 20000 read accesses @54390092
+system.cpu1: completed 20000 read accesses @54397720
+system.cpu7: completed 20000 read accesses @54632966
+system.cpu6: completed 30000 read accesses @80144176
+system.cpu3: completed 30000 read accesses @80518264
+system.cpu0: completed 30000 read accesses @80638600
+system.cpu5: completed 30000 read accesses @80869702
+system.cpu1: completed 30000 read accesses @81289158
+system.cpu2: completed 30000 read accesses @81358716
+system.cpu7: completed 30000 read accesses @81981296
+system.cpu4: completed 30000 read accesses @82043104
+system.cpu6: completed 40000 read accesses @107087547
+system.cpu0: completed 40000 read accesses @107662142
+system.cpu3: completed 40000 read accesses @107722516
+system.cpu5: completed 40000 read accesses @107884124
+system.cpu1: completed 40000 read accesses @107981413
+system.cpu7: completed 40000 read accesses @108415286
+system.cpu2: completed 40000 read accesses @108655120
+system.cpu4: completed 40000 read accesses @109427858
+system.cpu6: completed 50000 read accesses @133583246
+system.cpu0: completed 50000 read accesses @133832383
+system.cpu5: completed 50000 read accesses @134755386
+system.cpu1: completed 50000 read accesses @134792594
+system.cpu7: completed 50000 read accesses @134914312
+system.cpu3: completed 50000 read accesses @134993978
+system.cpu2: completed 50000 read accesses @135362549
+system.cpu4: completed 50000 read accesses @135394370
+system.cpu0: completed 60000 read accesses @160410176
+system.cpu6: completed 60000 read accesses @160667590
+system.cpu7: completed 60000 read accesses @161466346
+system.cpu1: completed 60000 read accesses @161592434
+system.cpu5: completed 60000 read accesses @161656374
+system.cpu4: completed 60000 read accesses @161882626
+system.cpu2: completed 60000 read accesses @162062631
+system.cpu3: completed 60000 read accesses @162154299
+system.cpu6: completed 70000 read accesses @187592265
+system.cpu1: completed 70000 read accesses @188138542
+system.cpu7: completed 70000 read accesses @188373105
+system.cpu0: completed 70000 read accesses @188690782
+system.cpu3: completed 70000 read accesses @189309687
+system.cpu2: completed 70000 read accesses @189360790
+system.cpu4: completed 70000 read accesses @189391126
+system.cpu5: completed 70000 read accesses @189902895
+system.cpu6: completed 80000 read accesses @214739574
+system.cpu1: completed 80000 read accesses @215665444
+system.cpu0: completed 80000 read accesses @216021457
+system.cpu7: completed 80000 read accesses @216394344
+system.cpu3: completed 80000 read accesses @216537382
+system.cpu4: completed 80000 read accesses @216775798
+system.cpu2: completed 80000 read accesses @216868662
+system.cpu5: completed 80000 read accesses @217401619
+system.cpu6: completed 90000 read accesses @241415090
+system.cpu1: completed 90000 read accesses @242558992
+system.cpu0: completed 90000 read accesses @242897388
+system.cpu7: completed 90000 read accesses @243372191
+system.cpu3: completed 90000 read accesses @243630762
+system.cpu5: completed 90000 read accesses @243633950
+system.cpu4: completed 90000 read accesses @243710816
+system.cpu2: completed 90000 read accesses @243974160
+system.cpu6: completed 100000 read accesses @268915439
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re --stdout-file stdout --stderr-file stderr tests/run.py quick/50.memtest/alpha/linux/memtest
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 268915439 because maximum number of loads reached
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 324480 # Number of bytes of host memory used
+host_seconds 257.27 # Real time elapsed on the host
+host_tick_rate 1045249 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_seconds 0.000269 # Number of seconds simulated
+sim_ticks 268915439 # Number of ticks simulated
+system.cpu0.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_hits 7762 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_misses 37405 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_hits 912 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_misses 23362 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.avg_blocked_cycles_no_mshrs 3772.150399 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu0.l1c.avg_refs 0.412252 # Average number of references to valid blocks.
+system.cpu0.l1c.blocked_no_mshrs 69914 # number of cycles access was blocked
+system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles_no_mshrs 263726123 # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu0.l1c.cache_copies 0 # number of cache copies performed
+system.cpu0.l1c.demand_accesses 69441 # number of demand (read+write) accesses
+system.cpu0.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency
+system.cpu0.l1c.demand_hits 8674 # number of demand (read+write) hits
+system.cpu0.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses
+system.cpu0.l1c.demand_misses 60767 # number of demand (read+write) misses
+system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu0.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses
+system.cpu0.l1c.fast_writes 0 # number of fast writes performed
+system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.l1c.overall_accesses 69441 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_hits 8674 # number of overall hits
+system.cpu0.l1c.overall_miss_latency 2449640896 # number of overall miss cycles
+system.cpu0.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses
+system.cpu0.l1c.overall_misses 60767 # number of overall misses
+system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu0.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_misses 60767 # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu0.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu0.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.l1c.replacements 28158 # number of replacements
+system.cpu0.l1c.sampled_refs 28502 # Sample count of references to valid blocks.
+system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.l1c.tagsinuse 346.020042 # Cycle average of tags in use
+system.cpu0.l1c.total_refs 11750 # Total number of references to valid blocks.
+system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.l1c.writebacks 11054 # number of writebacks
+system.cpu0.num_copies 0 # number of copy accesses completed
+system.cpu0.num_reads 99578 # number of read accesses completed
+system.cpu0.num_writes 53795 # number of write accesses completed
+system.cpu1.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_hits 7617 # number of ReadReq hits
+system.cpu1.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_misses 37080 # number of ReadReq misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_hits 934 # number of WriteReq hits
+system.cpu1.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_misses 23370 # number of WriteReq misses
+system.cpu1.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.avg_blocked_cycles_no_mshrs 3775.982019 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu1.l1c.avg_refs 0.415709 # Average number of references to valid blocks.
+system.cpu1.l1c.blocked_no_mshrs 69517 # number of cycles access was blocked
+system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu1.l1c.blocked_cycles_no_mshrs 262494942 # number of cycles access was blocked
+system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu1.l1c.cache_copies 0 # number of cache copies performed
+system.cpu1.l1c.demand_accesses 69001 # number of demand (read+write) accesses
+system.cpu1.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency
+system.cpu1.l1c.demand_hits 8551 # number of demand (read+write) hits
+system.cpu1.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses
+system.cpu1.l1c.demand_misses 60450 # number of demand (read+write) misses
+system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses
+system.cpu1.l1c.fast_writes 0 # number of fast writes performed
+system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.l1c.overall_accesses 69001 # number of overall (read+write) accesses
+system.cpu1.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_hits 8551 # number of overall hits
+system.cpu1.l1c.overall_miss_latency 2447852326 # number of overall miss cycles
+system.cpu1.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses
+system.cpu1.l1c.overall_misses 60450 # number of overall misses
+system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_misses 60450 # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu1.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu1.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.l1c.replacements 27563 # number of replacements
+system.cpu1.l1c.sampled_refs 27921 # Sample count of references to valid blocks.
+system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.l1c.tagsinuse 342.745179 # Cycle average of tags in use
+system.cpu1.l1c.total_refs 11607 # Total number of references to valid blocks.
+system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.l1c.writebacks 10923 # number of writebacks
+system.cpu1.num_copies 0 # number of copy accesses completed
+system.cpu1.num_reads 99680 # number of read accesses completed
+system.cpu1.num_writes 54175 # number of write accesses completed
+system.cpu2.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_hits 7547 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_misses 37391 # number of ReadReq misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_hits 890 # number of WriteReq hits
+system.cpu2.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_misses 23171 # number of WriteReq misses
+system.cpu2.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.avg_blocked_cycles_no_mshrs 3785.643263 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu2.l1c.avg_refs 0.410349 # Average number of references to valid blocks.
+system.cpu2.l1c.blocked_no_mshrs 69704 # number of cycles access was blocked
+system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu2.l1c.blocked_cycles_no_mshrs 263874478 # number of cycles access was blocked
+system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu2.l1c.cache_copies 0 # number of cache copies performed
+system.cpu2.l1c.demand_accesses 68999 # number of demand (read+write) accesses
+system.cpu2.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency
+system.cpu2.l1c.demand_hits 8437 # number of demand (read+write) hits
+system.cpu2.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses
+system.cpu2.l1c.demand_misses 60562 # number of demand (read+write) misses
+system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu2.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses
+system.cpu2.l1c.fast_writes 0 # number of fast writes performed
+system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.l1c.overall_accesses 68999 # number of overall (read+write) accesses
+system.cpu2.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_hits 8437 # number of overall hits
+system.cpu2.l1c.overall_miss_latency 2458156635 # number of overall miss cycles
+system.cpu2.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses
+system.cpu2.l1c.overall_misses 60562 # number of overall misses
+system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu2.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_misses 60562 # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu2.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu2.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu2.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu2.l1c.replacements 27725 # number of replacements
+system.cpu2.l1c.sampled_refs 28081 # Sample count of references to valid blocks.
+system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu2.l1c.tagsinuse 346.450009 # Cycle average of tags in use
+system.cpu2.l1c.total_refs 11523 # Total number of references to valid blocks.
+system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu2.l1c.writebacks 10868 # number of writebacks
+system.cpu2.num_copies 0 # number of copy accesses completed
+system.cpu2.num_reads 99153 # number of read accesses completed
+system.cpu2.num_writes 52976 # number of write accesses completed
+system.cpu3.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.ReadReq_hits 7629 # number of ReadReq hits
+system.cpu3.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_misses 37136 # number of ReadReq misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_hits 906 # number of WriteReq hits
+system.cpu3.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_misses 23397 # number of WriteReq misses
+system.cpu3.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.avg_blocked_cycles_no_mshrs 3780.086099 # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu3.l1c.avg_refs 0.418843 # Average number of references to valid blocks.
+system.cpu3.l1c.blocked_no_mshrs 69350 # number of cycles access was blocked
+system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu3.l1c.blocked_cycles_no_mshrs 262148971 # number of cycles access was blocked
+system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu3.l1c.cache_copies 0 # number of cache copies performed
+system.cpu3.l1c.demand_accesses 69068 # number of demand (read+write) accesses
+system.cpu3.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency
+system.cpu3.l1c.demand_hits 8535 # number of demand (read+write) hits
+system.cpu3.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses
+system.cpu3.l1c.demand_misses 60533 # number of demand (read+write) misses
+system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu3.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses
+system.cpu3.l1c.fast_writes 0 # number of fast writes performed
+system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.l1c.overall_accesses 69068 # number of overall (read+write) accesses
+system.cpu3.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_hits 8535 # number of overall hits
+system.cpu3.l1c.overall_miss_latency 2459294321 # number of overall miss cycles
+system.cpu3.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses
+system.cpu3.l1c.overall_misses 60533 # number of overall misses
+system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu3.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_misses 60533 # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu3.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu3.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu3.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu3.l1c.replacements 27562 # number of replacements
+system.cpu3.l1c.sampled_refs 27915 # Sample count of references to valid blocks.
+system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu3.l1c.tagsinuse 345.337496 # Cycle average of tags in use
+system.cpu3.l1c.total_refs 11692 # Total number of references to valid blocks.
+system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.l1c.writebacks 10850 # number of writebacks
+system.cpu3.num_copies 0 # number of copy accesses completed
+system.cpu3.num_reads 99282 # number of read accesses completed
+system.cpu3.num_writes 53764 # number of write accesses completed
+system.cpu4.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_hits 7462 # number of ReadReq hits
+system.cpu4.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_misses 37225 # number of ReadReq misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_hits 973 # number of WriteReq hits
+system.cpu4.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_misses 23193 # number of WriteReq misses
+system.cpu4.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.avg_blocked_cycles_no_mshrs 3787.291600 # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu4.l1c.avg_refs 0.411354 # Average number of references to valid blocks.
+system.cpu4.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked
+system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu4.l1c.blocked_cycles_no_mshrs 263356896 # number of cycles access was blocked
+system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu4.l1c.cache_copies 0 # number of cache copies performed
+system.cpu4.l1c.demand_accesses 68853 # number of demand (read+write) accesses
+system.cpu4.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency
+system.cpu4.l1c.demand_hits 8435 # number of demand (read+write) hits
+system.cpu4.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses
+system.cpu4.l1c.demand_misses 60418 # number of demand (read+write) misses
+system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu4.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses
+system.cpu4.l1c.fast_writes 0 # number of fast writes performed
+system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu4.l1c.overall_accesses 68853 # number of overall (read+write) accesses
+system.cpu4.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_hits 8435 # number of overall hits
+system.cpu4.l1c.overall_miss_latency 2449625152 # number of overall miss cycles
+system.cpu4.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses
+system.cpu4.l1c.overall_misses 60418 # number of overall misses
+system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu4.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_misses 60418 # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu4.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu4.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu4.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu4.l1c.replacements 27721 # number of replacements
+system.cpu4.l1c.sampled_refs 28078 # Sample count of references to valid blocks.
+system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu4.l1c.tagsinuse 344.718702 # Cycle average of tags in use
+system.cpu4.l1c.total_refs 11550 # Total number of references to valid blocks.
+system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu4.l1c.writebacks 10846 # number of writebacks
+system.cpu4.num_copies 0 # number of copy accesses completed
+system.cpu4.num_reads 99301 # number of read accesses completed
+system.cpu4.num_writes 53586 # number of write accesses completed
+system.cpu5.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.ReadReq_hits 7472 # number of ReadReq hits
+system.cpu5.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_misses 37075 # number of ReadReq misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_hits 890 # number of WriteReq hits
+system.cpu5.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_misses 23395 # number of WriteReq misses
+system.cpu5.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.avg_blocked_cycles_no_mshrs 3783.632237 # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu5.l1c.avg_refs 0.410620 # Average number of references to valid blocks.
+system.cpu5.l1c.blocked_no_mshrs 69474 # number of cycles access was blocked
+system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu5.l1c.blocked_cycles_no_mshrs 262864066 # number of cycles access was blocked
+system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu5.l1c.cache_copies 0 # number of cache copies performed
+system.cpu5.l1c.demand_accesses 68832 # number of demand (read+write) accesses
+system.cpu5.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency
+system.cpu5.l1c.demand_hits 8362 # number of demand (read+write) hits
+system.cpu5.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses
+system.cpu5.l1c.demand_misses 60470 # number of demand (read+write) misses
+system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu5.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses
+system.cpu5.l1c.fast_writes 0 # number of fast writes performed
+system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu5.l1c.overall_accesses 68832 # number of overall (read+write) accesses
+system.cpu5.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_hits 8362 # number of overall hits
+system.cpu5.l1c.overall_miss_latency 2452523238 # number of overall miss cycles
+system.cpu5.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses
+system.cpu5.l1c.overall_misses 60470 # number of overall misses
+system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu5.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_misses 60470 # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu5.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu5.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu5.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu5.l1c.replacements 27632 # number of replacements
+system.cpu5.l1c.sampled_refs 27965 # Sample count of references to valid blocks.
+system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu5.l1c.tagsinuse 343.014216 # Cycle average of tags in use
+system.cpu5.l1c.total_refs 11483 # Total number of references to valid blocks.
+system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu5.l1c.writebacks 10950 # number of writebacks
+system.cpu5.num_copies 0 # number of copy accesses completed
+system.cpu5.num_reads 99024 # number of read accesses completed
+system.cpu5.num_writes 53903 # number of write accesses completed
+system.cpu6.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_hits 7473 # number of ReadReq hits
+system.cpu6.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_misses 37586 # number of ReadReq misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_hits 923 # number of WriteReq hits
+system.cpu6.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_misses 23387 # number of WriteReq misses
+system.cpu6.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.avg_blocked_cycles_no_mshrs 3751.801399 # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu6.l1c.avg_refs 0.403583 # Average number of references to valid blocks.
+system.cpu6.l1c.blocked_no_mshrs 69894 # number of cycles access was blocked
+system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu6.l1c.blocked_cycles_no_mshrs 262228407 # number of cycles access was blocked
+system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu6.l1c.cache_copies 0 # number of cache copies performed
+system.cpu6.l1c.demand_accesses 69369 # number of demand (read+write) accesses
+system.cpu6.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency
+system.cpu6.l1c.demand_hits 8396 # number of demand (read+write) hits
+system.cpu6.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses
+system.cpu6.l1c.demand_misses 60973 # number of demand (read+write) misses
+system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu6.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses
+system.cpu6.l1c.fast_writes 0 # number of fast writes performed
+system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu6.l1c.overall_accesses 69369 # number of overall (read+write) accesses
+system.cpu6.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_hits 8396 # number of overall hits
+system.cpu6.l1c.overall_miss_latency 2453091767 # number of overall miss cycles
+system.cpu6.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses
+system.cpu6.l1c.overall_misses 60973 # number of overall misses
+system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu6.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_misses 60973 # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu6.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu6.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu6.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu6.l1c.replacements 28139 # number of replacements
+system.cpu6.l1c.sampled_refs 28470 # Sample count of references to valid blocks.
+system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu6.l1c.tagsinuse 343.673683 # Cycle average of tags in use
+system.cpu6.l1c.total_refs 11490 # Total number of references to valid blocks.
+system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu6.l1c.writebacks 11130 # number of writebacks
+system.cpu6.num_copies 0 # number of copy accesses completed
+system.cpu6.num_reads 100000 # number of read accesses completed
+system.cpu6.num_writes 54239 # number of write accesses completed
+system.cpu7.l1c.ReadReq_accesses 44716 # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_avg_miss_latency 35110.555319 # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 34106.579783 # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.ReadReq_hits 7559 # number of ReadReq hits
+system.cpu7.l1c.ReadReq_miss_latency 1304602904 # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_rate 0.830955 # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_misses 37157 # number of ReadReq misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency 1267298185 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830955 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_misses 37157 # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 815723673 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_accesses 24205 # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_avg_miss_latency 49444.663145 # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 48440.833956 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_hits 922 # number of WriteReq hits
+system.cpu7.l1c.WriteReq_miss_latency 1151220092 # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_rate 0.961909 # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_misses 23283 # number of WriteReq misses
+system.cpu7.l1c.WriteReq_mshr_miss_latency 1127847937 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_rate 0.961909 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_misses 23283 # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 536405254 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.avg_blocked_cycles_no_mshrs 3782.889997 # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu7.l1c.avg_refs 0.414017 # Average number of references to valid blocks.
+system.cpu7.l1c.blocked_no_mshrs 69498 # number of cycles access was blocked
+system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu7.l1c.blocked_cycles_no_mshrs 262903289 # number of cycles access was blocked
+system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu7.l1c.cache_copies 0 # number of cache copies performed
+system.cpu7.l1c.demand_accesses 68921 # number of demand (read+write) accesses
+system.cpu7.l1c.demand_avg_miss_latency 40632.412244 # average overall miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency
+system.cpu7.l1c.demand_hits 8481 # number of demand (read+write) hits
+system.cpu7.l1c.demand_miss_latency 2455822996 # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_rate 0.876946 # miss rate for demand accesses
+system.cpu7.l1c.demand_misses 60440 # number of demand (read+write) misses
+system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu7.l1c.demand_mshr_miss_latency 2395146122 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_rate 0.876946 # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_misses 60440 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.fast_writes 0 # number of fast writes performed
+system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu7.l1c.overall_accesses 68921 # number of overall (read+write) accesses
+system.cpu7.l1c.overall_avg_miss_latency 40632.412244 # average overall miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_hits 8481 # number of overall hits
+system.cpu7.l1c.overall_miss_latency 2455822996 # number of overall miss cycles
+system.cpu7.l1c.overall_miss_rate 0.876946 # miss rate for overall accesses
+system.cpu7.l1c.overall_misses 60440 # number of overall misses
+system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu7.l1c.overall_mshr_miss_latency 2395146122 # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_rate 0.876946 # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_misses 60440 # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_uncacheable_latency 1352128927 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu7.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu7.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu7.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu7.l1c.replacements 27627 # number of replacements
+system.cpu7.l1c.sampled_refs 27994 # Sample count of references to valid blocks.
+system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu7.l1c.tagsinuse 345.707784 # Cycle average of tags in use
+system.cpu7.l1c.total_refs 11590 # Total number of references to valid blocks.
+system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu7.l1c.writebacks 10984 # number of writebacks
+system.cpu7.num_copies 0 # number of copy accesses completed
+system.cpu7.num_reads 99634 # number of read accesses completed
+system.cpu7.num_writes 53744 # number of write accesses completed
+system.l2c.ReadExReq_accesses 75142 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 49861.980677 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 39995.605218 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 3746728952 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 75142 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_hits 587 # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_miss_latency 2981872347 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 0.992188 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 74555 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 137922 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 49640.109276 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 39996.564362 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits 89906 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 2383519487 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.348139 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 48016 # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits 1016 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency 1879838525 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.340772 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 47000 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 3163753169 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses 18428 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency 27998.751357 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 39992.012512 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 515960990 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses 18428 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_hits 45 # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_miss_latency 735173166 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate 0.997558 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses 18383 # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency 1717039696 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses 86929 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits 86929 # number of Writeback hits
+system.l2c.avg_blocked_cycles_no_mshrs 7154.090909 # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_refs 2.005630 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 11 # number of cycles access was blocked
+system.l2c.blocked_no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 78695 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.demand_accesses 213064 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 49775.478970 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency
+system.l2c.demand_hits 89906 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 6130248439 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.578033 # miss rate for demand accesses
+system.l2c.demand_misses 123158 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 1603 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 4861710872 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.570509 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 121555 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.overall_accesses 213064 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 49775.478970 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
+system.l2c.overall_hits 89906 # number of overall hits
+system.l2c.overall_miss_latency 6130248439 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.578033 # miss rate for overall accesses
+system.l2c.overall_misses 123158 # number of overall misses
+system.l2c.overall_mshr_hits 1603 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 4861710872 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.570509 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 121555 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 4880792865 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements 73303 # number of replacements
+system.l2c.sampled_refs 73894 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 633.737828 # Cycle average of tags in use
+system.l2c.total_refs 148204 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 47216 # number of writebacks
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-system.cpu3: completed 10000 read accesses @26226880
-system.cpu6: completed 10000 read accesses @26416342
-system.cpu2: completed 10000 read accesses @26427251
-system.cpu5: completed 10000 read accesses @26798889
-system.cpu0: completed 10000 read accesses @26886521
-system.cpu7: completed 10000 read accesses @27109446
-system.cpu1: completed 10000 read accesses @27197408
-system.cpu4: completed 10000 read accesses @27318359
-system.cpu3: completed 20000 read accesses @53279230
-system.cpu6: completed 20000 read accesses @53417084
-system.cpu2: completed 20000 read accesses @53757092
-system.cpu0: completed 20000 read accesses @53888320
-system.cpu5: completed 20000 read accesses @53947132
-system.cpu4: completed 20000 read accesses @54390092
-system.cpu1: completed 20000 read accesses @54397720
-system.cpu7: completed 20000 read accesses @54632966
-system.cpu6: completed 30000 read accesses @80144176
-system.cpu3: completed 30000 read accesses @80518264
-system.cpu0: completed 30000 read accesses @80638600
-system.cpu5: completed 30000 read accesses @80869702
-system.cpu1: completed 30000 read accesses @81289158
-system.cpu2: completed 30000 read accesses @81358716
-system.cpu7: completed 30000 read accesses @81981296
-system.cpu4: completed 30000 read accesses @82043104
-system.cpu6: completed 40000 read accesses @107087547
-system.cpu0: completed 40000 read accesses @107662142
-system.cpu3: completed 40000 read accesses @107722516
-system.cpu5: completed 40000 read accesses @107884124
-system.cpu1: completed 40000 read accesses @107981413
-system.cpu7: completed 40000 read accesses @108415286
-system.cpu2: completed 40000 read accesses @108655120
-system.cpu4: completed 40000 read accesses @109427858
-system.cpu6: completed 50000 read accesses @133583246
-system.cpu0: completed 50000 read accesses @133832383
-system.cpu5: completed 50000 read accesses @134755386
-system.cpu1: completed 50000 read accesses @134792594
-system.cpu7: completed 50000 read accesses @134914312
-system.cpu3: completed 50000 read accesses @134993978
-system.cpu2: completed 50000 read accesses @135362549
-system.cpu4: completed 50000 read accesses @135394370
-system.cpu0: completed 60000 read accesses @160410176
-system.cpu6: completed 60000 read accesses @160667590
-system.cpu7: completed 60000 read accesses @161466346
-system.cpu1: completed 60000 read accesses @161592434
-system.cpu5: completed 60000 read accesses @161656374
-system.cpu4: completed 60000 read accesses @161882626
-system.cpu2: completed 60000 read accesses @162062631
-system.cpu3: completed 60000 read accesses @162154299
-system.cpu6: completed 70000 read accesses @187592265
-system.cpu1: completed 70000 read accesses @188138542
-system.cpu7: completed 70000 read accesses @188373105
-system.cpu0: completed 70000 read accesses @188690782
-system.cpu3: completed 70000 read accesses @189309687
-system.cpu2: completed 70000 read accesses @189360790
-system.cpu4: completed 70000 read accesses @189391126
-system.cpu5: completed 70000 read accesses @189902895
-system.cpu6: completed 80000 read accesses @214739574
-system.cpu1: completed 80000 read accesses @215665444
-system.cpu0: completed 80000 read accesses @216021457
-system.cpu7: completed 80000 read accesses @216394344
-system.cpu3: completed 80000 read accesses @216537382
-system.cpu4: completed 80000 read accesses @216775798
-system.cpu2: completed 80000 read accesses @216868662
-system.cpu5: completed 80000 read accesses @217401619
-system.cpu6: completed 90000 read accesses @241415090
-system.cpu1: completed 90000 read accesses @242558992
-system.cpu0: completed 90000 read accesses @242897388
-system.cpu7: completed 90000 read accesses @243372191
-system.cpu3: completed 90000 read accesses @243630762
-system.cpu5: completed 90000 read accesses @243633950
-system.cpu4: completed 90000 read accesses @243710816
-system.cpu2: completed 90000 read accesses @243974160
-system.cpu6: completed 100000 read accesses @268915439
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:21:43
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:21:45
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re --stdout-file stdout --stderr-file stderr tests/run.py quick/50.memtest/alpha/linux/memtest
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 268915439 because maximum number of loads reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-drivesys.cpu.dtb.accesses 401302 # DTB accesses
-drivesys.cpu.dtb.acv 40 # DTB access violations
-drivesys.cpu.dtb.hits 624235 # DTB hits
-drivesys.cpu.dtb.misses 569 # DTB misses
-drivesys.cpu.dtb.read_accesses 268057 # DTB read accesses
-drivesys.cpu.dtb.read_acv 30 # DTB read access violations
-drivesys.cpu.dtb.read_hits 393500 # DTB read hits
-drivesys.cpu.dtb.read_misses 487 # DTB read misses
-drivesys.cpu.dtb.write_accesses 133245 # DTB write accesses
-drivesys.cpu.dtb.write_acv 10 # DTB write access violations
-drivesys.cpu.dtb.write_hits 230735 # DTB write hits
-drivesys.cpu.dtb.write_misses 82 # DTB write misses
-drivesys.cpu.idle_fraction 1.000000 # Percentage of idle cycles
-drivesys.cpu.itb.accesses 1337980 # ITB accesses
-drivesys.cpu.itb.acv 22 # ITB acv
-drivesys.cpu.itb.hits 1337786 # ITB hits
-drivesys.cpu.itb.misses 194 # ITB misses
-drivesys.cpu.kern.callpal 4443 # number of callpals executed
-drivesys.cpu.kern.callpal_swpctx 70 1.58% 1.58% # number of callpals executed
-drivesys.cpu.kern.callpal_tbi 5 0.11% 1.69% # number of callpals executed
-drivesys.cpu.kern.callpal_swpipl 3654 82.24% 83.93% # number of callpals executed
-drivesys.cpu.kern.callpal_rdps 359 8.08% 92.01% # number of callpals executed
-drivesys.cpu.kern.callpal_rdusp 1 0.02% 92.03% # number of callpals executed
-drivesys.cpu.kern.callpal_rti 322 7.25% 99.28% # number of callpals executed
-drivesys.cpu.kern.callpal_callsys 25 0.56% 99.84% # number of callpals executed
-drivesys.cpu.kern.callpal_imb 7 0.16% 100.00% # number of callpals executed
-drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
-drivesys.cpu.kern.inst.hwrei 5483 # number of hwrei instructions executed
-drivesys.cpu.kern.inst.quiesce 215 # number of quiesce instructions executed
-drivesys.cpu.kern.ipl_count 4191 # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count_0 1189 28.37% 28.37% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count_21 10 0.24% 28.61% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count_22 205 4.89% 33.50% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count_31 2787 66.50% 100.00% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_good 2593 # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks 199571362884 # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks_0 199571043172 100.00% 100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used_31 0.426624 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.mode_good_kernel 110
-drivesys.cpu.kern.mode_good_user 107
-drivesys.cpu.kern.mode_good_idle 3
-drivesys.cpu.kern.mode_switch_kernel 174 # number of protection mode switches
-drivesys.cpu.kern.mode_switch_user 107 # number of protection mode switches
-drivesys.cpu.kern.mode_switch_idle 218 # number of protection mode switches
-drivesys.cpu.kern.mode_switch_good 1.645945 # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks_user 1278343 1.15% 1.39% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks_idle 109686421 98.61% 100.00% # number of ticks spent at the given mode
-drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed
-drivesys.cpu.kern.syscall 22 # number of syscalls executed
-drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed
-drivesys.cpu.kern.syscall_6 3 13.64% 18.18% # number of syscalls executed
-drivesys.cpu.kern.syscall_17 2 9.09% 27.27% # number of syscalls executed
-drivesys.cpu.kern.syscall_97 1 4.55% 31.82% # number of syscalls executed
-drivesys.cpu.kern.syscall_99 2 9.09% 40.91% # number of syscalls executed
-drivesys.cpu.kern.syscall_101 2 9.09% 50.00% # number of syscalls executed
-drivesys.cpu.kern.syscall_102 3 13.64% 63.64% # number of syscalls executed
-drivesys.cpu.kern.syscall_104 1 4.55% 68.18% # number of syscalls executed
-drivesys.cpu.kern.syscall_105 3 13.64% 81.82% # number of syscalls executed
-drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # number of syscalls executed
-drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed
-drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed
-drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles
-drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated
-drivesys.cpu.num_insts 1958129 # Number of instructions executed
-drivesys.cpu.num_refs 626223 # Number of memory references
-drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
-drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
-drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
-drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
-drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-drivesys.tsunami.ethernet.descDMAReads 4 # Number of descriptors the device read w/ DMA
-drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes 96 # number of descriptor bytes read w/ DMA
-drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
-drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-drivesys.tsunami.ethernet.postedInterrupts 16 # number of posts to CPU
-drivesys.tsunami.ethernet.postedRxDesc 6 # number of RxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.postedTxIdle 4 # number of TxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.rxBandwidth 38400 # Receive Bandwidth (bits/s)
-drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
-drivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device
-drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s)
-drivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received
-drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device
-drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
-drivesys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s)
-drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes
-drivesys.tsunami.ethernet.totPackets 13 # Total Packets
-drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR
-drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-drivesys.tsunami.ethernet.totalTxIdle 4 # total number of TxIdle written to ISR
-drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-drivesys.tsunami.ethernet.txBandwidth 31920 # Transmit Bandwidth (bits/s)
-drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
-drivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
-drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s)
-drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
-drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
-drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-host_inst_rate 200792296 # Simulator instruction rate (inst/s)
-host_mem_usage 476644 # Number of bytes of host memory used
-host_seconds 1.36 # Real time elapsed on the host
-host_tick_rate 146922204609 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 273294177 # Number of instructions simulated
-sim_seconds 0.200001 # Number of seconds simulated
-sim_ticks 200000789468 # Number of ticks simulated
-testsys.cpu.dtb.accesses 335402 # DTB accesses
-testsys.cpu.dtb.acv 161 # DTB access violations
-testsys.cpu.dtb.hits 1163288 # DTB hits
-testsys.cpu.dtb.misses 3815 # DTB misses
-testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
-testsys.cpu.dtb.read_acv 80 # DTB read access violations
-testsys.cpu.dtb.read_hits 658435 # DTB read hits
-testsys.cpu.dtb.read_misses 3287 # DTB read misses
-testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
-testsys.cpu.dtb.write_acv 81 # DTB write access violations
-testsys.cpu.dtb.write_hits 504853 # DTB write hits
-testsys.cpu.dtb.write_misses 528 # DTB write misses
-testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles
-testsys.cpu.itb.accesses 1249822 # ITB accesses
-testsys.cpu.itb.acv 69 # ITB acv
-testsys.cpu.itb.hits 1248325 # ITB hits
-testsys.cpu.itb.misses 1497 # ITB misses
-testsys.cpu.kern.callpal 13122 # number of callpals executed
-testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed
-testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed
-testsys.cpu.kern.callpal_swpipl 11074 84.39% 87.88% # number of callpals executed
-testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed
-testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed
-testsys.cpu.kern.callpal_rdusp 3 0.02% 90.66% # number of callpals executed
-testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # number of callpals executed
-testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed
-testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed
-testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
-testsys.cpu.kern.inst.hwrei 19053 # number of hwrei instructions executed
-testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed
-testsys.cpu.kern.ipl_count 12504 # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count_21 184 1.47% 41.95% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count_22 205 1.64% 43.59% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count_31 7054 56.41% 100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks 199569460830 # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks_0 199568845670 100.00% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks_31 566504 0.00% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.mode_good_kernel 654
-testsys.cpu.kern.mode_good_user 649
-testsys.cpu.kern.mode_good_idle 5
-testsys.cpu.kern.mode_switch_kernel 1099 # number of protection mode switches
-testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches
-testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches
-testsys.cpu.kern.mode_switch_good 1.608210 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good_kernel 0.595086 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks_kernel 1821131 2.10% 2.10% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks_user 1065606 1.23% 3.32% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks_idle 83963628 96.68% 100.00% # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
-testsys.cpu.kern.syscall 83 # number of syscalls executed
-testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed
-testsys.cpu.kern.syscall_3 7 8.43% 12.05% # number of syscalls executed
-testsys.cpu.kern.syscall_4 1 1.20% 13.25% # number of syscalls executed
-testsys.cpu.kern.syscall_6 7 8.43% 21.69% # number of syscalls executed
-testsys.cpu.kern.syscall_17 7 8.43% 30.12% # number of syscalls executed
-testsys.cpu.kern.syscall_19 2 2.41% 32.53% # number of syscalls executed
-testsys.cpu.kern.syscall_20 1 1.20% 33.73% # number of syscalls executed
-testsys.cpu.kern.syscall_33 3 3.61% 37.35% # number of syscalls executed
-testsys.cpu.kern.syscall_45 10 12.05% 49.40% # number of syscalls executed
-testsys.cpu.kern.syscall_48 5 6.02% 55.42% # number of syscalls executed
-testsys.cpu.kern.syscall_54 1 1.20% 56.63% # number of syscalls executed
-testsys.cpu.kern.syscall_59 3 3.61% 60.24% # number of syscalls executed
-testsys.cpu.kern.syscall_71 15 18.07% 78.31% # number of syscalls executed
-testsys.cpu.kern.syscall_74 4 4.82% 83.13% # number of syscalls executed
-testsys.cpu.kern.syscall_97 2 2.41% 85.54% # number of syscalls executed
-testsys.cpu.kern.syscall_98 2 2.41% 87.95% # number of syscalls executed
-testsys.cpu.kern.syscall_101 2 2.41% 90.36% # number of syscalls executed
-testsys.cpu.kern.syscall_102 2 2.41% 92.77% # number of syscalls executed
-testsys.cpu.kern.syscall_104 1 1.20% 93.98% # number of syscalls executed
-testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed
-testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed
-testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles
-testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated
-testsys.cpu.num_insts 3560411 # Number of instructions executed
-testsys.cpu.num_refs 1173571 # Number of memory references
-testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
-testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
-testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
-testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
-testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-testsys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-testsys.tsunami.ethernet.descDMAReads 6 # Number of descriptors the device read w/ DMA
-testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes 144 # number of descriptor bytes read w/ DMA
-testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
-testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-testsys.tsunami.ethernet.postedInterrupts 15 # number of posts to CPU
-testsys.tsunami.ethernet.postedRxDesc 4 # number of RxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.postedTxIdle 6 # number of TxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-testsys.tsunami.ethernet.rxBandwidth 31920 # Receive Bandwidth (bits/s)
-testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
-testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device
-testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s)
-testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received
-testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device
-testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
-testsys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s)
-testsys.tsunami.ethernet.totBytes 1758 # Total Bytes
-testsys.tsunami.ethernet.totPackets 13 # Total Packets
-testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR
-testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-testsys.tsunami.ethernet.totalTxIdle 6 # total number of TxIdle written to ISR
-testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-testsys.tsunami.ethernet.txBandwidth 38400 # Transmit Bandwidth (bits/s)
-testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
-testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
-testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s)
-testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted
-testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
-testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-
----------- End Simulation Statistics ----------
-
----------- Begin Simulation Statistics ----------
-drivesys.cpu.dtb.accesses 0 # DTB accesses
-drivesys.cpu.dtb.acv 0 # DTB access violations
-drivesys.cpu.dtb.hits 0 # DTB hits
-drivesys.cpu.dtb.misses 0 # DTB misses
-drivesys.cpu.dtb.read_accesses 0 # DTB read accesses
-drivesys.cpu.dtb.read_acv 0 # DTB read access violations
-drivesys.cpu.dtb.read_hits 0 # DTB read hits
-drivesys.cpu.dtb.read_misses 0 # DTB read misses
-drivesys.cpu.dtb.write_accesses 0 # DTB write accesses
-drivesys.cpu.dtb.write_acv 0 # DTB write access violations
-drivesys.cpu.dtb.write_hits 0 # DTB write hits
-drivesys.cpu.dtb.write_misses 0 # DTB write misses
-drivesys.cpu.idle_fraction 1 # Percentage of idle cycles
-drivesys.cpu.itb.accesses 0 # ITB accesses
-drivesys.cpu.itb.acv 0 # ITB acv
-drivesys.cpu.itb.hits 0 # ITB hits
-drivesys.cpu.itb.misses 0 # ITB misses
-drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
-drivesys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed
-drivesys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-drivesys.cpu.kern.mode_good_kernel 0
-drivesys.cpu.kern.mode_good_user 0
-drivesys.cpu.kern.mode_good_idle 0
-drivesys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches
-drivesys.cpu.kern.mode_switch_user 0 # number of protection mode switches
-drivesys.cpu.kern.mode_switch_idle 0 # number of protection mode switches
-drivesys.cpu.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good_kernel <err: div-0> # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good_user <err: div-0> # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode
-drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed
-drivesys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles
-drivesys.cpu.numCycles 0 # number of cpu cycles simulated
-drivesys.cpu.num_insts 0 # Number of instructions executed
-drivesys.cpu.num_refs 0 # Number of memory references
-drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
-drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
-drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
-drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
-drivesys.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
-drivesys.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
-drivesys.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
-drivesys.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
-drivesys.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
-drivesys.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
-drivesys.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
-drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-drivesys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-drivesys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-host_inst_rate 214516622449 # Simulator instruction rate (inst/s)
-host_mem_usage 476644 # Number of bytes of host memory used
-host_seconds 0.00 # Real time elapsed on the host
-host_tick_rate 582637509 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 273294177 # Number of instructions simulated
-sim_seconds 0.000001 # Number of seconds simulated
-sim_ticks 785978 # Number of ticks simulated
-testsys.cpu.dtb.accesses 0 # DTB accesses
-testsys.cpu.dtb.acv 0 # DTB access violations
-testsys.cpu.dtb.hits 0 # DTB hits
-testsys.cpu.dtb.misses 0 # DTB misses
-testsys.cpu.dtb.read_accesses 0 # DTB read accesses
-testsys.cpu.dtb.read_acv 0 # DTB read access violations
-testsys.cpu.dtb.read_hits 0 # DTB read hits
-testsys.cpu.dtb.read_misses 0 # DTB read misses
-testsys.cpu.dtb.write_accesses 0 # DTB write accesses
-testsys.cpu.dtb.write_acv 0 # DTB write access violations
-testsys.cpu.dtb.write_hits 0 # DTB write hits
-testsys.cpu.dtb.write_misses 0 # DTB write misses
-testsys.cpu.idle_fraction 1 # Percentage of idle cycles
-testsys.cpu.itb.accesses 0 # ITB accesses
-testsys.cpu.itb.acv 0 # ITB acv
-testsys.cpu.itb.hits 0 # ITB hits
-testsys.cpu.itb.misses 0 # ITB misses
-testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
-testsys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed
-testsys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-testsys.cpu.kern.mode_good_kernel 0
-testsys.cpu.kern.mode_good_user 0
-testsys.cpu.kern.mode_good_idle 0
-testsys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches
-testsys.cpu.kern.mode_switch_user 0 # number of protection mode switches
-testsys.cpu.kern.mode_switch_idle 0 # number of protection mode switches
-testsys.cpu.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good_kernel <err: div-0> # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good_user <err: div-0> # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context 0 # number of times the context was actually changed
-testsys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles
-testsys.cpu.numCycles 0 # number of cpu cycles simulated
-testsys.cpu.num_insts 0 # Number of instructions executed
-testsys.cpu.num_refs 0 # Number of memory references
-testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
-testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
-testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
-testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
-testsys.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
-testsys.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
-testsys.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
-testsys.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
-testsys.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
-testsys.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
-testsys.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
-testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-testsys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
-testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-testsys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
-testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-testsys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-
----------- End Simulation Statistics ----------
--- /dev/null
+warn: kernel located at: /dist/m5/system/binaries/vmlinux
+warn: Sockets disabled, not accepting terminal connections
+warn: kernel located at: /dist/m5/system/binaries/vmlinux
+warn: Sockets disabled, not accepting gdb connections
+warn: Obsolete M5 ivlb instruction encountered.
+warn: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:38:27
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 4300236804024 because checkpoint
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+drivesys.cpu.dtb.accesses 401302 # DTB accesses
+drivesys.cpu.dtb.acv 40 # DTB access violations
+drivesys.cpu.dtb.hits 624235 # DTB hits
+drivesys.cpu.dtb.misses 569 # DTB misses
+drivesys.cpu.dtb.read_accesses 268057 # DTB read accesses
+drivesys.cpu.dtb.read_acv 30 # DTB read access violations
+drivesys.cpu.dtb.read_hits 393500 # DTB read hits
+drivesys.cpu.dtb.read_misses 487 # DTB read misses
+drivesys.cpu.dtb.write_accesses 133245 # DTB write accesses
+drivesys.cpu.dtb.write_acv 10 # DTB write access violations
+drivesys.cpu.dtb.write_hits 230735 # DTB write hits
+drivesys.cpu.dtb.write_misses 82 # DTB write misses
+drivesys.cpu.idle_fraction 1.000000 # Percentage of idle cycles
+drivesys.cpu.itb.accesses 1337980 # ITB accesses
+drivesys.cpu.itb.acv 22 # ITB acv
+drivesys.cpu.itb.hits 1337786 # ITB hits
+drivesys.cpu.itb.misses 194 # ITB misses
+drivesys.cpu.kern.callpal 4443 # number of callpals executed
+drivesys.cpu.kern.callpal_swpctx 70 1.58% 1.58% # number of callpals executed
+drivesys.cpu.kern.callpal_tbi 5 0.11% 1.69% # number of callpals executed
+drivesys.cpu.kern.callpal_swpipl 3654 82.24% 83.93% # number of callpals executed
+drivesys.cpu.kern.callpal_rdps 359 8.08% 92.01% # number of callpals executed
+drivesys.cpu.kern.callpal_rdusp 1 0.02% 92.03% # number of callpals executed
+drivesys.cpu.kern.callpal_rti 322 7.25% 99.28% # number of callpals executed
+drivesys.cpu.kern.callpal_callsys 25 0.56% 99.84% # number of callpals executed
+drivesys.cpu.kern.callpal_imb 7 0.16% 100.00% # number of callpals executed
+drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
+drivesys.cpu.kern.inst.hwrei 5483 # number of hwrei instructions executed
+drivesys.cpu.kern.inst.quiesce 215 # number of quiesce instructions executed
+drivesys.cpu.kern.ipl_count 4191 # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count_0 1189 28.37% 28.37% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count_21 10 0.24% 28.61% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count_22 205 4.89% 33.50% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count_31 2787 66.50% 100.00% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_good 2593 # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_ticks 199571362884 # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks_0 199571043172 100.00% 100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used_31 0.426624 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.mode_good_kernel 110
+drivesys.cpu.kern.mode_good_user 107
+drivesys.cpu.kern.mode_good_idle 3
+drivesys.cpu.kern.mode_switch_kernel 174 # number of protection mode switches
+drivesys.cpu.kern.mode_switch_user 107 # number of protection mode switches
+drivesys.cpu.kern.mode_switch_idle 218 # number of protection mode switches
+drivesys.cpu.kern.mode_switch_good 1.645945 # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks_user 1278343 1.15% 1.39% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks_idle 109686421 98.61% 100.00% # number of ticks spent at the given mode
+drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed
+drivesys.cpu.kern.syscall 22 # number of syscalls executed
+drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed
+drivesys.cpu.kern.syscall_6 3 13.64% 18.18% # number of syscalls executed
+drivesys.cpu.kern.syscall_17 2 9.09% 27.27% # number of syscalls executed
+drivesys.cpu.kern.syscall_97 1 4.55% 31.82% # number of syscalls executed
+drivesys.cpu.kern.syscall_99 2 9.09% 40.91% # number of syscalls executed
+drivesys.cpu.kern.syscall_101 2 9.09% 50.00% # number of syscalls executed
+drivesys.cpu.kern.syscall_102 3 13.64% 63.64% # number of syscalls executed
+drivesys.cpu.kern.syscall_104 1 4.55% 68.18% # number of syscalls executed
+drivesys.cpu.kern.syscall_105 3 13.64% 81.82% # number of syscalls executed
+drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # number of syscalls executed
+drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed
+drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed
+drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles
+drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated
+drivesys.cpu.num_insts 1958129 # Number of instructions executed
+drivesys.cpu.num_refs 626223 # Number of memory references
+drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
+drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
+drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
+drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
+drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+drivesys.tsunami.ethernet.descDMAReads 4 # Number of descriptors the device read w/ DMA
+drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
+drivesys.tsunami.ethernet.descDmaReadBytes 96 # number of descriptor bytes read w/ DMA
+drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
+drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+drivesys.tsunami.ethernet.postedInterrupts 16 # number of posts to CPU
+drivesys.tsunami.ethernet.postedRxDesc 6 # number of RxDesc interrupts posted to CPU
+drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+drivesys.tsunami.ethernet.postedTxIdle 4 # number of TxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+drivesys.tsunami.ethernet.rxBandwidth 38400 # Receive Bandwidth (bits/s)
+drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
+drivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device
+drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s)
+drivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received
+drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device
+drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
+drivesys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s)
+drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes
+drivesys.tsunami.ethernet.totPackets 13 # Total Packets
+drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR
+drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+drivesys.tsunami.ethernet.totalTxIdle 4 # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+drivesys.tsunami.ethernet.txBandwidth 31920 # Transmit Bandwidth (bits/s)
+drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
+drivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
+drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s)
+drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
+drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
+drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+host_inst_rate 200792296 # Simulator instruction rate (inst/s)
+host_mem_usage 476644 # Number of bytes of host memory used
+host_seconds 1.36 # Real time elapsed on the host
+host_tick_rate 146922204609 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 273294177 # Number of instructions simulated
+sim_seconds 0.200001 # Number of seconds simulated
+sim_ticks 200000789468 # Number of ticks simulated
+testsys.cpu.dtb.accesses 335402 # DTB accesses
+testsys.cpu.dtb.acv 161 # DTB access violations
+testsys.cpu.dtb.hits 1163288 # DTB hits
+testsys.cpu.dtb.misses 3815 # DTB misses
+testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
+testsys.cpu.dtb.read_acv 80 # DTB read access violations
+testsys.cpu.dtb.read_hits 658435 # DTB read hits
+testsys.cpu.dtb.read_misses 3287 # DTB read misses
+testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
+testsys.cpu.dtb.write_acv 81 # DTB write access violations
+testsys.cpu.dtb.write_hits 504853 # DTB write hits
+testsys.cpu.dtb.write_misses 528 # DTB write misses
+testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles
+testsys.cpu.itb.accesses 1249822 # ITB accesses
+testsys.cpu.itb.acv 69 # ITB acv
+testsys.cpu.itb.hits 1248325 # ITB hits
+testsys.cpu.itb.misses 1497 # ITB misses
+testsys.cpu.kern.callpal 13122 # number of callpals executed
+testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed
+testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed
+testsys.cpu.kern.callpal_swpipl 11074 84.39% 87.88% # number of callpals executed
+testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed
+testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed
+testsys.cpu.kern.callpal_rdusp 3 0.02% 90.66% # number of callpals executed
+testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # number of callpals executed
+testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed
+testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed
+testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
+testsys.cpu.kern.inst.hwrei 19053 # number of hwrei instructions executed
+testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed
+testsys.cpu.kern.ipl_count 12504 # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count_21 184 1.47% 41.95% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count_22 205 1.64% 43.59% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count_31 7054 56.41% 100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_ticks 199569460830 # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks_0 199568845670 100.00% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks_31 566504 0.00% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.mode_good_kernel 654
+testsys.cpu.kern.mode_good_user 649
+testsys.cpu.kern.mode_good_idle 5
+testsys.cpu.kern.mode_switch_kernel 1099 # number of protection mode switches
+testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches
+testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches
+testsys.cpu.kern.mode_switch_good 1.608210 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good_kernel 0.595086 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_ticks_kernel 1821131 2.10% 2.10% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks_user 1065606 1.23% 3.32% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks_idle 83963628 96.68% 100.00% # number of ticks spent at the given mode
+testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
+testsys.cpu.kern.syscall 83 # number of syscalls executed
+testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed
+testsys.cpu.kern.syscall_3 7 8.43% 12.05% # number of syscalls executed
+testsys.cpu.kern.syscall_4 1 1.20% 13.25% # number of syscalls executed
+testsys.cpu.kern.syscall_6 7 8.43% 21.69% # number of syscalls executed
+testsys.cpu.kern.syscall_17 7 8.43% 30.12% # number of syscalls executed
+testsys.cpu.kern.syscall_19 2 2.41% 32.53% # number of syscalls executed
+testsys.cpu.kern.syscall_20 1 1.20% 33.73% # number of syscalls executed
+testsys.cpu.kern.syscall_33 3 3.61% 37.35% # number of syscalls executed
+testsys.cpu.kern.syscall_45 10 12.05% 49.40% # number of syscalls executed
+testsys.cpu.kern.syscall_48 5 6.02% 55.42% # number of syscalls executed
+testsys.cpu.kern.syscall_54 1 1.20% 56.63% # number of syscalls executed
+testsys.cpu.kern.syscall_59 3 3.61% 60.24% # number of syscalls executed
+testsys.cpu.kern.syscall_71 15 18.07% 78.31% # number of syscalls executed
+testsys.cpu.kern.syscall_74 4 4.82% 83.13% # number of syscalls executed
+testsys.cpu.kern.syscall_97 2 2.41% 85.54% # number of syscalls executed
+testsys.cpu.kern.syscall_98 2 2.41% 87.95% # number of syscalls executed
+testsys.cpu.kern.syscall_101 2 2.41% 90.36% # number of syscalls executed
+testsys.cpu.kern.syscall_102 2 2.41% 92.77% # number of syscalls executed
+testsys.cpu.kern.syscall_104 1 1.20% 93.98% # number of syscalls executed
+testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed
+testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed
+testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles
+testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated
+testsys.cpu.num_insts 3560411 # Number of instructions executed
+testsys.cpu.num_refs 1173571 # Number of memory references
+testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
+testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
+testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
+testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
+testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+testsys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+testsys.tsunami.ethernet.descDMAReads 6 # Number of descriptors the device read w/ DMA
+testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
+testsys.tsunami.ethernet.descDmaReadBytes 144 # number of descriptor bytes read w/ DMA
+testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
+testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+testsys.tsunami.ethernet.postedInterrupts 15 # number of posts to CPU
+testsys.tsunami.ethernet.postedRxDesc 4 # number of RxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.postedTxIdle 6 # number of TxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+testsys.tsunami.ethernet.rxBandwidth 31920 # Receive Bandwidth (bits/s)
+testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
+testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device
+testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s)
+testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received
+testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device
+testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
+testsys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s)
+testsys.tsunami.ethernet.totBytes 1758 # Total Bytes
+testsys.tsunami.ethernet.totPackets 13 # Total Packets
+testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR
+testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+testsys.tsunami.ethernet.totalTxIdle 6 # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+testsys.tsunami.ethernet.txBandwidth 38400 # Transmit Bandwidth (bits/s)
+testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
+testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device
+testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s)
+testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted
+testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
+testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+
+---------- End Simulation Statistics ----------
+
+---------- Begin Simulation Statistics ----------
+drivesys.cpu.dtb.accesses 0 # DTB accesses
+drivesys.cpu.dtb.acv 0 # DTB access violations
+drivesys.cpu.dtb.hits 0 # DTB hits
+drivesys.cpu.dtb.misses 0 # DTB misses
+drivesys.cpu.dtb.read_accesses 0 # DTB read accesses
+drivesys.cpu.dtb.read_acv 0 # DTB read access violations
+drivesys.cpu.dtb.read_hits 0 # DTB read hits
+drivesys.cpu.dtb.read_misses 0 # DTB read misses
+drivesys.cpu.dtb.write_accesses 0 # DTB write accesses
+drivesys.cpu.dtb.write_acv 0 # DTB write access violations
+drivesys.cpu.dtb.write_hits 0 # DTB write hits
+drivesys.cpu.dtb.write_misses 0 # DTB write misses
+drivesys.cpu.idle_fraction 1 # Percentage of idle cycles
+drivesys.cpu.itb.accesses 0 # ITB accesses
+drivesys.cpu.itb.acv 0 # ITB acv
+drivesys.cpu.itb.hits 0 # ITB hits
+drivesys.cpu.itb.misses 0 # ITB misses
+drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
+drivesys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed
+drivesys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
+drivesys.cpu.kern.mode_good_kernel 0
+drivesys.cpu.kern.mode_good_user 0
+drivesys.cpu.kern.mode_good_idle 0
+drivesys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches
+drivesys.cpu.kern.mode_switch_user 0 # number of protection mode switches
+drivesys.cpu.kern.mode_switch_idle 0 # number of protection mode switches
+drivesys.cpu.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good_kernel <err: div-0> # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good_user <err: div-0> # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode
+drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed
+drivesys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles
+drivesys.cpu.numCycles 0 # number of cpu cycles simulated
+drivesys.cpu.num_insts 0 # Number of instructions executed
+drivesys.cpu.num_refs 0 # Number of memory references
+drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
+drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions.
+drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
+drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+drivesys.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
+drivesys.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
+drivesys.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
+drivesys.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
+drivesys.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
+drivesys.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+drivesys.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
+drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+drivesys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+drivesys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+host_inst_rate 214516622449 # Simulator instruction rate (inst/s)
+host_mem_usage 476644 # Number of bytes of host memory used
+host_seconds 0.00 # Real time elapsed on the host
+host_tick_rate 582637509 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 273294177 # Number of instructions simulated
+sim_seconds 0.000001 # Number of seconds simulated
+sim_ticks 785978 # Number of ticks simulated
+testsys.cpu.dtb.accesses 0 # DTB accesses
+testsys.cpu.dtb.acv 0 # DTB access violations
+testsys.cpu.dtb.hits 0 # DTB hits
+testsys.cpu.dtb.misses 0 # DTB misses
+testsys.cpu.dtb.read_accesses 0 # DTB read accesses
+testsys.cpu.dtb.read_acv 0 # DTB read access violations
+testsys.cpu.dtb.read_hits 0 # DTB read hits
+testsys.cpu.dtb.read_misses 0 # DTB read misses
+testsys.cpu.dtb.write_accesses 0 # DTB write accesses
+testsys.cpu.dtb.write_acv 0 # DTB write access violations
+testsys.cpu.dtb.write_hits 0 # DTB write hits
+testsys.cpu.dtb.write_misses 0 # DTB write misses
+testsys.cpu.idle_fraction 1 # Percentage of idle cycles
+testsys.cpu.itb.accesses 0 # ITB accesses
+testsys.cpu.itb.acv 0 # ITB acv
+testsys.cpu.itb.hits 0 # ITB hits
+testsys.cpu.itb.misses 0 # ITB misses
+testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
+testsys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed
+testsys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
+testsys.cpu.kern.mode_good_kernel 0
+testsys.cpu.kern.mode_good_user 0
+testsys.cpu.kern.mode_good_idle 0
+testsys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches
+testsys.cpu.kern.mode_switch_user 0 # number of protection mode switches
+testsys.cpu.kern.mode_switch_idle 0 # number of protection mode switches
+testsys.cpu.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good_kernel <err: div-0> # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good_user <err: div-0> # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
+testsys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode
+testsys.cpu.kern.swap_context 0 # number of times the context was actually changed
+testsys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles
+testsys.cpu.numCycles 0 # number of cpu cycles simulated
+testsys.cpu.num_insts 0 # Number of instructions executed
+testsys.cpu.num_refs 0 # Number of memory references
+testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes.
+testsys.disk0.dma_write_txs 0 # Number of DMA write transactions.
+testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
+testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes.
+testsys.disk2.dma_write_txs 0 # Number of DMA write transactions.
+testsys.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
+testsys.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
+testsys.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
+testsys.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
+testsys.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
+testsys.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+testsys.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
+testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+testsys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
+testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+testsys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
+testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+testsys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
-warn: Sockets disabled, not accepting terminal connections
-warn: kernel located at: /dist/m5/system/binaries/vmlinux
-warn: Sockets disabled, not accepting gdb connections
-warn: Obsolete M5 ivlb instruction encountered.
-warn: be nice to actually delete the event here
+++ /dev/null
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Dec 4 2008 21:30:58
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:38:27
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 4300236804024 because checkpoint
projects / gem5.git / commitdiff