integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding...

This is useful for CPUs elaborated at buildtime to use sdram's native data width on the CPU memory ports.

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 838e65b3de4842492fe684011be24dbeeea4ab8f..40ae46a5159f9f35fea28ab537d51a67a24a2441 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1157,6 +1157,13 @@ class LiteXSoC(SoC):
         # Add SDRAM region
         self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size))
 
+        # Add CPU's direct memory buses (if not already declared) ----------------------------------
+        if hasattr(self.cpu, "add_memory_buses"):
+            self.cpu.add_memory_buses(
+                address_width = 32,
+                data_width    = self.sdram.crossbar.controller.data_width
+            )
+
         # SoC [<--> L2 Cache] <--> LiteDRAM --------------------------------------------------------
         if len(self.cpu.memory_buses):
             # When CPU has at least a direct memory bus, connect them directly to LiteDRAM.