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i386.md (SINCOS): New int iterator.
authorUros Bizjak <ubizjak@gmail.com>
Wed, 20 Jun 2012 19:28:07 +0000 (21:28 +0200)
committerUros Bizjak <uros@gcc.gnu.org>
Wed, 20 Jun 2012 19:28:07 +0000 (21:28 +0200)
2012-06-20  Uros Bizjak  <ubizjak@gmail.com>

* config/i386/i386.md (SINCOS): New int iterator.
(sincos): New int attribute.
(*<sincos>xf2_i387): Macroize insn from *{sin,cos}xf2_i387 using
SINCOS int iterator.
(*<sincos>_extend<mode>xf2_i387): Macroize insn from
*{sin,cos}_extend<mode>xf2_i387 using SINCOS int iterator.

2012-06-20  Uros Bizjak  <ubizjak@gmail.com>

* config/i386/i386.md (RDFSGSBASE): New int iterator.
(WRFSGSBASE): Ditto.
(fsgs): New int attribute.
(rd<fsgs>base<mode>): Macroize insn from rd<fsgs>base<mode> using
RDFSGSBASE int iterator.
(wr<fsgs>base<mode>): Macroize insn from wr<fsgs>base<mode> using
WRFSGSBASE int iterator.

From-SVN: r188843

gcc/ChangeLog patch | blob | history
gcc/config/i386/i386.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 50bf3289acf9af3487237ae0d6b4becb4d646b50..543be452a170e5443a31b5f32be33581278e299a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -2,6 +2,25 @@
 
        * tree.h (DECL_SOURCE_COLUMN): New accessor.
 
+2012-06-20  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md (SINCOS): New int iterator.
+       (sincos): New int attribute.
+       (*<sincos>xf2_i387): Macroize insn from *{sin,cos}xf2_i387 using
+       SINCOS int iterator.
+       (*<sincos>_extend<mode>xf2_i387): Macroize insn from
+       *{sin,cos}_extend<mode>xf2_i387 using SINCOS int iterator.
+
+2012-06-20  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md (RDFSGSBASE): New int iterator.
+       (WRFSGSBASE): Ditto.
+       (fsgs): New int attribute.
+       (rd<fsgs>base<mode>): Macroize insn from rd<fsgs>base<mode> using
+       RDFSGSBASE int iterator.
+       (wr<fsgs>base<mode>): Macroize insn from wr<fsgs>base<mode> using
+       WRFSGSBASE int iterator.
+
 2012-06-20  Uros Bizjak  <ubizjak@gmail.com>
 
        * config/i386/i386.md (<rounding_insn><mode>2): Macroize expander
@@ -38,7 +57,7 @@
        * config/i386/i386.md (IEEE_MAXMIN): New int iterator.
        (ieee_maxmin): New int attribute.
        (*ieee_s<ieee_maxmin><mode>3): Macroize insn from
-       *ieee_s{max,min}<mode>3 using IEEE_MAXMIN mode iterator.
+       *ieee_s{max,min}<mode>3 using IEEE_MAXMIN int iterator.
 
 2012-06-20  Steven Bosscher  <steven@gcc.gnu.org>
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a74fdc0678d35a19c6c3d6b388002d3c3b3b10af..879b87b34479db1da851689eec026f563cdf9e69 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -13863,47 +13863,34 @@
   DONE;
 })
 
-(define_insn "*sinxf2_i387"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-       (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
-  "TARGET_USE_FANCY_MATH_387
-   && flag_unsafe_math_optimizations"
-  "fsin"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")])
+(define_int_iterator SINCOS
+       [UNSPEC_SIN
+        UNSPEC_COS])
 
-(define_insn "*sin_extend<mode>xf2_i387"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-       (unspec:XF [(float_extend:XF
-                     (match_operand:MODEF 1 "register_operand" "0"))]
-                  UNSPEC_SIN))]
-  "TARGET_USE_FANCY_MATH_387
-   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
-       || TARGET_MIX_SSE_I387)
-   && flag_unsafe_math_optimizations"
-  "fsin"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")])
+(define_int_attr sincos
+       [(UNSPEC_SIN "sin")
+        (UNSPEC_COS "cos")])
 
-(define_insn "*cosxf2_i387"
+(define_insn "*<sincos>xf2_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
-       (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
+       (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+                  SINCOS))]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
-  "fcos"
+  "f<sincos>"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
 
-(define_insn "*cos_extend<mode>xf2_i387"
+(define_insn "*<sincos>_extend<mode>xf2_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (unspec:XF [(float_extend:XF
                      (match_operand:MODEF 1 "register_operand" "0"))]
-                  UNSPEC_COS))]
+                  SINCOS))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
-  "fcos"
+  "f<sincos>"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
 
@@ -18087,35 +18074,33 @@
    (set (attr "length")
         (symbol_ref "ix86_attr_length_address_default (insn) + 9"))])
 
-(define_insn "rdfsbase<mode>"
-  [(set (match_operand:SWI48 0 "register_operand" "=r")
-       (unspec_volatile:SWI48 [(const_int 0)] UNSPECV_RDFSBASE))]
-  "TARGET_64BIT && TARGET_FSGSBASE"
-  "rdfsbase %0"
-  [(set_attr "type" "other")
-   (set_attr "prefix_extra" "2")])
+(define_int_iterator RDFSGSBASE
+       [UNSPECV_RDFSBASE
+        UNSPECV_RDGSBASE])
 
-(define_insn "rdgsbase<mode>"
-  [(set (match_operand:SWI48 0 "register_operand" "=r")
-       (unspec_volatile:SWI48 [(const_int 0)] UNSPECV_RDGSBASE))]
-  "TARGET_64BIT && TARGET_FSGSBASE"
-  "rdgsbase %0"
-  [(set_attr "type" "other")
-   (set_attr "prefix_extra" "2")])
+(define_int_iterator WRFSGSBASE
+       [UNSPECV_WRFSBASE
+        UNSPECV_WRGSBASE])
 
-(define_insn "wrfsbase<mode>"
-  [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")]
-                   UNSPECV_WRFSBASE)]
+(define_int_attr fsgs
+       [(UNSPECV_RDFSBASE "fs")
+        (UNSPECV_RDGSBASE "gs")
+        (UNSPECV_WRFSBASE "fs")
+        (UNSPECV_WRGSBASE "gs")])
+
+(define_insn "rd<fsgs>base<mode>"
+  [(set (match_operand:SWI48 0 "register_operand" "=r")
+       (unspec_volatile:SWI48 [(const_int 0)] RDFSGSBASE))]
   "TARGET_64BIT && TARGET_FSGSBASE"
-  "wrfsbase %0"
+  "rd<fsgs>base\t%0"
   [(set_attr "type" "other")
    (set_attr "prefix_extra" "2")])
 
-(define_insn "wrgsbase<mode>"
+(define_insn "wr<fsgs>base<mode>"
   [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")]
-                   UNSPECV_WRGSBASE)]
+                   WRFSGSBASE)]
   "TARGET_64BIT && TARGET_FSGSBASE"
-  "wrgsbase %0"
+  "wr<fsgs>base\t%0"
   [(set_attr "type" "other")
    (set_attr "prefix_extra" "2")])