2002-06-07 Chris Demetriou <cgd@broadcom.com>

	* cp1.c: Clean up formatting of a few comments.
	(value_fpr): Reformat switch statement.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index dff7b80707205f6b429191ebc3dc1eb4d6326ddc..0afcde955529cbec7d642ff62f513579c472c40b 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,8 @@
+2002-06-07  Chris Demetriou  <cgd@broadcom.com>
+
+       * cp1.c: Clean up formatting of a few comments.
+       (value_fpr): Reformat switch statement.
+
 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
             Ed Satterthwaite  <ehs@broadcom.com>
 

diff --git a/sim/mips/cp1.c b/sim/mips/cp1.c
index 3641df7fc9583a5998f6bb86da1ea73b7c4bb932..e4bfba2b028a75d5fdda7618c25dc0e9502f6332 100644 (file)
--- a/sim/mips/cp1.c
+++ b/sim/mips/cp1.c
@@ -127,25 +127,11 @@ value_fpr (sim_cpu *cpu,
       /* Set QNaN value:  */
       switch (fmt)
        {
-       case fmt_single:
-         value = FPQNaN_SINGLE;
-         break;
-
-       case fmt_double:
-         value = FPQNaN_DOUBLE;
-         break;
-
-       case fmt_word:
-         value = FPQNaN_WORD;
-         break;
-
-       case fmt_long:
-         value = FPQNaN_LONG;
-         break;
-
-       default:
-         err = -1;
-         break;
+       case fmt_single:  value = FPQNaN_SINGLE;  break;
+       case fmt_double:  value = FPQNaN_DOUBLE;  break;
+       case fmt_word:    value = FPQNaN_WORD;    break;
+       case fmt_long:    value = FPQNaN_LONG;    break;
+       default:          err = -1;               break;
        }
     }
   else if (SizeFGR () == 64)
@@ -182,7 +168,7 @@ value_fpr (sim_cpu *cpu,
        case fmt_long:
          if ((fpr & 1) == 0)
            {
-             /* even registers only */
+             /* Even registers numbers only.  */
 #ifdef DEBUG
              printf ("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
                      fpr + 1, pr_uword64 ((uword64) FGR[fpr+1]),
@@ -280,7 +266,7 @@ store_fpr (sim_cpu *cpu,
        case fmt_long:
          if ((fpr & 1) == 0)
            {
-             /* even register number only */
+             /* Even register numbers only.  */
              FGR[fpr+1] = (value >> 32);
              FGR[fpr] = (value & 0xFFFFFFFF);
              FPR_STATE[fpr + 1] = fmt;