+2017-03-21 Palmer Dabbbelt <palmer@dabbelt.com>
+
+ * config/tc-riscv.c (md_show_usage): Remode defuct -m32, -m64,
+ -msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
+ print an invalid default ISA string.
+ * doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.
+
2017-03-22 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_relax_frag): Change fx_size of the
{
fprintf (stream, _("\
RISC-V options:\n\
- -m32 assemble RV32 code\n\
- -m64 assemble RV64 code (default)\n\
-fpic generate position-independent code\n\
-fno-pic don't generate position-independent code (default)\n\
- -msoft-float don't use F registers for floating-point values\n\
- -mhard-float use F registers for floating-point values (default)\n\
- -mno-rvc disable the C extension for compressed instructions (default)\n\
- -mrvc enable the C extension for compressed instructions\n\
- -march=ISA set the RISC-V architecture, RV64IMAFD by default\n\
+ -march=ISA set the RISC-V architecture\n\
+ -mabi=ABI set the RISC-V ABI\n\
"));
}
@c man begin OPTIONS
@table @gcctabopt
+@cindex @samp{-fpic} option, RISC-V
+@item -fpic
+Generate position-independent code
+
+@cindex @samp{-fno-pic} option, RISC-V
+@item -fno-pic
+Don't generate position-independent code (default)
+
@cindex @samp{-march=ISA} option, RISC-V
@item -march=ISA
Select the base isa, as specified by ISA. For example -march=rv32ima.