rv32ui_sc_tests = \
add addi \
amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoswap_w \
- #and andi \
- #auipc \
- #beq bge bgeu blt bltu bne \
- #div divu \
- #fence_i \
- #j jal jalr \
- #lb lbu lh lhu lw \
- #lui \
- #mul mulh mulhsu mulhu \
- #or ori \
- #rem remu \
- #sb sh sw \
- #sll slli \
- #slt slti \
+ and andi \
+ auipc \
+ beq bge bgeu blt bltu bne \
+ div divu \
+ fence_i \
+ j jal jalr \
+ lb lbu lh lhu lw \
+ lui \
+ mul mulh mulhu mulhsu \
+ or ori \
+ rem remu \
+ sb sh sw \
+ sll slli \
+ slt slti \
#sra srai \
#srl srli \
#sub \
#xor xori \
rv32ui_mc_tests = \
- #lrsc
+ lrsc
rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests))
rv32ui_pm_tests = $(addprefix rv32ui-pm-, $(rv32ui_mc_tests))
--- /dev/null
+#*****************************************************************************
+# and.S
+#-----------------------------------------------------------------------------
+#
+# Test and instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Logical tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 9, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 );
+ TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff );
+ TEST_RR_ZEROSRC12( 26, and, 0 );
+ TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# andi.S
+#-----------------------------------------------------------------------------
+#
+# Test andi instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Logical tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f );
+ TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 );
+ TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f );
+ TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
+ TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
+ TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f );
+
+ TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
+ TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
+ TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f );
+
+ TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 );
+ TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# auipc.S
+#-----------------------------------------------------------------------------
+#
+# Test auipc instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a0, 1<<12, \
+ .align 3; \
+ auipc a0, 0x00001; \
+ jal a1, 1f; \
+ 1: srl a1, a1, 12; \
+ sll a1, a1, 12; \
+ sub a0, a0, a1; \
+ )
+
+ TEST_CASE(3, a0, -1<<12, \
+ .align 3; \
+ auipc a0, 0xfffff; \
+ jal a1, 1f; \
+ 1: srl a1, a1, 12; \
+ sll a1, a1, 12; \
+ sub a0, a0, a1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# beq.S
+#-----------------------------------------------------------------------------
+#
+# Test beq instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Branch tests
+ #-------------------------------------------------------------
+
+ # Each test checks both forward and backward branches
+
+ TEST_BR2_OP_TAKEN( 2, beq, 0, 0 );
+ TEST_BR2_OP_TAKEN( 3, beq, 1, 1 );
+ TEST_BR2_OP_TAKEN( 4, beq, -1, -1 );
+
+ TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 );
+ TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 );
+ TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 );
+ TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 );
+
+ TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 21, x1, 3, \
+ li x1, 1; \
+ beq x0, x0, 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# bge.S
+#-----------------------------------------------------------------------------
+#
+# Test bge instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Branch tests
+ #-------------------------------------------------------------
+
+ # Each test checks both forward and backward branches
+
+ TEST_BR2_OP_TAKEN( 2, bge, 0, 0 );
+ TEST_BR2_OP_TAKEN( 3, bge, 1, 1 );
+ TEST_BR2_OP_TAKEN( 4, bge, -1, -1 );
+ TEST_BR2_OP_TAKEN( 5, bge, 1, 0 );
+ TEST_BR2_OP_TAKEN( 6, bge, 1, -1 );
+ TEST_BR2_OP_TAKEN( 7, bge, -1, -2 );
+
+ TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 );
+ TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 );
+ TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 );
+ TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 );
+
+ TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 );
+ TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 24, x1, 3, \
+ li x1, 1; \
+ bge x1, x0, 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# bgeu.S
+#-----------------------------------------------------------------------------
+#
+# Test bgeu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Branch tests
+ #-------------------------------------------------------------
+
+ # Each test checks both forward and backward branches
+
+ TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 );
+ TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 );
+ TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff );
+ TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 );
+ TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe );
+ TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 );
+
+ TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 );
+ TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff );
+ TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff );
+ TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
+
+ TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
+ TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 24, x1, 3, \
+ li x1, 1; \
+ bgeu x1, x0, 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# blt.S
+#-----------------------------------------------------------------------------
+#
+# Test blt instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Branch tests
+ #-------------------------------------------------------------
+
+ # Each test checks both forward and backward branches
+
+ TEST_BR2_OP_TAKEN( 2, blt, 0, 1 );
+ TEST_BR2_OP_TAKEN( 3, blt, -1, 1 );
+ TEST_BR2_OP_TAKEN( 4, blt, -2, -1 );
+
+ TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 );
+ TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 );
+ TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 );
+ TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 );
+
+ TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 );
+ TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 21, x1, 3, \
+ li x1, 1; \
+ blt x0, x1, 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# bltu.S
+#-----------------------------------------------------------------------------
+#
+# Test bltu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Branch tests
+ #-------------------------------------------------------------
+
+ # Each test checks both forward and backward branches
+
+ TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 );
+ TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff );
+ TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff );
+
+ TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 );
+ TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe );
+ TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 );
+ TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff );
+
+ TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff );
+ TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 21, x1, 3, \
+ li x1, 1; \
+ bltu x0, x1, 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# bne.S
+#-----------------------------------------------------------------------------
+#
+# Test bne instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Branch tests
+ #-------------------------------------------------------------
+
+ # Each test checks both forward and backward branches
+
+ TEST_BR2_OP_TAKEN( 2, bne, 0, 1 );
+ TEST_BR2_OP_TAKEN( 3, bne, 1, 0 );
+ TEST_BR2_OP_TAKEN( 4, bne, -1, 1 );
+ TEST_BR2_OP_TAKEN( 5, bne, 1, -1 );
+
+ TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 );
+ TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 );
+ TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 );
+
+ TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 );
+ TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 21, x1, 3, \
+ li x1, 1; \
+ bne x1, x0, 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# div.S
+#-----------------------------------------------------------------------------
+#
+# Test div instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, div, 3, 20, 6 );
+ TEST_RR_OP( 3, div, -3, -20, 6 );
+ TEST_RR_OP( 4, div, -3, 20, -6 );
+ TEST_RR_OP( 5, div, 3, -20, -6 );
+
+ TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 );
+ TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 );
+
+ TEST_RR_OP( 8, div, -1, -1<<63, 0 );
+ TEST_RR_OP( 9, div, -1, 1, 0 );
+ TEST_RR_OP(10, div, -1, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# divu.S
+#-----------------------------------------------------------------------------
+#
+# Test divu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, divu, 3, 20, 6 );
+ TEST_RR_OP( 3, divu, 715827879, -20, 6 );
+ TEST_RR_OP( 4, divu, 0, 20, -6 );
+ TEST_RR_OP( 5, divu, 0, -20, -6 );
+
+ TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 );
+ TEST_RR_OP( 7, divu, 0, -1<<31, -1 );
+
+ TEST_RR_OP( 8, divu, -1, -1<<31, 0 );
+ TEST_RR_OP( 9, divu, -1, 1, 0 );
+ TEST_RR_OP(10, divu, -1, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# divuw.S
+#-----------------------------------------------------------------------------
+#
+# Test divuw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, divuw, 3, 20, 6 );
+ TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 );
+ TEST_RR_OP( 4, divuw, 0, 20, -6 );
+ TEST_RR_OP( 5, divuw, 0, -20, -6 );
+
+ TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 );
+ TEST_RR_OP( 7, divuw, 0, -1<<31, -1 );
+
+ TEST_RR_OP( 8, divuw, -1, -1<<31, 0 );
+ TEST_RR_OP( 9, divuw, -1, 1, 0 );
+ TEST_RR_OP(10, divuw, -1, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# divw.S
+#-----------------------------------------------------------------------------
+#
+# Test divw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, divw, 3, 20, 6 );
+ TEST_RR_OP( 3, divw, -3, -20, 6 );
+ TEST_RR_OP( 4, divw, -3, 20, -6 );
+ TEST_RR_OP( 5, divw, 3, -20, -6 );
+
+ TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 );
+ TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 );
+
+ TEST_RR_OP( 8, divw, -1, -1<<31, 0 );
+ TEST_RR_OP( 9, divw, -1, 1, 0 );
+ TEST_RR_OP(10, divw, -1, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# fence_i.S
+#-----------------------------------------------------------------------------
+#
+# Test self-modifying code and the fence.i instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+li a3, 111
+la a0, 3f
+la a1, 1f
+la a2, 2f
+lw a0, 0(a0)
+
+# test I$ hit
+.align 6
+sw a0, 0(a1)
+fence.i
+
+1: addi a3, a3, 222
+TEST_CASE( 2, a3, 444, nop )
+
+# test prefetcher hit
+li a4, 100
+1: addi a4, a4, -1
+bnez a4, 1b
+
+sw a0, 0(a2)
+fence.i
+
+.align 6
+2: addi a3, a3, 555
+TEST_CASE( 3, a3, 777, nop )
+
+3: addi a3, a3, 333
+
+TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# j.S
+#-----------------------------------------------------------------------------
+#
+# Test j instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Test basic
+ #-------------------------------------------------------------
+
+ li x28, 2;
+ j test_2;
+ j fail;
+test_2:
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 3, x1, 3, \
+ li x1, 1; \
+ j 1f; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# jal.S
+#-----------------------------------------------------------------------------
+#
+# Test jal instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Test 2: Basic test
+ #-------------------------------------------------------------
+
+test_2:
+ li x28, 2
+ li ra, 0
+
+linkaddr_2:
+ jal target_2
+ nop
+ nop
+
+ j fail
+
+target_2:
+ la x2, linkaddr_2
+ addi x2, x2, 4
+ bne x2, ra, fail
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 3, x2, 3, \
+ li x2, 1; \
+ jal 1f; \
+ addi x2, x2, 1; \
+ addi x2, x2, 1; \
+ addi x2, x2, 1; \
+ addi x2, x2, 1; \
+1: addi x2, x2, 1; \
+ addi x2, x2, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# jalr.S
+#-----------------------------------------------------------------------------
+#
+# Test jalr instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Test 2: Basic test
+ #-------------------------------------------------------------
+
+test_2:
+ li x28, 2
+ li x31, 0
+ la x2, target_2
+
+linkaddr_2:
+ jalr x19, x2, 0
+ nop
+ nop
+
+ j fail
+
+target_2:
+ la x1, linkaddr_2
+ addi x1, x1, 4
+ bne x1, x19, fail
+
+ #-------------------------------------------------------------
+ # Test 3: Check r0 target and that r31 is not modified
+ #-------------------------------------------------------------
+
+test_3:
+ li x28, 3
+ li x31, 0
+ la x3, target_3
+
+linkaddr_3:
+ jalr x0, x3, 0
+ nop
+
+ j fail
+
+target_3:
+ bne x31, x0, fail
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
+ TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
+ TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
+
+ #-------------------------------------------------------------
+ # Test delay slot instructions not executed nor bypassed
+ #-------------------------------------------------------------
+
+ TEST_CASE( 7, x1, 4, \
+ li x1, 1; \
+ la x2, 1f;
+ jalr x19, x2, -4; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ addi x1, x1, 1; \
+1: addi x1, x1, 1; \
+ addi x1, x1, 1; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# lb.S
+#-----------------------------------------------------------------------------
+#
+# Test lb instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, lb, 0xffffffff, 0, tdat );
+ TEST_LD_OP( 3, lb, 0x00000000, 1, tdat );
+ TEST_LD_OP( 4, lb, 0xfffffff0, 2, tdat );
+ TEST_LD_OP( 5, lb, 0x0000000f, 3, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, lb, 0xffffffff, -3, tdat4 );
+ TEST_LD_OP( 7, lb, 0x00000000, -2, tdat4 );
+ TEST_LD_OP( 8, lb, 0xfffffff0, -1, tdat4 );
+ TEST_LD_OP( 9, lb, 0x0000000f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x3, 0xffffffff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ lb x3, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x3, 0x00000000, \
+ la x1, tdat; \
+ addi x1, x1, -6; \
+ lb x3, 7(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffff0, 1, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, lb, 0x0000000f, 1, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, lb, 0x00000000, 1, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffff0, 1, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x0000000f, 1, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x00000000, 1, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x3, tdat; \
+ lb x2, 0(x3); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x3, tdat; \
+ lb x2, 0(x3); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .byte 0xff
+tdat2: .byte 0x00
+tdat3: .byte 0xf0
+tdat4: .byte 0x0f
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# lbu.S
+#-----------------------------------------------------------------------------
+#
+# Test lbu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, lbu, 0x000000ff, 0, tdat );
+ TEST_LD_OP( 3, lbu, 0x00000000, 1, tdat );
+ TEST_LD_OP( 4, lbu, 0x000000f0, 2, tdat );
+ TEST_LD_OP( 5, lbu, 0x0000000f, 3, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, lbu, 0x000000ff, -3, tdat4 );
+ TEST_LD_OP( 7, lbu, 0x00000000, -2, tdat4 );
+ TEST_LD_OP( 8, lbu, 0x000000f0, -1, tdat4 );
+ TEST_LD_OP( 9, lbu, 0x0000000f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x3, 0x000000ff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ lbu x3, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x3, 0x00000000, \
+ la x1, tdat; \
+ addi x1, x1, -6; \
+ lbu x3, 7(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x000000f0, 1, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x0000000f, 1, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x00000000, 1, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x000000f0, 1, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x0000000f, 1, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x00000000, 1, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x3, tdat; \
+ lbu x2, 0(x3); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x3, tdat; \
+ lbu x2, 0(x3); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .byte 0xff
+tdat2: .byte 0x00
+tdat3: .byte 0xf0
+tdat4: .byte 0x0f
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# ld.S
+#-----------------------------------------------------------------------------
+#
+# Test ld instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, ld, 0x00ff00ff, 0, tdat );
+ TEST_LD_OP( 3, ld, 0xff00ff00, 8, tdat );
+ TEST_LD_OP( 4, ld, 0x0ff00ff0, 16, tdat );
+ TEST_LD_OP( 5, ld, 0xf00ff00f, 24, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, ld, 0x00ff00ff, -24, tdat4 );
+ TEST_LD_OP( 7, ld, 0xff00ff00, -16, tdat4 );
+ TEST_LD_OP( 8, ld, 0x0ff00ff0, -8, tdat4 );
+ TEST_LD_OP( 9, ld, 0xf00ff00f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x3, 0x00ff00ff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ ld x3, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x3, 0xff00ff00, \
+ la x1, tdat; \
+ addi x1, x1, -3; \
+ ld x3, 11(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, ld, 0x0ff00ff0, 8, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, ld, 0xf00ff00f, 8, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, ld, 0xff00ff00, 8, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, ld, 0x0ff00ff0, 8, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, ld, 0xf00ff00f, 8, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, ld, 0xff00ff00, 8, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x3, tdat; \
+ ld x2, 0(x3); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x3, tdat; \
+ ld x2, 0(x3); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .dword 0x00ff00ff
+tdat2: .dword 0xff00ff00
+tdat3: .dword 0x0ff00ff0
+tdat4: .dword 0xf00ff00f
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# lh.S
+#-----------------------------------------------------------------------------
+#
+# Test lh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, lh, 0x000000ff, 0, tdat );
+ TEST_LD_OP( 3, lh, 0xffffff00, 2, tdat );
+ TEST_LD_OP( 4, lh, 0x00000ff0, 4, tdat );
+ TEST_LD_OP( 5, lh, 0xfffff00f, 6, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, lh, 0x000000ff, -6, tdat4 );
+ TEST_LD_OP( 7, lh, 0xffffff00, -4, tdat4 );
+ TEST_LD_OP( 8, lh, 0x00000ff0, -2, tdat4 );
+ TEST_LD_OP( 9, lh, 0xfffff00f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x3, 0x000000ff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ lh x3, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x3, 0xffffff00, \
+ la x1, tdat; \
+ addi x1, x1, -5; \
+ lh x3, 7(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, lh, 0x00000ff0, 2, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffff00f, 2, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffff00, 2, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x00000ff0, 2, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffff00f, 2, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffff00, 2, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x3, tdat; \
+ lh x2, 0(x3); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x3, tdat; \
+ lh x2, 0(x3); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .half 0x00ff
+tdat2: .half 0xff00
+tdat3: .half 0x0ff0
+tdat4: .half 0xf00f
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# lhu.S
+#-----------------------------------------------------------------------------
+#
+# Test lhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, lhu, 0x000000ff, 0, tdat );
+ TEST_LD_OP( 3, lhu, 0x0000ff00, 2, tdat );
+ TEST_LD_OP( 4, lhu, 0x00000ff0, 4, tdat );
+ TEST_LD_OP( 5, lhu, 0x0000f00f, 6, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, lhu, 0x000000ff, -6, tdat4 );
+ TEST_LD_OP( 7, lhu, 0x0000ff00, -4, tdat4 );
+ TEST_LD_OP( 8, lhu, 0x00000ff0, -2, tdat4 );
+ TEST_LD_OP( 9, lhu, 0x0000f00f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x3, 0x000000ff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ lhu x3, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x3, 0x0000ff00, \
+ la x1, tdat; \
+ addi x1, x1, -5; \
+ lhu x3, 7(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x00000ff0, 2, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x0000f00f, 2, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x0000ff00, 2, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x00000ff0, 2, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x0000f00f, 2, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x0000ff00, 2, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x3, tdat; \
+ lhu x2, 0(x3); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x3, tdat; \
+ lhu x2, 0(x3); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .half 0x00ff
+tdat2: .half 0xff00
+tdat3: .half 0x0ff0
+tdat4: .half 0xf00f
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# lrsr.S
+#-----------------------------------------------------------------------------
+#
+# Test LR/SC instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+# wait for all cores to boot
+la a0, coreid
+li a1, 1
+amoadd.w a2, a1, (a0)
+lw a3, 4(x0)
+1: lw a1, (a0)
+blt a1, a3, 1b
+
+# make sure that sc without a reservation fails.
+TEST_CASE( 2, a4, 1, \
+ la a0, foo; \
+ sc.w a4, x0, (a0); \
+)
+
+# make sure that sc with the wrong reservation fails.
+TEST_CASE( 3, a4, 1, \
+ la a0, foo; \
+ add a1, a0, 1024; \
+ lr.w a1, (a1); \
+ sc.w a4, a1, (a0); \
+)
+
+# have each core add its coreid to foo 1000 times
+la a0, foo
+li a1, 1000
+1: lr.w a4, (a0)
+add a4, a4, a2
+sc.w a4, a4, (a0)
+bnez a4, 1b
+add a1, a1, -1
+bnez a1, 1b
+
+# wait for all cores to finish
+la a0, barrier
+li a1, 1
+amoadd.w x0, a1, (a0)
+1: lw a1, (a0)
+blt a1, a3, 1b
+fence
+
+# expected result is 1000*ncores*(ncores-1)/2
+TEST_CASE( 4, a2, 0, \
+ la a0, foo; \
+ li a1, 500; \
+ mul a1, a1, a3; \
+ add a2, a3, -1; \
+ mul a1, a1, a2; \
+ lw a2, (a0); \
+ sub a2, a2, a1; \
+)
+
+TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+coreid: .word 0
+barrier: .word 0
+foo: .word 0
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# lui.S
+#-----------------------------------------------------------------------------
+#
+# Test lui instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_CASE( 2, x1, 0x00000000, lui x1, 0x00000 );
+ TEST_CASE( 3, x1, 0xfffff800, lui x1, 0xfffff;sra x1,x1,1);
+ TEST_CASE( 4, x1, 0x000007ff, lui x1, 0x7ffff;sra x1,x1,20);
+ TEST_CASE( 5, x1, 0xfffff800, lui x1, 0x80000;sra x1,x1,20);
+
+ TEST_CASE( 6, x0, 0, lui x0, 0x80000 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# lw.S
+#-----------------------------------------------------------------------------
+#
+# Test lw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, lw, 0x00ff00ff, 0, tdat );
+ TEST_LD_OP( 3, lw, 0xff00ff00, 4, tdat );
+ TEST_LD_OP( 4, lw, 0x0ff00ff0, 8, tdat );
+ TEST_LD_OP( 5, lw, 0xf00ff00f, 12, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, lw, 0x00ff00ff, -12, tdat4 );
+ TEST_LD_OP( 7, lw, 0xff00ff00, -8, tdat4 );
+ TEST_LD_OP( 8, lw, 0x0ff00ff0, -4, tdat4 );
+ TEST_LD_OP( 9, lw, 0xf00ff00f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x3, 0x00ff00ff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ lw x3, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x3, 0xff00ff00, \
+ la x1, tdat; \
+ addi x1, x1, -3; \
+ lw x3, 7(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, lw, 0x0ff00ff0, 4, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, lw, 0xf00ff00f, 4, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, lw, 0xff00ff00, 4, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x0ff00ff0, 4, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xf00ff00f, 4, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xff00ff00, 4, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x3, tdat; \
+ lw x2, 0(x3); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x3, tdat; \
+ lw x2, 0(x3); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .word 0x00ff00ff
+tdat2: .word 0xff00ff00
+tdat3: .word 0x0ff00ff0
+tdat4: .word 0xf00ff00f
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# lwu.S
+#-----------------------------------------------------------------------------
+#
+# Test lwu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_LD_OP( 2, lwu, 0x00ff00ff, 0, tdat );
+ TEST_LD_OP( 3, lwu, 0xff00ff00, 4, tdat );
+ TEST_LD_OP( 4, lwu, 0x0ff00ff0, 8, tdat );
+ TEST_LD_OP( 5, lwu, 0xf00ff00f, 12, tdat );
+
+ # Test with negative offset
+
+ TEST_LD_OP( 6, lwu, 0x00ff00ff, -12, tdat4 );
+ TEST_LD_OP( 7, lwu, 0xff00ff00, -8, tdat4 );
+ TEST_LD_OP( 8, lwu, 0x0ff00ff0, -4, tdat4 );
+ TEST_LD_OP( 9, lwu, 0xf00ff00f, 0, tdat4 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x3, 0x00ff00ff, \
+ la x1, tdat; \
+ addi x1, x1, -32; \
+ lwu x3, 32(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x3, 0xff00ff00, \
+ la x1, tdat; \
+ addi x1, x1, -3; \
+ lwu x3, 7(x1); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_LD_DEST_BYPASS( 12, 0, lwu, 0x0ff00ff0, 4, tdat2 );
+ TEST_LD_DEST_BYPASS( 13, 1, lwu, 0xf00ff00f, 4, tdat3 );
+ TEST_LD_DEST_BYPASS( 14, 2, lwu, 0xff00ff00, 4, tdat1 );
+
+ TEST_LD_SRC1_BYPASS( 15, 0, lwu, 0x0ff00ff0, 4, tdat2 );
+ TEST_LD_SRC1_BYPASS( 16, 1, lwu, 0xf00ff00f, 4, tdat3 );
+ TEST_LD_SRC1_BYPASS( 17, 2, lwu, 0xff00ff00, 4, tdat1 );
+
+ #-------------------------------------------------------------
+ # Test write-after-write hazard
+ #-------------------------------------------------------------
+
+ TEST_CASE( 18, x2, 2, \
+ la x3, tdat; \
+ lwu x2, 0(x3); \
+ li x2, 2; \
+ )
+
+ TEST_CASE( 19, x2, 2, \
+ la x3, tdat; \
+ lwu x2, 0(x3); \
+ nop; \
+ li x2, 2; \
+ )
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .word 0x00ff00ff
+tdat2: .word 0xff00ff00
+tdat3: .word 0x0ff00ff0
+tdat4: .word 0xf00ff00f
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# mul.S
+#-----------------------------------------------------------------------------
+#
+# Test mul instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
+ TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
+
+ TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 );
+
+ TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
+ TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
+ TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
+ TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
+ TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
+ TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
+
+ TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
+ TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
+ TEST_RR_ZEROSRC12( 28, mul, 0 );
+ TEST_RR_ZERODEST( 29, mul, 33, 34 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# mulh.S
+#-----------------------------------------------------------------------------
+#
+# Test mulh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 );
+ TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 );
+ TEST_RR_ZEROSRC12( 28, mulh, 0 );
+ TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# mulhsu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhsu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
+ TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
+ TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
+ TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
+
+
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# mulhu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
+
+ TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
+ TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
+ TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
+ TEST_RR_ZEROSRC12( 28, mulhu, 0 );
+ TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
+
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# mulw.S
+#-----------------------------------------------------------------------------
+#
+# Test mulw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulw, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulw, 0x00000001, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulw, 0x00000015, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulw, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mulw, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulw, 0x00000000, 0x80000000, 0xffff8000 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 );
+
+ TEST_RR_ZEROSRC1( 26, mulw, 0, 31 );
+ TEST_RR_ZEROSRC2( 27, mulw, 0, 32 );
+ TEST_RR_ZEROSRC12( 28, mulw, 0 );
+ TEST_RR_ZERODEST( 29, mulw, 33, 34 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# or.S
+#-----------------------------------------------------------------------------
+#
+# Test or instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Logical tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 9, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 );
+ TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff );
+ TEST_RR_ZEROSRC12( 26, or, 0 );
+ TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# ori.S
+#-----------------------------------------------------------------------------
+#
+# Test ori instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Logical tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, ori, 0xffffff0f, 0xff00ff00, 0xf0f );
+ TEST_IMM_OP( 3, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 );
+ TEST_IMM_OP( 4, ori, 0x00ff07ff, 0x00ff00ff, 0x70f );
+ TEST_IMM_OP( 5, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 7, 0, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 );
+ TEST_IMM_DEST_BYPASS( 8, 1, ori, 0x00ff07ff, 0x00ff00ff, 0x70f );
+ TEST_IMM_DEST_BYPASS( 9, 2, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
+
+ TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 );
+ TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffff, 0x00ff00ff, 0xf0f );
+ TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
+
+ TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 );
+ TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# rem.S
+#-----------------------------------------------------------------------------
+#
+# Test rem instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, rem, 2, 20, 6 );
+ TEST_RR_OP( 3, rem, -2, -20, 6 );
+ TEST_RR_OP( 4, rem, 2, 20, -6 );
+ TEST_RR_OP( 5, rem, -2, -20, -6 );
+
+ TEST_RR_OP( 6, rem, 0, -1<<63, 1 );
+ TEST_RR_OP( 7, rem, 0, -1<<63, -1 );
+
+ TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 );
+ TEST_RR_OP( 9, rem, 1, 1, 0 );
+ TEST_RR_OP(10, rem, 0, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# remu.S
+#-----------------------------------------------------------------------------
+#
+# Test remu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, remu, 2, 20, 6 );
+ TEST_RR_OP( 3, remu, 2, -20, 6 );
+ TEST_RR_OP( 4, remu, 20, 20, -6 );
+ TEST_RR_OP( 5, remu, -20, -20, -6 );
+
+ TEST_RR_OP( 6, remu, 0, -1<<63, 1 );
+ TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 );
+
+ TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 );
+ TEST_RR_OP( 9, remu, 1, 1, 0 );
+ TEST_RR_OP(10, remu, 0, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# sb.S
+#-----------------------------------------------------------------------------
+#
+# Test sb instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_ST_OP( 2, lb, sb, 0xffffffaa, 0, tdat );
+ TEST_ST_OP( 3, lb, sb, 0x00000000, 1, tdat );
+#ifdef __RISCVEL
+ TEST_ST_OP( 4, lh, sb, 0xffffefa0, 2, tdat );
+#elif defined(__RISCVEB)
+#else
+ TEST_ST_OP( 4, lh, sb, 0xffffa0ef, 2, tdat );
+#error unknown endianness!
+#endif
+ TEST_ST_OP( 5, lb, sb, 0x0000000a, 3, tdat );
+
+ # Test with negative offset
+
+ TEST_ST_OP( 6, lb, sb, 0xffffffaa, -3, tdat8 );
+ TEST_ST_OP( 7, lb, sb, 0x00000000, -2, tdat8 );
+ TEST_ST_OP( 8, lb, sb, 0xffffffa0, -1, tdat8 );
+ TEST_ST_OP( 9, lb, sb, 0x0000000a, 0, tdat8 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x3, 0x78, \
+ la x1, tdat9; \
+ li x2, 0x12345678; \
+ addi x4, x1, -32; \
+ sb x2, 32(x4); \
+ lb x3, 0(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x3, 0xffffff98, \
+ la x1, tdat9; \
+ li x2, 0x00003098; \
+ addi x1, x1, -6; \
+ sb x2, 7(x1); \
+ la x4, tdat10; \
+ lb x3, 0(x4); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffdd, 0, tdat );
+ TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffcd, 1, tdat );
+ TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffcc, 2, tdat );
+ TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffbc, 3, tdat );
+ TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffbb, 4, tdat );
+ TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffab, 5, tdat );
+
+ TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat );
+ TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat );
+ TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat );
+ TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat );
+ TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat );
+ TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat );
+
+ li a0, 0xef
+ la a1, tdat
+ sb a0, 3(a1)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .byte 0xef
+tdat2: .byte 0xef
+tdat3: .byte 0xef
+tdat4: .byte 0xef
+tdat5: .byte 0xef
+tdat6: .byte 0xef
+tdat7: .byte 0xef
+tdat8: .byte 0xef
+tdat9: .byte 0xef
+tdat10: .byte 0xef
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# sh.S
+#-----------------------------------------------------------------------------
+#
+# Test sh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_ST_OP( 2, lh, sh, 0x000000aa, 0, tdat );
+ TEST_ST_OP( 3, lh, sh, 0xffffaa00, 2, tdat );
+#ifdef __RISCVEL
+ TEST_ST_OP( 4, lw, sh, 0xbeef0aa0, 4, tdat );
+#elif defined(__RISCVEB)
+#else
+ TEST_ST_OP( 4, lw, sh, 0x0aa0beef, 4, tdat );
+#error unknown endianness!
+#endif
+ TEST_ST_OP( 5, lh, sh, 0xffffa00a, 6, tdat );
+
+ # Test with negative offset
+
+ TEST_ST_OP( 6, lh, sh, 0x000000aa, -6, tdat8 );
+ TEST_ST_OP( 7, lh, sh, 0xffffaa00, -4, tdat8 );
+ TEST_ST_OP( 8, lh, sh, 0x00000aa0, -2, tdat8 );
+ TEST_ST_OP( 9, lh, sh, 0xffffa00a, 0, tdat8 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x3, 0x5678, \
+ la x1, tdat9; \
+ li x2, 0x12345678; \
+ addi x4, x1, -32; \
+ sh x2, 32(x4); \
+ lh x3, 0(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x3, 0x3098, \
+ la x1, tdat9; \
+ li x2, 0x00003098; \
+ addi x1, x1, -5; \
+ sh x2, 7(x1); \
+ la x4, tdat10; \
+ lh x3, 0(x4); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffccdd, 0, tdat );
+ TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffbccd, 2, tdat );
+ TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffbbcc, 4, tdat );
+ TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffabbc, 6, tdat );
+ TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffaabb, 8, tdat );
+ TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffdaab, 10, tdat );
+
+ TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat );
+ TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat );
+ TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat );
+ TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat );
+ TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat );
+ TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat );
+
+ li a0, 0xbeef
+ la a1, tdat
+ sh a0, 6(a1)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .half 0xbeef
+tdat2: .half 0xbeef
+tdat3: .half 0xbeef
+tdat4: .half 0xbeef
+tdat5: .half 0xbeef
+tdat6: .half 0xbeef
+tdat7: .half 0xbeef
+tdat8: .half 0xbeef
+tdat9: .half 0xbeef
+tdat10: .half 0xbeef
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# sll.S
+#-----------------------------------------------------------------------------
+#
+# Test sll instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, sll, 0x00000001, 0x00000001, 0 );
+ TEST_RR_OP( 3, sll, 0x00000002, 0x00000001, 1 );
+ TEST_RR_OP( 4, sll, 0x00000080, 0x00000001, 7 );
+ TEST_RR_OP( 5, sll, 0x00004000, 0x00000001, 14 );
+ TEST_RR_OP( 6, sll, 0x80000000, 0x00000001, 31 );
+
+ TEST_RR_OP( 7, sll, 0xffffffff, 0xffffffff, 0 );
+ TEST_RR_OP( 8, sll, 0xfffffffe, 0xffffffff, 1 );
+ TEST_RR_OP( 9, sll, 0xffffff80, 0xffffffff, 7 );
+ TEST_RR_OP( 10, sll, 0xffffc000, 0xffffffff, 14 );
+ TEST_RR_OP( 11, sll, 0x80000000, 0xffffffff, 31 );
+
+ TEST_RR_OP( 12, sll, 0x21212121, 0x21212121, 0 );
+ TEST_RR_OP( 13, sll, 0x42424242, 0x21212121, 1 );
+ TEST_RR_OP( 14, sll, 0x90909080, 0x21212121, 7 );
+ TEST_RR_OP( 15, sll, 0x48484000, 0x21212121, 14 );
+ TEST_RR_OP( 16, sll, 0x80000000, 0x21212121, 31 );
+
+ # Verify that shifts only use bottom five bits
+
+ TEST_RR_OP( 17, sll, 0x21212121, 0x21212121, 0xffffffe0 );
+ TEST_RR_OP( 18, sll, 0x42424242, 0x21212121, 0xffffffe1 );
+ TEST_RR_OP( 19, sll, 0x90909080, 0x21212121, 0xffffffe7 );
+ TEST_RR_OP( 20, sll, 0x48484000, 0x21212121, 0xffffffee );
+ TEST_RR_OP( 21, sll, 0x00000000, 0x21212120, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 );
+ TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 );
+ TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 25, 0, sll, 0x00000080, 0x00000001, 7 );
+ TEST_RR_DEST_BYPASS( 26, 1, sll, 0x00004000, 0x00000001, 14 );
+ TEST_RR_DEST_BYPASS( 27, 2, sll, 0x80000000, 0x00000001, 31 );
+
+ TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x00000080, 0x00000001, 7 );
+ TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x00004000, 0x00000001, 14 );
+ TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x80000000, 0x00000001, 31 );
+ TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x00000080, 0x00000001, 7 );
+ TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x00004000, 0x00000001, 14 );
+ TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x80000000, 0x00000001, 31 );
+
+ TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x00000080, 0x00000001, 7 );
+ TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x00004000, 0x00000001, 14 );
+ TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x80000000, 0x00000001, 31 );
+ TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x00000080, 0x00000001, 7 );
+ TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x00004000, 0x00000001, 14 );
+ TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x80000000, 0x00000001, 31 );
+
+ TEST_RR_ZEROSRC1( 40, sll, 0, 15 );
+ TEST_RR_ZEROSRC2( 41, sll, 32, 32 );
+ TEST_RR_ZEROSRC12( 42, sll, 0 );
+ TEST_RR_ZERODEST( 43, sll, 1024, 2048 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# slli.S
+#-----------------------------------------------------------------------------
+#
+# Test slli instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, slli, 0x00000001, 0x00000001, 0 );
+ TEST_IMM_OP( 3, slli, 0x00000002, 0x00000001, 1 );
+ TEST_IMM_OP( 4, slli, 0x00000080, 0x00000001, 7 );
+ TEST_IMM_OP( 5, slli, 0x00004000, 0x00000001, 14 );
+ TEST_IMM_OP( 6, slli, 0x80000000, 0x00000001, 31 );
+
+ TEST_IMM_OP( 7, slli, 0xffffffff, 0xffffffff, 0 );
+ TEST_IMM_OP( 8, slli, 0xfffffffe, 0xffffffff, 1 );
+ TEST_IMM_OP( 9, slli, 0xffffff80, 0xffffffff, 7 );
+ TEST_IMM_OP( 10, slli, 0xffffc000, 0xffffffff, 14 );
+ TEST_IMM_OP( 11, slli, 0x80000000, 0xffffffff, 31 );
+
+ TEST_IMM_OP( 12, slli, 0x21212121, 0x21212121, 0 );
+ TEST_IMM_OP( 13, slli, 0x42424242, 0x21212121, 1 );
+ TEST_IMM_OP( 14, slli, 0x90909080, 0x21212121, 7 );
+ TEST_IMM_OP( 15, slli, 0x48484000, 0x21212121, 14 );
+ TEST_IMM_OP( 16, slli, 0x80000000, 0x21212121, 31 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x00000080, 0x00000001, 7 );
+ TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x00004000, 0x00000001, 14 );
+ TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x80000000, 0x00000001, 31 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x00000080, 0x00000001, 7 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x00004000, 0x00000001, 14 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x80000000, 0x00000001, 31 );
+
+ TEST_IMM_ZEROSRC1( 24, slli, 0, 31 );
+ TEST_IMM_ZERODEST( 25, slli, 33, 20 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# slt.S
+#-----------------------------------------------------------------------------
+#
+# Test slt instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, slt, 0, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, slt, 0, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, slt, 1, 0x00000003, 0x00000007 );
+ TEST_RR_OP( 5, slt, 0, 0x00000007, 0x00000003 );
+
+ TEST_RR_OP( 6, slt, 0, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 7, slt, 1, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 8, slt, 1, 0x80000000, 0xffff8000 );
+
+ TEST_RR_OP( 9, slt, 1, 0x00000000, 0x00007fff );
+ TEST_RR_OP( 10, slt, 0, 0x7fffffff, 0x00000000 );
+ TEST_RR_OP( 11, slt, 0, 0x7fffffff, 0x00007fff );
+
+ TEST_RR_OP( 12, slt, 1, 0x80000000, 0x00007fff );
+ TEST_RR_OP( 13, slt, 0, 0x7fffffff, 0xffff8000 );
+
+ TEST_RR_OP( 14, slt, 0, 0x00000000, 0xffffffff );
+ TEST_RR_OP( 15, slt, 1, 0xffffffff, 0x00000001 );
+ TEST_RR_OP( 16, slt, 0, 0xffffffff, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 );
+ TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 );
+ TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 );
+ TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 );
+ TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 );
+
+ TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 );
+ TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 );
+ TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 );
+ TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 );
+ TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 );
+ TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1, 9, 13 );
+
+ TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 );
+ TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1, 8, 13 );
+ TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 );
+ TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1, 7, 13 );
+ TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 );
+ TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1, 6, 13 );
+
+ TEST_RR_ZEROSRC1( 35, slt, 0, -1 );
+ TEST_RR_ZEROSRC2( 36, slt, 1, -1 );
+ TEST_RR_ZEROSRC12( 37, slt, 0 );
+ TEST_RR_ZERODEST( 38, slt, 16, 30 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# slti.S
+#-----------------------------------------------------------------------------
+#
+# Test slti instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, slti, 0, 0x00000000, 0x000 );
+ TEST_IMM_OP( 3, slti, 0, 0x00000001, 0x001 );
+ TEST_IMM_OP( 4, slti, 1, 0x00000003, 0x007 );
+ TEST_IMM_OP( 5, slti, 0, 0x00000007, 0x003 );
+
+ TEST_IMM_OP( 6, slti, 0, 0x00000000, 0x800 );
+ TEST_IMM_OP( 7, slti, 1, 0x80000000, 0x000 );
+ TEST_IMM_OP( 8, slti, 1, 0x80000000, 0x800 );
+
+ TEST_IMM_OP( 9, slti, 1, 0x00000000, 0x7ff );
+ TEST_IMM_OP( 10, slti, 0, 0x7fffffff, 0x000 );
+ TEST_IMM_OP( 11, slti, 0, 0x7fffffff, 0x7ff );
+
+ TEST_IMM_OP( 12, slti, 1, 0x80000000, 0x7ff );
+ TEST_IMM_OP( 13, slti, 0, 0x7fffffff, 0x800 );
+
+ TEST_IMM_OP( 14, slti, 0, 0x00000000, 0xfff );
+ TEST_IMM_OP( 15, slti, 1, 0xffffffff, 0x001 );
+ TEST_IMM_OP( 16, slti, 0, 0xffffffff, 0xfff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 );
+ TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 );
+ TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16, 9 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17, 8 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 );
+
+ TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff );
+ TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# sra.S
+#-----------------------------------------------------------------------------
+#
+# Test sra instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, sra, 0x80000000, 0x80000000, 0 );
+ TEST_RR_OP( 3, sra, 0xc0000000, 0x80000000, 1 );
+ TEST_RR_OP( 4, sra, 0xff000000, 0x80000000, 7 );
+ TEST_RR_OP( 5, sra, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_OP( 6, sra, 0xffffffff, 0x80000001, 31 );
+
+ TEST_RR_OP( 7, sra, 0x7fffffff, 0x7fffffff, 0 );
+ TEST_RR_OP( 8, sra, 0x3fffffff, 0x7fffffff, 1 );
+ TEST_RR_OP( 9, sra, 0x00ffffff, 0x7fffffff, 7 );
+ TEST_RR_OP( 10, sra, 0x0001ffff, 0x7fffffff, 14 );
+ TEST_RR_OP( 11, sra, 0x00000000, 0x7fffffff, 31 );
+
+ TEST_RR_OP( 12, sra, 0x81818181, 0x81818181, 0 );
+ TEST_RR_OP( 13, sra, 0xc0c0c0c0, 0x81818181, 1 );
+ TEST_RR_OP( 14, sra, 0xff030303, 0x81818181, 7 );
+ TEST_RR_OP( 15, sra, 0xfffe0606, 0x81818181, 14 );
+ TEST_RR_OP( 16, sra, 0xffffffff, 0x81818181, 31 );
+
+ # Verify that shifts only use bottom five bits
+
+ TEST_RR_OP( 17, sra, 0x81818181, 0x81818181, 0xffffffc0 );
+ TEST_RR_OP( 18, sra, 0xc0c0c0c0, 0x81818181, 0xffffffc1 );
+ TEST_RR_OP( 19, sra, 0xff030303, 0x81818181, 0xffffffc7 );
+ TEST_RR_OP( 20, sra, 0xfffe0606, 0x81818181, 0xffffffce );
+ TEST_RR_OP( 21, sra, 0xffffffff, 0x81818181, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 22, sra, 0xff000000, 0x80000000, 7 );
+ TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 25, 0, sra, 0xff000000, 0x80000000, 7 );
+ TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffff, 0x80000000, 31 );
+
+ TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xff000000, 0x80000000, 7 );
+ TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffff, 0x80000000, 31 );
+ TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xff000000, 0x80000000, 7 );
+ TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffff, 0x80000000, 31 );
+
+ TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xff000000, 0x80000000, 7 );
+ TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffff, 0x80000000, 31 );
+ TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xff000000, 0x80000000, 7 );
+ TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffff, 0x80000000, 31 );
+
+ TEST_RR_ZEROSRC1( 40, sra, 0, 15 );
+ TEST_RR_ZEROSRC2( 41, sra, 32, 32 );
+ TEST_RR_ZEROSRC12( 42, sra, 0 );
+ TEST_RR_ZERODEST( 43, sra, 1024, 2048 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# srai.S
+#-----------------------------------------------------------------------------
+#
+# Test srai instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, srai, 0x00000000, 0x00000000, 0 );
+ TEST_IMM_OP( 3, srai, 0xc0000000, 0x80000000, 1 );
+ TEST_IMM_OP( 4, srai, 0xff000000, 0x80000000, 7 );
+ TEST_IMM_OP( 5, srai, 0xfffe0000, 0x80000000, 14 );
+ TEST_IMM_OP( 6, srai, 0xffffffff, 0x80000001, 31 );
+
+ TEST_IMM_OP( 7, srai, 0x7fffffff, 0x7fffffff, 0 );
+ TEST_IMM_OP( 8, srai, 0x3fffffff, 0x7fffffff, 1 );
+ TEST_IMM_OP( 9, srai, 0x00ffffff, 0x7fffffff, 7 );
+ TEST_IMM_OP( 10, srai, 0x0001ffff, 0x7fffffff, 14 );
+ TEST_IMM_OP( 11, srai, 0x00000000, 0x7fffffff, 31 );
+
+ TEST_IMM_OP( 12, srai, 0x81818181, 0x81818181, 0 );
+ TEST_IMM_OP( 13, srai, 0xc0c0c0c0, 0x81818181, 1 );
+ TEST_IMM_OP( 14, srai, 0xff030303, 0x81818181, 7 );
+ TEST_IMM_OP( 15, srai, 0xfffe0606, 0x81818181, 14 );
+ TEST_IMM_OP( 16, srai, 0xffffffff, 0x81818181, 31 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xff000000, 0x80000000, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xff000000, 0x80000000, 7 );
+ TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffe0000, 0x80000000, 14 );
+ TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffff, 0x80000001, 31 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xff000000, 0x80000000, 7 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffe0000, 0x80000000, 14 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffff, 0x80000001, 31 );
+
+ TEST_IMM_ZEROSRC1( 24, srai, 0, 32 );
+ TEST_IMM_ZERODEST( 25, srai, 33, 50 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# srl.S
+#-----------------------------------------------------------------------------
+#
+# Test srl instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, srl, 0x80000000, 0x80000000, 0 );
+ TEST_RR_OP( 3, srl, 0xc0000000, 0x80000000, 1 );
+ TEST_RR_OP( 4, srl, 0xff000000, 0x80000000, 7 );
+ TEST_RR_OP( 5, srl, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_OP( 6, srl, 0xffffffff, 0x80000001, 31 );
+
+ TEST_RR_OP( 7, srl, 0xffffffff, 0xffffffff, 0 );
+ TEST_RR_OP( 8, srl, 0xffffffff, 0xffffffff, 1 );
+ TEST_RR_OP( 9, srl, 0xffffffff, 0xffffffff, 7 );
+ TEST_RR_OP( 10, srl, 0xffffffff, 0xffffffff, 14 );
+ TEST_RR_OP( 11, srl, 0xffffffff, 0xffffffff, 31 );
+
+ TEST_RR_OP( 12, srl, 0x21212121, 0x21212121, 0 );
+ TEST_RR_OP( 13, srl, 0x10909090, 0x21212121, 1 );
+ TEST_RR_OP( 14, srl, 0x00424242, 0x21212121, 7 );
+ TEST_RR_OP( 15, srl, 0x00008484, 0x21212121, 14 );
+ TEST_RR_OP( 16, srl, 0x00000000, 0x21212121, 31 );
+
+ # Verify that shifts only use bottom five bits
+
+ TEST_RR_OP( 17, srl, 0x21212121, 0x21212121, 0xffffffc0 );
+ TEST_RR_OP( 18, srl, 0x10909090, 0x21212121, 0xffffffc1 );
+ TEST_RR_OP( 19, srl, 0x00424242, 0x21212121, 0xffffffc7 );
+ TEST_RR_OP( 20, srl, 0x00008484, 0x21212121, 0xffffffce );
+ TEST_RR_OP( 21, srl, 0x00000000, 0x21212121, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 22, srl, 0xff000000, 0x80000000, 7 );
+ TEST_RR_SRC2_EQ_DEST( 23, srl, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 25, 0, srl, 0xff000000, 0x80000000, 7 );
+ TEST_RR_DEST_BYPASS( 26, 1, srl, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_DEST_BYPASS( 27, 2, srl, 0xffffffff, 0x80000000, 31 );
+
+ TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0xff000000, 0x80000000, 7 );
+ TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0xffffffff, 0x80000000, 31 );
+ TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0xff000000, 0x80000000, 7 );
+ TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0xffffffff, 0x80000000, 31 );
+
+ TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0xff000000, 0x80000000, 7 );
+ TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0xffffffff, 0x80000000, 31 );
+ TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0xff000000, 0x80000000, 7 );
+ TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0xfffe0000, 0x80000000, 14 );
+ TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0xffffffff, 0x80000000, 31 );
+
+ TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
+ TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
+ TEST_RR_ZEROSRC12( 42, srl, 0 );
+ TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# srli.S
+#-----------------------------------------------------------------------------
+#
+# Test srli instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, srli, 0x80000000, 0x80000000, 0 );
+ TEST_IMM_OP( 3, srli, 0xc0000000, 0x80000000, 1 );
+ TEST_IMM_OP( 4, srli, 0xff000000, 0x80000000, 7 );
+ TEST_IMM_OP( 5, srli, 0xfffe0000, 0x80000000, 14 );
+ TEST_IMM_OP( 6, srli, 0xffffffff, 0x80000001, 31 );
+
+ TEST_IMM_OP( 7, srli, 0xffffffff, 0xffffffff, 0 );
+ TEST_IMM_OP( 8, srli, 0xffffffff, 0xffffffff, 1 );
+ TEST_IMM_OP( 9, srli, 0xffffffff, 0xffffffff, 7 );
+ TEST_IMM_OP( 10, srli, 0xffffffff, 0xffffffff, 14 );
+ TEST_IMM_OP( 11, srli, 0xffffffff, 0xffffffff, 31 );
+
+ TEST_IMM_OP( 12, srli, 0x21212121, 0x21212121, 0 );
+ TEST_IMM_OP( 13, srli, 0x10909090, 0x21212121, 1 );
+ TEST_IMM_OP( 14, srli, 0x00424242, 0x21212121, 7 );
+ TEST_IMM_OP( 15, srli, 0x00008484, 0x21212121, 14 );
+ TEST_IMM_OP( 16, srli, 0x00000000, 0x21212121, 31 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, srli, 0xff000000, 0x80000000, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, srli, 0xff000000, 0x80000000, 7 );
+ TEST_IMM_DEST_BYPASS( 19, 1, srli, 0xfffe0000, 0x80000000, 14 );
+ TEST_IMM_DEST_BYPASS( 20, 2, srli, 0xffffffff, 0x80000001, 31 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0xff000000, 0x80000000, 7 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0xfffe0000, 0x80000000, 14 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0xffffffff, 0x80000001, 31 );
+
+ TEST_IMM_ZEROSRC1( 24, srli, 0, 32 );
+ TEST_IMM_ZERODEST( 25, srli, 33, 50 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# sub.S
+#-----------------------------------------------------------------------------
+#
+# Test sub instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, sub, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, sub, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, sub, 0xfffffffc, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, sub, 0x00008000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, sub, 0x80000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, sub, 0x80008000, 0x80000000, 0xffff8000 );
+
+ TEST_RR_OP( 8, sub, 0xffff8001, 0x00000000, 0x00007fff );
+ TEST_RR_OP( 9, sub, 0x7fffffff, 0x7fffffff, 0x00000000 );
+ TEST_RR_OP( 10, sub, 0x7fff8000, 0x7fffffff, 0x00007fff );
+
+ TEST_RR_OP( 11, sub, 0x7fff8001, 0x80000000, 0x00007fff );
+ TEST_RR_OP( 12, sub, 0x80007fff, 0x7fffffff, 0xffff8000 );
+
+ TEST_RR_OP( 13, sub, 0x00000001, 0x00000000, 0xffffffff );
+ TEST_RR_OP( 14, sub, 0xfffffffe, 0xffffffff, 0x00000001 );
+ TEST_RR_OP( 15, sub, 0x00000000, 0xffffffff, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 );
+ TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 );
+ TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 );
+ TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 );
+ TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 );
+
+ TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 );
+ TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 );
+
+ TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 );
+ TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 );
+
+ TEST_RR_ZEROSRC1( 34, sub, 15, -15 );
+ TEST_RR_ZEROSRC2( 35, sub, 32, 32 );
+ TEST_RR_ZEROSRC12( 36, sub, 0 );
+ TEST_RR_ZERODEST( 37, sub, 16, 30 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# sw.S
+#-----------------------------------------------------------------------------
+#
+# Test sw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Basic tests
+ #-------------------------------------------------------------
+
+ TEST_ST_OP( 2, lw, sw, 0x00aa00aa, 0, tdat );
+ TEST_ST_OP( 3, lw, sw, 0xaa00aa00, 4, tdat );
+ TEST_ST_OP( 4, lw, sw, 0x0aa00aa0, 8, tdat );
+ TEST_ST_OP( 5, lw, sw, 0xa00aa00a, 12, tdat );
+
+ # Test with negative offset
+
+ TEST_ST_OP( 6, lw, sw, 0x00aa00aa, -12, tdat8 );
+ TEST_ST_OP( 7, lw, sw, 0xaa00aa00, -8, tdat8 );
+ TEST_ST_OP( 8, lw, sw, 0x0aa00aa0, -4, tdat8 );
+ TEST_ST_OP( 9, lw, sw, 0xa00aa00a, 0, tdat8 );
+
+ # Test with a negative base
+
+ TEST_CASE( 10, x3, 0x12345678, \
+ la x1, tdat9; \
+ li x2, 0x12345678; \
+ addi x4, x1, -32; \
+ sw x2, 32(x4); \
+ lw x3, 0(x1); \
+ )
+
+ # Test with unaligned base
+
+ TEST_CASE( 11, x3, 0x58213098, \
+ la x1, tdat9; \
+ li x2, 0x58213098; \
+ addi x1, x1, -3; \
+ sw x2, 7(x1); \
+ la x4, tdat10; \
+ lw x3, 0(x4); \
+ )
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xaabbccdd, 0, tdat );
+ TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xdaabbccd, 4, tdat );
+ TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xddaabbcc, 8, tdat );
+ TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xcddaabbc, 12, tdat );
+ TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xccddaabb, 16, tdat );
+ TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xbccddaab, 20, tdat );
+
+ TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0, tdat );
+ TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4, tdat );
+ TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8, tdat );
+ TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat );
+ TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat );
+ TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+tdat:
+tdat1: .word 0xdeadbeef
+tdat2: .word 0xdeadbeef
+tdat3: .word 0xdeadbeef
+tdat4: .word 0xdeadbeef
+tdat5: .word 0xdeadbeef
+tdat6: .word 0xdeadbeef
+tdat7: .word 0xdeadbeef
+tdat8: .word 0xdeadbeef
+tdat9: .word 0xdeadbeef
+tdat10: .word 0xdeadbeef
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# xor.S
+#-----------------------------------------------------------------------------
+#
+# Test xor instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Logical tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 9, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+ TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+ TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+ TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 );
+ TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff );
+ TEST_RR_ZEROSRC12( 26, xor, 0 );
+ TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#*****************************************************************************
+# xori.S
+#-----------------------------------------------------------------------------
+#
+# Test xori instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Logical tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, xori, 0xff00f00f, 0x00ff0f00, 0xf0f );
+ TEST_IMM_OP( 3, xori, 0x0ff00f00, 0x0ff00ff0, 0x0f0 );
+ TEST_IMM_OP( 4, xori, 0x00ff0ff0, 0x00ff08ff, 0x70f );
+ TEST_IMM_OP( 5, xori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xff00f00f, 0xff00f700, 0x70f );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 7, 0, xori, 0x0ff00f00, 0x0ff00ff0, 0x0f0 );
+ TEST_IMM_DEST_BYPASS( 8, 1, xori, 0x00ff0ff0, 0x00ff08ff, 0x70f );
+ TEST_IMM_DEST_BYPASS( 9, 2, xori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
+
+ TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x0ff00f00, 0x0ff00ff0, 0x0f0 );
+ TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x00ff0ff0, 0x00ff0fff, 0x00f );
+ TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
+
+ TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 );
+ TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
projects / riscv-tests.git / commitdiff