(no commit message)

diff --git a/nlnet_2023_svp64_riscv.mdwn b/nlnet_2023_svp64_riscv.mdwn
index 1298c3cc850ba0f5b3e8a2f3fc400f969ccaa795..f385defe998719b012276b4f6fa647daf15671a0 100644 (file)
--- a/nlnet_2023_svp64_riscv.mdwn
+++ b/nlnet_2023_svp64_riscv.mdwn
@@ -55,6 +55,8 @@ EUR 100,000.
   modernising the work already done four years ago under
   NLnet Grant 2019-10-012 <https://libre-soc.org/nlnet_2018/>
 * Implementing Simple-V in the Libre-SOC Simulator, ISACaller.
+* Assembler and disassembler of RISC-V instructions and also
+  SVP64 in the Libre-SOC infrastructure.
 * Upgrading sv-spike which was completed four years ago with
   an early prototype Simple-V Specification
   <https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv>