back.rtlil: explicitly pad constants with zeroes.

I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 433dd2060bc9b399551f5ed102d71a13f196e145..0b61268481be820024c6fee54eedcc0e670dd5a1 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -353,7 +353,7 @@ class _RHSValueCompiler(_ValueCompiler):
         if isinstance(value.value, str):
             return "{}'{}".format(value.nbits, value.value)
         else:
-            return "{}'{:b}".format(value.nbits, value.value)
+            return "{}'{:0{}b}".format(value.nbits, value.value, value.nbits)
 
     def on_Signal(self, value):
         wire_curr, wire_next = self.s.resolve(value)