(no commit message)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index eca3eeaca2d229cd39c2799eb7f75fc981220674..3c94ca182b10092bd011ea8f00f62165762da8a6 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -52,7 +52,7 @@ actual Vector ISA it introduces over 1.5 million 64-bit True-Scalable
 Vector instructions on the SFFS Subset and closer to 10 million 64-bit
 True-Scalable Vector instructions if introduced on VSX.  SVP64, the
 instruction format used by Simple-V, is therefore best viewed as an
-orthogonal RISC-paradigm "Prefixing" subsystem instead.
+orthogonal RISC-paradigm "Loop Prefixing" subsystem instead.
 
 [^bib_ldir]:  [Zilog Z80 LDIR](http://z80-heaven.wikidot.com/instructions-set:ldir)
 [^bib_cpir]:  [Zilog Z80 CPIR](http://z80-heaven.wikidot.com/instructions-set:cpir)