ARM: Get rid of unused postacc_code.

diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index 0c736f947337c5fd8d654e36dedcd8f24fd552bb..df1d067dce20812421280a2ea1e8ca7fe7876c46 100644 (file)
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -357,20 +357,12 @@ def template StoreMemAccExecute {{
         {
             EA = xc->getEA();
 
-            if (fault == NoFault) {
-                %(postacc_code)s;
-            }
-
             if (fault == NoFault) {
                 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                                   memAccessFlags, NULL);
                 if (traceData) { traceData->setData(Mem); }
             }
 
-            if (fault == NoFault) {
-                %(postacc_code)s;
-            }
-
             if (fault == NoFault) {
                 %(op_wb)s;
             }
@@ -405,10 +397,6 @@ def template StoreExecute {{
                 if (traceData) { traceData->setData(Mem); }
             }
 
-            if (fault == NoFault) {
-                %(postacc_code)s;
-            }
-
             if (fault == NoFault) {
                 %(op_wb)s;
             }
@@ -465,10 +453,6 @@ def template StoreCompleteAcc {{
 
         if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
         {
-            if (fault == NoFault) {
-                %(postacc_code)s;
-            }
-
             if (fault == NoFault) {
                 %(op_wb)s;
             }
@@ -490,10 +474,6 @@ def template StoreCondCompleteAcc {{
 
         if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
         {
-            if (fault == NoFault) {
-                %(postacc_code)s;
-            }
-
             if (fault == NoFault) {
                 %(op_wb)s;
             }

diff --git a/src/arch/arm/isa/formats/util.isa b/src/arch/arm/isa/formats/util.isa
index ee6339c0203dea8071391a40cebeec00dce275f0..354f936d74c847fda6195acdc0a4c6ab77e2621e 100644 (file)
--- a/src/arch/arm/isa/formats/util.isa
+++ b/src/arch/arm/isa/formats/util.isa
@@ -39,7 +39,7 @@ def ArmGenericCodeSubs(code):
     return new_code
 
 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-                  postacc_code = '', base_class = 'Memory',
+                  base_class = 'Memory',
                   decode_template = BasicDecode, exec_template_base = ''):
     # Make sure flags are in lists (convert to lists if not).
     mem_flags = makeList(mem_flags)
@@ -58,13 +58,13 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
     # they differ only in the set of code objects contained (which in
     # turn affects the object's overall operand list).
     iop = InstObjParams(name, Name, base_class,
-                        { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
+                        { 'ea_code':ea_code, 'memacc_code':memacc_code},
                         inst_flags)
     ea_iop = InstObjParams(name, Name, base_class,
                         { 'ea_code':ea_code },
                         inst_flags)
     memacc_iop = InstObjParams(name, Name, base_class,
-                        { 'memacc_code':memacc_code, 'postacc_code':postacc_code },
+                        { 'memacc_code':memacc_code},
                         inst_flags)
 
     if mem_flags: