The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding is
defined in the Prefix Fields section.
-## Remapped Encoding Fields
++## Twin Predication
+
+ There are two different encodings: single-predication (typically arithmetic operations i.e. with more than one source register) and twin-predication (one source, one destination). They require different encodings
+
-Single Predication (2+ src ops):
-
-| Remapped Encoding Field Name | Field bits | Description |
-|------------------------------|------------|----------------|
-| MASKMODE | `0` | Predicate Mode |
-| MASK | `1:3` | Execution Mask |
-| TBD | `4:23` | TBD |
-
-Twin Predication (1 src, 1 dest):
-
-| Remapped Encoding Field Name | Field bits | Description |
-|------------------------------|------------|----------------|
-| MASKMODE | `0` | Predicate Mode |
-| SRCMASK | `1:3` | Source Mask |
-| DSTMASK | `4:6` | Dest Mask |
-| TBD | `7:23` | TBD |
+## Remapped Encoding Fields
-## Predicate MASK Encoding
+| Remapped Encoding Field Name | Field bits | Description |
+|------------------------------|------------|------------------------------------------------------------------------|
+| MASK_KIND | `0` | Execution Mask Kind |
+| MASK | `1:3` | Execution Mask |
+| ELWIDTH | `4:5` | Element Width |
+| SUBVL | `6:7` | Sub-vector length |
+| TBD | `8:23` | TBD |
+| MASK_SRC | TBD | Execution Mask for Source (only on instructions with twin-predication) |
+
+## ELWIDTH Encoding
+
+| Instruction Kind | ELWIDTH Value | Mnemonic | Description |
+|------------------|---------------|---------------------------|-------------------------------------------------------------------------------------|
+| Integer | 00 | `ELWIDTH=b` | Byte: 8-bit integer |
+| Integer | 01 | `ELWIDTH=h` | Halfword: 16-bit integer |
+| Integer | 10 | `ELWIDTH=w` | Word: 32-bit integer |
+| Integer | 11 | `ELWIDTH=d` | Doubleword: 64-bit integer |
+| FP | 00 | `ELWIDTH=bf16` (Reserved) | Reserved for [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format) |
+| FP | 01 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point |
+| FP | 10 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point |
+| FP | 11 | `ELWIDTH=f64` | 64-bit IEEE 754 Double floating-point |
+
+## SUBVL Encoding
+
+| SUBVL Value | Mnemonic | Description |
+|-------------|---------------------|------------------------|
+| 00 | `SUBVL=4` | Sub-vector length of 4 |
+| 01 | `SUBVL=1` (default) | Sub-vector length of 1 |
+| 10 | `SUBVL=2` | Sub-vector length of 2 |
+| 11 | `SUBVL=3` | Sub-vector length of 3 |
+
+## MASK/MASK_SRC & MASK_KIND Encoding
- One bit indicates the mode: CR or Int predication. The two types may not be mixed.
+ One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two types may not be mixed.
+| MASK_KIND Value | Description |
+|-----------------|------------------------------------------------------|
+| 0 | MASK/MASK_SRC are encoded using Integer Predication |
+| 1 | MASK/MASK_SRC are encoded using CR-based Predication |
+
Integer Twin predication has a second set if 3 bits that uses the same encoding thus allowing either the same register (r3 or r10) to be used for both src and dest, or different regs (one for src, one for dest).
Likewise CR based twin predication has a second set of 3 bits, allowing a different test to be applied.
When the predicate mode bit is zero the 3 bits are interpreted as below.
Twin predication has an identical 3 bit field similarly encoded.
-| Value | Mnemonic | Description |
-|-------|----------|-----------------------------------------------------|
-| 000 | ALWAYS | Operation is not masked (mask set to all 1s) |
-| 001 | 1 << R3 | Reserved (causes an illegal instruction trap) |
-| 010 | R3 | Element `i` enabled if `R3 & (1 << i)` is non-zero |
-| 011 | ~R3 | Element `i` enabled if `R3 & (1 << i)` is zero |
-| 100 | R10 | Element `i` enabled if `R10 & (1 << i)` is non-zero |
-| 101 | ~R10 | Element `i` enabled if `R10 & (1 << i)` is zero |
-| 110 | R30 | Element `i` enabled if `R30 & (1 << i)` is non-zero |
-| 111 | ~R30 | Element `i` enabled if `R30 & (1 << i)` is zero |
+| MASK/MASK_SRC<br/>Value | Mnemonic | Description |
+|-------------------------|----------|--------------------------------------------------------|
- | 000 | ALWAYS | Operation is not masked see [[discussion]] |
++| 000 | ALWAYS | Operation is not masked (mask set to all 1s) |
+| 001 | 1 << R3 | Element `i` is enabled if `i == R3` |
+| 010 | R3 | Element `i` is enabled if `R3 & (1 << i)` is non-zero |
+| 011 | ~R3 | Element `i` is enabled if `R3 & (1 << i)` is zero |
+| 100 | R10 | Element `i` is enabled if `R10 & (1 << i)` is non-zero |
+| 101 | ~R10 | Element `i` is enabled if `R10 & (1 << i)` is zero |
+| 110 | R30 | Element `i` is enabled if `R30 & (1 << i)` is non-zero |
+| 111 | ~R30 | Element `i` is enabled if `R30 & (1 << i)` is zero |
-### CR based predication
+### CR-based Predication (MASK_KIND=1)
When the predicate mode bit is one the 3 bits are interpreted as below. Twin predication has an identical 3 bit field similarly encoded
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