platforms/lx9_microboard,usrp_b100: fix bitgen opts

diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py
index cbf03b3bf137e871dc087da6ea00ab3e6d25989e..077d0a0b2cd339e7fe78eee25032462403e9d031 100644 (file)
--- a/mibuild/platforms/lx9_microboard.py
+++ b/mibuild/platforms/lx9_microboard.py
@@ -110,8 +110,8 @@ class Platform(XilinxPlatform):
                self.add_platform_command("""
 CONFIG VCCAUX = "3.3";
 """)
-               self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
-               self.ise_commands = """
+               self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
+               self.toolchain.ise_commands = """
 promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
 """
 

diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py
index ac2edb49d4d3db97009ec1971b6808dd0369ae40..ff6413e09d5c7abf18af752310d6a16a3a3f2efe 100644 (file)
--- a/mibuild/platforms/usrp_b100.py
+++ b/mibuild/platforms/usrp_b100.py
@@ -118,7 +118,7 @@ class Platform(XilinxPlatform):
 
        def __init__(self):
                XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io)
-               self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
+               self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
 
        def do_finalize(self, fragment):
                XilinxPlatform.do_finalize(self, fragment)