arch-riscv: Move unknown out of ISA description

This patch removes the Unknown instruction type out of the ISA generated
code and puts it into arch/riscv/insts.  Since there isn't any dynamic
behavior to it, all that's left behind is a template for creating a new
Unknown instruction.

Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
Reviewed-on: https://gem5-review.googlesource.com/6023
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

diff --git a/src/arch/riscv/insts/bitfields.hh b/src/arch/riscv/insts/bitfields.hh
index 45744e0817a3c175eb9a08344a3da4e37fbc1250..d6648227e653f58eb52b5b48627019e198acc873 100644 (file)
--- a/src/arch/riscv/insts/bitfields.hh
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -5,5 +5,6 @@
 
 #define CSRIMM  bits(machInst, 19, 15)
 #define FUNCT12 bits(machInst, 31, 20)
+#define OPCODE  bits(machInst, 6, 0)
 
 #endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file

diff --git a/src/arch/riscv/insts/unknown.hh b/src/arch/riscv/insts/unknown.hh
new file mode 100644 (file)
index 0000000..049f879
--- /dev/null
+++ b/src/arch/riscv/insts/unknown.hh
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2015 RISC-V Foundation
+ * Copyright (c) 2017 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+
+#ifndef __ARCH_RISCV_UNKNOWN_INST_HH__
+#define __ARCH_RISCV_UNKNOWN_INST_HH__
+
+#include <memory>
+#include <string>
+
+#include "arch/riscv/faults.hh"
+#include "arch/riscv/insts/bitfields.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Static instruction class for unknown (illegal) instructions.
+ * These cause simulator termination if they are executed in a
+ * non-speculative mode.  This is a leaf class.
+ */
+class Unknown : public RiscvStaticInst
+{
+  public:
+    Unknown(MachInst _machInst)
+        : RiscvStaticInst("unknown", _machInst, No_OpClass)
+    {}
+
+    Fault
+    execute(ExecContext *, Trace::InstRecord *) const override
+    {
+        return std::make_shared<UnknownInstFault>();
+    }
+
+    std::string
+    generateDisassembly(Addr pc, const SymbolTable *symtab) const override
+    {
+        return csprintf("unknown opcode %#02x", OPCODE);
+    }
+};
+
+}
+
+#endif // __ARCH_RISCV_UNKNOWN_INST_HH__
\ No newline at end of file

diff --git a/src/arch/riscv/isa/formats/unknown.isa b/src/arch/riscv/isa/formats/unknown.isa
index b6d76497d1f032a57c75bf13620a9764894995ee..7c2317f9823646eab015bc410a4b986df4abc075 100644 (file)
--- a/src/arch/riscv/isa/formats/unknown.isa
+++ b/src/arch/riscv/isa/formats/unknown.isa
@@ -34,47 +34,6 @@
 //
 // Unknown instructions
 //
-
-output header {{
-    /**
-     * Static instruction class for unknown (illegal) instructions.
-     * These cause simulator termination if they are executed in a
-     * non-speculative mode.  This is a leaf class.
-     */
-    class Unknown : public RiscvStaticInst
-    {
-      public:
-        /// Constructor
-        Unknown(MachInst _machInst)
-            : RiscvStaticInst("unknown", _machInst, No_OpClass)
-        {
-            flags[IsNonSpeculative] = true;
-        }
-
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-    };
-}};
-
-output decoder {{
-    std::string
-    Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-    {
-        return csprintf("unknown opcode 0x%02x", OPCODE);
-    }
-}};
-
-output exec {{
-    Fault
-    Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
-    {
-        Fault fault = std::make_shared<UnknownInstFault>();
-        return fault;
-    }
-}};
-
 def format Unknown() {{
     decode_block = 'return new Unknown(machInst);\n'
 }};

diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa
index dfd0f37b427466e2d05b6d5d0664319ae1373d0a..cd43996e8115d9dd7bccb7f0f821c8ae5715ce1b 100644 (file)
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -44,6 +44,7 @@ output header {{
 
 #include "arch/riscv/insts/standard.hh"
 #include "arch/riscv/insts/static_inst.hh"
+#include "arch/riscv/insts/unknown.hh"
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"