[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transc...

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+Date: Tue, 05 May 2020 15:10:21 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: ALU (including IEEE754 16/32/64-bit FPU)
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
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+Message-ID: <bug-208-13-CE5GFBtkcC@https.bugs.libre-soc.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 208] implement CORDIC in a general way
+ sufficient to do transcendentals
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